JPH08124879A - Manufacture of mesa semiconductor device - Google Patents
Manufacture of mesa semiconductor deviceInfo
- Publication number
- JPH08124879A JPH08124879A JP25713394A JP25713394A JPH08124879A JP H08124879 A JPH08124879 A JP H08124879A JP 25713394 A JP25713394 A JP 25713394A JP 25713394 A JP25713394 A JP 25713394A JP H08124879 A JPH08124879 A JP H08124879A
- Authority
- JP
- Japan
- Prior art keywords
- mesa
- type semiconductor
- groove
- depth
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000011521 glass Substances 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 17
- 230000001681 protective effect Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Dicing (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はメサ型半導体装置の製造
方法に関し、詳しくはメサ溝の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a mesa type semiconductor device, and more particularly to a method for forming a mesa groove.
【0002】[0002]
【従来の技術】従来、電圧耐圧や高周波特性の良いダイ
オードやトランジスタ等の半導体装置を形成する場合に
は、図2に概要を示すような製造方法により形成してい
た。図2(a)はウェハを上面より見た状態を示し、図
2(b)乃至図2(e)は図2(a)をZ3−Z4で切
断した時の断面形状を示し、図2(f)は図2(a)の
ウェハを個々の半導体素子に分離した時の断面形状を示
す。2. Description of the Related Art Conventionally, in the case of forming a semiconductor device such as a diode or a transistor having a high voltage withstand voltage and a high frequency characteristic, it is formed by a manufacturing method as shown in FIG. 2A shows a state of the wafer viewed from the upper surface, and FIGS. 2B to 2E show cross-sectional shapes when the FIG. 2A is cut along Z3-Z4. 2F shows a sectional shape when the wafer of FIG. 2A is separated into individual semiconductor elements.
【0003】製造方法について説明する。図2における
半導体素子は、図2(b)に示すようにN型半導体基板
12の上面にP型半導体領域11を形成した後、図示し
ないレジスト膜を用いてエッチングすることにより、図
2(c)に示すようにP型半導体領域11とN型半導体
基板12を各素子単位に分離するための溝(以下メサ
溝)14を縦横にW3の幅で、D3の深さに形成し、図
2(d)に示すようにメサ溝14にガラス15を注入し
て約700℃の温度で焼成し、図2(e)に示すように
メサ溝14に露出するPN接合部13を覆うようにガラ
ス保護膜15aを形成する。最後に、メサ溝14の中央
部(点線で示す部分)をガラス保護膜15aの上からダ
イサ等によりスクライブして切断して、図2(f)に示
すような個々の半導体素子16に分離し、樹脂等により
封止して組立てることにより個別の半導体装置が完成す
る。A manufacturing method will be described. The semiconductor element in FIG. 2 is formed by forming a P-type semiconductor region 11 on the upper surface of an N-type semiconductor substrate 12 as shown in FIG. 2), a groove (hereinafter referred to as a mesa groove) 14 for separating the P-type semiconductor region 11 and the N-type semiconductor substrate 12 into respective element units is formed vertically and horizontally with a width W3 and a depth D3. As shown in FIG. 2D, the glass 15 is injected into the mesa groove 14 and baked at a temperature of about 700 ° C., and the glass is formed so as to cover the PN junction 13 exposed in the mesa groove 14 as shown in FIG. The protective film 15a is formed. Finally, the central portion (the portion indicated by the dotted line) of the mesa groove 14 is scribed and cut from above the glass protective film 15a with a dicer or the like to separate into individual semiconductor elements 16 as shown in FIG. 2 (f). Individual semiconductor devices are completed by assembling by sealing with resin or the like.
【0004】[0004]
【発明が解決しようとする課題】上述の半導体装置の製
造方法は、メサ溝14をエッチングにより形成する時、
溝の深さ方向と共に横方向に対してもエッチングされる
ために、メサ溝14を有しない半導体素子の分離領域
(スクライブラインという)に比べてメサ溝14の幅W
3を広くとる必要があるのでチップサイズが大きくな
り、一枚のウェハ10に形成できる半導体素子16の個
数が少なくなってしまうという問題がある。特に、高耐
圧の半導体装置を形成する場合には、メサ溝14の深さ
D3を深くする必要があるのでメサ溝14の幅W3が更
に広くなってチップサイズが大きくなるので、ウェハ当
たりの取れ数が更に少なくなるという問題があった。In the method of manufacturing a semiconductor device described above, when the mesa groove 14 is formed by etching,
Since the etching is performed not only in the depth direction of the groove but also in the lateral direction, the width W of the mesa groove 14 is larger than that of the isolation region (called a scribe line) of the semiconductor element having no mesa groove 14.
Since it is necessary to take 3 wide, there is a problem that the chip size becomes large and the number of semiconductor elements 16 that can be formed on one wafer 10 becomes small. In particular, when forming a high breakdown voltage semiconductor device, it is necessary to make the depth D3 of the mesa groove 14 deeper, so that the width W3 of the mesa groove 14 becomes wider and the chip size becomes larger. There was a problem that the number would be even smaller.
【0005】そこで本発明はこれらの問題を解決し、簡
単な製造工程を追加することによりメサ溝14の幅W3
を従来よりも広げることなくメサ溝14の深さD3のみ
を深くしたメサ型半導体装置を得られるようにして、メ
サ型半導体装置の電気的特性を向上すると共に、チップ
サイズを小さくすることにより、ウェハ10当たりの取
れ数を多くすることができるようにすることを目的とす
る。Therefore, the present invention solves these problems and adds a simple manufacturing process to increase the width W3 of the mesa groove 14.
By making it possible to obtain a mesa-type semiconductor device in which only the depth D3 of the mesa groove 14 is made deeper than before in order to improve the electrical characteristics of the mesa-type semiconductor device and reduce the chip size, It is an object to increase the number of wafers to be taken per wafer 10.
【0006】[0006]
【課題を解決するための手段】上記の問題を解決するた
めに、請求項1の記載に係わるメサ型半導体装置の製造
方法は、PN接合部を分離するためのメサ溝を有する半
導体装置の製造方法において、メサ溝となる部分に予め
カット溝を形成した後、メサ溝のエッチングを行うこと
を特徴とする。また、請求項2の記載に係わるメサ型半
導体装置の製造方法は、カット溝の深さがウェハの厚み
の半分以下であることを特徴とする。In order to solve the above problems, a method of manufacturing a mesa type semiconductor device according to a first aspect of the present invention is a method of manufacturing a semiconductor device having a mesa groove for separating a PN junction. In the method, the mesa groove is etched after the cut groove is formed in advance in the portion to be the mesa groove. Further, the method of manufacturing a mesa type semiconductor device according to a second aspect is characterized in that the depth of the cut groove is not more than half the thickness of the wafer.
【0007】[0007]
【作用】本発明のメサ型半導体装置の製造方法によれ
ば、メサ溝の幅を広くすること無く、メサ溝の深さのみ
を深くすることができるようになる。According to the method of manufacturing the mesa type semiconductor device of the present invention, only the depth of the mesa groove can be increased without increasing the width of the mesa groove.
【0008】[0008]
【実施例】以下、本発明の実施例であるメサ型半導体装
置の製造方法を図1を参照しながら詳細に説明する。
尚、本明細書では、全図面を通して、同一または同様の
部位には同一の符号を付して説明する。図1は本発明の
メサ型半導体装置の製造方法の概要を示し、図1(a)
はウェハを上面より見た状態を示し、図1(b)乃至図
1(f)は図1(a)のウェハ10をZ1−Z2で切断
した時の断面形状を示し、図1(g)は図1(a)のウ
ェハ10を個々の半導体素子16に分離した時の断面形
状を示す。尚、図1(a)では説明のために各半導体素
子16及びメサ溝14の大きさの割合を大きくして模式
的に表現している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a mesa type semiconductor device which is an embodiment of the present invention will be described in detail below with reference to FIG.
In the present specification, the same or similar parts will be denoted by the same reference symbols throughout the drawings. FIG. 1 shows an outline of a method for manufacturing a mesa type semiconductor device of the present invention, and FIG.
1B shows a state of the wafer viewed from above, FIGS. 1B to 1F show sectional shapes when the wafer 10 of FIG. 1A is cut along Z1-Z2, and FIG. Shows a sectional shape when the wafer 10 of FIG. 1A is separated into individual semiconductor elements 16. Note that, in FIG. 1A, for the sake of explanation, the ratio of the sizes of the semiconductor elements 16 and the mesa grooves 14 is enlarged and schematically represented.
【0009】製造方法について説明する。図1における
半導体装置は、図1(b)に示すようにN型半導体基板
12の上面にP型半導体領域11を形成した後、図示し
ないダイヤモンドブレードやレーザ光等によるダイシン
グにより、図1(c)に示すような溝(以下カット溝)
17をW1の幅で、D1の深さに図1(a)に示すよう
に縦横に形成してから、図示しないレジスト膜を用いて
エッチングすることにより、図1(d)に示すようにP
型半導体領域11とN型半導体基板12を各素子単位に
分離するための溝(以下メサ溝)14を縦横にW2の幅
で、D2の深さに形成し、図1(e)に示すようにメサ
溝14にガラス15を注入して約700℃の温度で焼成
し、図1(f)に示すようにメサ溝14に露出するPN
接合部13を覆うようにガラス保護膜15aを形成す
る。最後に、メサ溝14の中央部(点線で示す部分)を
ガラス保護膜15aの上からダイシングすることにより
切断して、図1(g)に示すような個々の半導体素子1
6に分離し、エポキシ樹脂やガラス等により封止して組
立てることにより個別の半導体装置が完成する。The manufacturing method will be described. The semiconductor device shown in FIG. 1 is formed by forming a P-type semiconductor region 11 on the upper surface of an N-type semiconductor substrate 12 as shown in FIG. ) Grooves shown below (hereinafter referred to as cut grooves)
17 is formed to have a width of W1 and a depth of D1 in the vertical and horizontal directions as shown in FIG. 1A, and then is etched using a resist film (not shown) to form P as shown in FIG.
A groove (hereinafter referred to as a mesa groove) 14 for separating the n-type semiconductor region 11 and the n-type semiconductor substrate 12 into respective element units is formed vertically and horizontally with a width of W2 and a depth of D2, as shown in FIG. Then, glass 15 is injected into the mesa groove 14 and baked at a temperature of about 700 ° C., and the PN exposed in the mesa groove 14 as shown in FIG.
The glass protective film 15a is formed so as to cover the bonding portion 13. Finally, the central portion (the portion indicated by the dotted line) of the mesa groove 14 is cut by dicing from above the glass protective film 15a, and the individual semiconductor elements 1 as shown in FIG.
Individual semiconductor devices are completed by separating into 6 and assembling by sealing with epoxy resin or glass.
【0010】上述の製造方法は、予めカット溝17を形
成してからメサ溝14をエッチングするので、予め幅方
向に比べて深さ方向を大きくエッチングしたことと同様
になり、その後に従来と同様のエッチングを行えば、従
来に比べてカット溝17の深さの分だけ深さ方向のみに
深いメサ溝14が形成されることになる。尚、ガラス保
護膜15aは、PN接合部13に水やその他の不要な導
電物質が付着して半導体素子にリーク電流が発生するの
を防止する役目を果たしている。In the above-described manufacturing method, since the cut groove 17 is formed in advance and then the mesa groove 14 is etched, it becomes the same as that in which the depth direction is larger than the width direction in advance. If the etching is performed, the mesa groove 14 which is deeper than the conventional one by the depth of the cut groove 17 is formed only in the depth direction. The glass protective film 15a has a function of preventing water and other unnecessary conductive substances from adhering to the PN junction 13 and generating a leak current in the semiconductor element.
【0011】カット溝17の幅W1はダイシング用の歯
(ブレード)の厚みにより決定され、本実施例では約3
0μmとなっている。また、カット溝17形成によりウ
ェハ10の機械的強度が大幅に低下して製造途中でウェ
ハ10が割れたり欠けたりするのを防ぐために、カット
溝17の深さD1及びメサ溝14の深さD2はウェハ1
0の厚みの半分以下の数10μm乃至200μm程度の
深さに形成するのが好ましく、本実施例では約40μm
としている。カット溝17の深さD1を一定に保つた
め、ウェハ毎やダイシング前後等に適時ブレードの大き
さを測定するようにするか、カット溝17の深さをレー
ザ光等により測定し、ブレードの位置を調整するように
すると良い。また、深さ方向のエッチング速度が横方向
のエッチング速度よりも速くなるような結晶方向をもつ
ウェハを用いると、カット溝17の深さを余り深くする
必要がないので更に効果的である。The width W1 of the cut groove 17 is determined by the thickness of the tooth (blade) for dicing, and is about 3 in this embodiment.
It is 0 μm. Further, in order to prevent the mechanical strength of the wafer 10 from being significantly reduced due to the formation of the cut groove 17 and the wafer 10 from being cracked or chipped during manufacturing, the depth D1 of the cut groove 17 and the depth D2 of the mesa groove 14 are prevented. Is wafer 1
It is preferable to form it to a depth of about several tens of μm to 200 μm, which is less than half of the thickness of 0, and is about 40 μm in this embodiment.
And In order to keep the depth D1 of the cut groove 17 constant, the size of the blade should be measured at appropriate times for each wafer, before and after dicing, or the depth of the cut groove 17 should be measured by laser light or the like to determine the position of the blade. Should be adjusted. Further, it is more effective to use a wafer having a crystallographic direction such that the etching rate in the depth direction is higher than the etching rate in the lateral direction, because it is not necessary to make the depth of the cut groove 17 too deep.
【0012】本実施例では、ダイシングを行った後に図
示しないレジスト膜を用いてメサ溝14をエッチングす
るようにしているが、レジスト膜を形成した後にダイシ
ングを行うようにしても良い。In this embodiment, the mesa groove 14 is etched using a resist film (not shown) after the dicing, but the dicing may be performed after the resist film is formed.
【0013】[0013]
【発明の効果】以上に詳細を説明したように本発明によ
れば、メサ溝14の幅W2を従来よりも広げることなく
メサ溝の深さD2のみを深くしたメサ型半導体装置を得
ることができるようになるので、電圧耐圧や高周波特性
の良いダイオードやトランジスタ等のメサ型半導体装置
が、従来の製造方法に比べてウェハ当たりの取れ数を多
くしながら形成することができるようになり、半導体素
子16のコストダウンができるという効果がある。As described above in detail, according to the present invention, it is possible to obtain a mesa-type semiconductor device in which only the depth D2 of the mesa groove is increased without increasing the width W2 of the mesa groove 14 as compared with the conventional case. As a result, it becomes possible to form mesa-type semiconductor devices such as diodes and transistors having good withstand voltage and high frequency characteristics while increasing the number of wafers per wafer as compared with the conventional manufacturing method. There is an effect that the cost of the element 16 can be reduced.
【図1】 本発明の製造方法の概要フローを示す説明図
である。FIG. 1 is an explanatory diagram showing a schematic flow of a manufacturing method of the present invention.
【図2】 従来の製造方法の概要フローを示す説明図で
ある。FIG. 2 is an explanatory diagram showing a schematic flow of a conventional manufacturing method.
10 :半導体ウェハ 11 :P型半導体領域 12 :N型半導体基板 13 :接合部 14 :溝(メサ溝) 15a:ガラス保護膜 16 :個別半導体素子 17 :カット溝 10: Semiconductor wafer 11: P-type semiconductor region 12: N-type semiconductor substrate 13: Bonding part 14: Groove (mesa groove) 15a: Glass protective film 16: Individual semiconductor element 17: Cut groove
Claims (2)
する半導体装置の製造方法において、メサ溝となる部分
に予めカット溝を形成した後、前記メサ溝のエッチング
を行うことを特徴とするメサ型半導体装置の製造方法。1. A method of manufacturing a semiconductor device having a mesa groove for separating a PN junction, wherein a cut groove is formed in advance in a portion to be a mesa groove, and then the mesa groove is etched. Manufacturing method of mesa type semiconductor device.
分以下であることを特徴とする請求項1に記載のメサ型
半導体装置の製造方法。2. The method of manufacturing a mesa type semiconductor device according to claim 1, wherein the depth of the cut groove is not more than half the thickness of the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25713394A JPH08124879A (en) | 1994-10-21 | 1994-10-21 | Manufacture of mesa semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25713394A JPH08124879A (en) | 1994-10-21 | 1994-10-21 | Manufacture of mesa semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08124879A true JPH08124879A (en) | 1996-05-17 |
Family
ID=17302187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25713394A Pending JPH08124879A (en) | 1994-10-21 | 1994-10-21 | Manufacture of mesa semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08124879A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0948036A3 (en) * | 1998-03-30 | 2002-03-20 | GENERAL SEMICONDUCTOR, Inc. | Method for forming semiconductor chips with a mesa structure by sawing |
| JP2010109015A (en) * | 2008-10-28 | 2010-05-13 | Panasonic Electric Works Co Ltd | Method of manufacturing semiconductor light-emitting element |
| CN104217996A (en) * | 2013-05-29 | 2014-12-17 | 力神科技股份有限公司 | Plateau structure forming method of semiconductor substrate |
| CN111319345A (en) * | 2018-12-14 | 2020-06-23 | 天津环鑫科技发展有限公司 | TVS chip glass passivation screen printing plate and process method thereof |
-
1994
- 1994-10-21 JP JP25713394A patent/JPH08124879A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0948036A3 (en) * | 1998-03-30 | 2002-03-20 | GENERAL SEMICONDUCTOR, Inc. | Method for forming semiconductor chips with a mesa structure by sawing |
| JP2010109015A (en) * | 2008-10-28 | 2010-05-13 | Panasonic Electric Works Co Ltd | Method of manufacturing semiconductor light-emitting element |
| US8399272B2 (en) | 2008-10-28 | 2013-03-19 | Panasonic Corporation | Method of manufacturing semiconductor light emitting element |
| TWI424588B (en) * | 2008-10-28 | 2014-01-21 | 松下電器產業股份有限公司 | Semiconductor light emitting device manufacturing method |
| CN104217996A (en) * | 2013-05-29 | 2014-12-17 | 力神科技股份有限公司 | Plateau structure forming method of semiconductor substrate |
| CN111319345A (en) * | 2018-12-14 | 2020-06-23 | 天津环鑫科技发展有限公司 | TVS chip glass passivation screen printing plate and process method thereof |
| CN111319345B (en) * | 2018-12-14 | 2021-05-14 | 天津环鑫科技发展有限公司 | TVS chip glass passivation screen printing plate and process method thereof |
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