JPH08129886A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To facilitate the inspection of a circuit device by normally connecting an address terminal to a control circuit and to an address buffer and by connecting a control terminal to the control circuit and also the address terminal to the address buffer with a switching circuit at the time of a testing operation. CONSTITUTION: At the time of a normal and inspecting operations, a high voltage detector 13 detects the voltage of a detection terminal TE1 on which different voltages are impressed and a switching circuit SW is changed over with a changeover signal SS. Then, at the time of a normal operation, an address signal and an automatic precharge (an AP) signal inputting from an address pin A8 are distributed to an address buffer 11 and an AP controller 12 with a time division. Besides, at the time of testings such as bun-in test and so forth, the address signal and the AP signal are respectively inputted from the pin A8 to the buffer 11 and from a control terminal TE2 to a controller 12 by being isolated. Thus, a complex control is not necessitated, the creation of an inspecting program and the execution of the inspection are facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a synchronous DRAM (Synchr
onous DRAM) improvement.

[0002]

2. Description of the Related Art A synchronous DR according to a conventional example will be described below.
AM will be described with reference to the drawings. In recent years, a DRAM called a synchronous DRAM has been proposed in a computer in order to cope with an increase in CPU speed. This is the same as RAS (Row Addr
This is a DRAM that speeds up by reading and writing data in synchronization with the clock without reading and writing the data based on signals unrelated to the clock such as ess select) and CAS (Column Address Select). is there.

The circuit of the input / output unit is shown in FIG. FIG.
FIG. 6 is a circuit diagram showing a part of an input / output unit of a conventional synchronous DRAM. As shown in FIG. 4, the conventional synchronous DRAM has an address pin (A8) provided externally.
And an address buffer (1) and an auto precharge controller (2). Either the row address (RA8) or the auto precharge signal (AP) is input to the externally provided address pin (A8) in a time division manner, and the row address (RA8) is input to the address buffer (1). Then, the voltage level is converted and output to a decoder (not shown).

When an auto precharge signal (AP) is input to the auto precharge controller (2), the synchronous DRAM is automatically precharged in the next cycle. Normal synchronous DRAM
Among the address pins, one of the address pins serves as a row address input pin and also as an input pin of a signal for designating auto precharge (DRAM is automatically precharged in the next cycle).

For example, in the case of a 2M synchronous DRAM which has 10 address pins A0 to A9 and is divided into two banks, row / column addresses are input to A0 to A7. The A9 pin is a pin to which a signal for deciding which bank out of the two banks is selected is input, but the A8 pin controls the row address (RA8) and auto precharge. It is shared with both pin and row address (RA8) in time division.
The input pin or the control pin for auto-precharge is switched.

The detailed operation will be described with reference to the timing chart of FIG. First, the clock (CLK)
RAS (Row Address S
trobe) is input to the address buffer (1) in FIG. At the same time, a row address is input to each address pin (A0 to A9) and each word line is activated.

Then, in synchronization with the next rise of the clock (CLK), CAS (Column Address Strobe) falls to "L", a column address is designated, and data is read out. In the case where auto precharge is performed in the next cycle, the auto precharge signal (AP) of "H" from the address pin (A8) is synchronized with the fall of CAS to "L". Input to (2). When this signal is input, the auto precharge controller automatically precharges the DRAM after reading is completed.

When auto precharge is not performed in the next cycle, when CAS becomes "L", the auto precharge signal (AP) of "L" is sent from the address pin (A8) to the auto precharge controller (2). It is input and auto precharge is not performed in the next cycle. As described above, in a normal synchronous DRAM, at least one address pin is connected to the row address input pin,
It also serves as an input pin for the auto precharge designation signal, and this was switched in time division to perform auto precharge.

[0009]

However, the conventional synchronous DRAM described above has the following problems. That is, when the synchronous DRAM is inspected by actually operating it at the package stage to check the quality, as described above, in such a synchronous DRAM, the A8 pin is used for both auto precharge and address. The complicated operation of switching this in a time-division manner requires a complicated control program for the inspection as described above, which makes it difficult to perform the inspection. was there.

[0010] As such an inspection, there is an inspection called a burn-in test in which a DRAM at a packaging stage is put in a high temperature tank and an actual operation is performed at a high temperature. For the sake of testing
Since the control program for inspection is relatively simple, the burn-in test of the synchronous DRAM, which requires complicated operations as described above, is particularly difficult.

[0011]

The present invention has been made in view of the above-mentioned drawbacks of the prior art. As shown in FIG. 1, a control terminal to which a control signal is input, and the semiconductor integrated circuit based on the control signal are provided. A control circuit for controlling the circuit device, an address terminal to which the control signal and the address are input, an address buffer, and the address terminal, the control circuit and the address buffer are connected during a normal operation, and a test operation is performed. Sometimes, by having a switching circuit that connects the control terminal and the control circuit and also connects the address terminal and the address buffer, it is possible to simplify the inspection program for controlling the inspection device, and to perform various inspections. A semiconductor integrated circuit device that can be easily implemented.

[0012]

[Operation] According to the semiconductor integrated circuit device of the present invention,
As shown in FIG. 1, during normal operation, the address terminal is connected to a control circuit such as an auto precharge controller and an address buffer, and during test operation, the control terminal and the control circuit are connected, and the address terminal and the address buffer are connected. And a switching circuit for connecting

Therefore, during the normal operation, both the address signal and the control signal such as the auto-precharge signal are input from the address pin as in the conventional case, and one pin is allocated to the address buffer and the control circuit by time division. Further, during the test operation, it is possible to separately input the address signal from the address pin to the address buffer, the control signal such as auto precharge from the control terminal to the control circuit, and so on.

As a result, at the time of inspection, the pin to which the control signal is input and the pin to which the address signal is input are separated from each other. Therefore, the same pin is assigned to each function in a time division manner. There is no need to do it. Therefore, it is easy to create an inspection program, and the inspection can be performed easily. In particular, it is effective for an inspection using an inspection device that operates with a simple control program such as a burn-in test.

In the present invention, different voltages are applied during normal operation and during inspection, and a detection terminal provided outside and the voltage applied to the detection terminal are detected to perform switching operation of the switching circuit. It has a detection circuit for controlling.
Therefore, for example, if it is set so that the switching circuit operates at the above-described normal operation at a predetermined voltage or higher, and operates at the inspection at the predetermined voltage or lower, it is detected from the outside depending on the situation. By applying a voltage to the terminals, the switching circuit can be easily switched.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A synchronous DRAM according to an embodiment of the present invention will be described below with reference to the drawings. The synchronous DRAM according to the present embodiment is a DRAM having a storage capacity of 2 Mbytes which is divided into two banks.
As shown in FIG. 2, the synchronous DRAM has an address buffer (11), an auto precharge controller (12), a high voltage detector (13), and
It has an input / output circuit including a detection terminal (TE1), a control terminal (TE2), an address pin (A8), and a switching circuit (SW).

The address buffer (11) converts the voltage level of an input address and outputs it to a decoder (not shown). The auto precharge controller (12) is an example of a control circuit. When the auto precharge signal (AP) is input, the auto precharge controller (12) automatically precharges the synchronous DRAM in the next cycle.

The high voltage detector (13) is an example of a detection circuit, detects a voltage applied to the detection terminal (TE1), and outputs a switching signal (SS) of "H" when the voltage is equal to or higher than a predetermined threshold value. Switching circuit (S
W), and outputs a switching signal (SS) of “L” to the switching circuit (SW) when it is less than or equal to the threshold.

The switching circuit (SW) connects the address pin (A8) to the address buffer (11) during normal operation.
And the auto precharge controller (12), and during the test operation, the address pin (A8) is connected to the address buffer (11) and the control terminal (TE2) is connected to the auto precharge controller (12). .

Note that the control terminal (TE2) connected to the switching circuit (SW) and provided outside the synchronous DRAM has an auto pre-charge for designating auto pre-charging of the DRAM during a test operation. The charge signal (AP) is input and the address buffer (1
1) and a switching circuit (SW), and an address pin (A) provided outside the synchronous DRAM.
In 8), either the auto precharge signal (AP) or the row address (RA8) is input.

The operation of the above circuit is divided into an operation at the time of inspection such as a burn-in test and an operation at the normal operation, and will be described below with reference to the timing charts of FIGS. (1) Operation during inspection In this case, a high voltage is first applied to the detection terminal (TE1), and this high voltage is applied to the high voltage detector (13).
Is detected, and as a result, the switching signal (SS) of "H" is output to the switching circuit (SW).

Upon receipt of this "H" switching signal (SS), the switching circuit (SW) switches, and the control terminal (TE2) and the auto precharge controller (12).
, And the address pin (A8) and the address buffer (11) are connected. At this time, only the row address (RA8) is input to the external address pin (A8) from the external test device (not shown), and the control terminal (TE).
Only the auto precharge signal (AP) is input to 2).

Therefore, the row address is the address pin (A8).
Is input to the address buffer (11), converted into a voltage level, and output to a decoder (not shown). Further, the auto precharge signal (AP) is input to the auto precharge controller (12) via the control terminal (TE2) and is not input via the address pin (A8) as in the conventional case.

In this way, when the auto precharge signal (AP) is input to the auto precharge controller (12), the synchronous DRA in the next cycle is input.
M is automatically precharged. Therefore, during such a test operation, the row address (RA8) and the auto precharge signal (A8) are supplied to the address pin (A8) as in the conventional case.
Both P and P are input, and a complicated operation of switching and operating in time division is not required.

The details of the operation will be described with reference to the timing chart of FIG. First, the clock (CLK)
RAS (Row Address S
trobe) is input to the address buffer (11). At the same time, a row address is input to each address pin (A0 to A9) and the word line is activated.

Then, in synchronization with the next rising edge of the clock (CLK), CAS (Column Address Strobe) becomes "L", a column address is designated, and data is read out. At this time, when auto precharge is performed in the next cycle, when CAS becomes "L", the auto precharge signal (AP) of "H" is sent from the address pin (A8) to the auto precharge controller (AP). 12) is input. When this signal is input, the auto precharge controller (12) causes the DRAM to execute auto precharge after the reading is completed.

When the automatic precharge is not performed after the reading is completed, the automatic precharge signal (AP) of "L" is sent to the address pin (A) when CAS becomes "L".
It is input to the auto precharge controller (12) from 8) and the auto precharge of the DRAM is not executed after the reading is completed. (2) Operation during normal operation In this case, first, a low voltage is applied to the detection terminal (TE1), and this low voltage is applied to the high voltage detector (13).
Is detected, and as a result, the switching signal (SS) of "L" is output to the switching circuit (SW).

Upon receipt of this "L" switching signal (SS), the switching circuit (SW) is switched, and the control terminal (TE2) is switched to the auto precharge controller (12).
And the address pin (A8) is connected to the address buffer (11) and the auto precharge controller (12). In this case, both the row address (RA8) and the auto precharge signal (AP) are input to the address pin (A8) in the same manner as in the conventional case,
It operates by switching in time division.

The rest of the operation is similar to that described above. That is, the address pin (A8) provided outside is
Row address (RA8) and auto precharge signal (A
P) is input in a time division manner and the row address (RA8) is input to the address buffer (1), the voltage level is converted and output to a decoder (not shown). When the auto precharge signal (AP) is input to the auto precharge controller (2), the synchronous DRAM is automatically precharged in the next cycle.

The detailed operation will be described with reference to the timing chart of FIG. First, the clock (CLK)
The RAS of "L" is input to the address buffer (11) in synchronization with the rising edge of. At the same time, a row address is input to each address pin (A0 to A9) and the word line is activated.

Then, CAS becomes "L" in synchronization with the next rising edge of the clock (CLK), a column address is designated, and data is read out. In the case where auto precharge is performed in the next cycle, an auto precharge signal (AP) of "H" is sent from the address pin (A8) to the auto precharge controller (12) when CAS becomes "L". Is entered. When this signal is input, the auto precharge controller causes the DRAM to auto precharge after the reading is completed.

When the automatic precharge is not performed after the reading is completed, the automatic precharge signal (AP) of "L" is sent to the address pin (A) when CAS becomes "L".
8) is input to the auto precharge controller (12), and auto precharge is not performed after the reading is completed. As described above, in the synchronous DRAM according to the present embodiment, the switching circuit (SW) is switched, so that in the normal operation, both the address and the auto precharge signal (AP) have the address pin ( A8), the address buffer (11) and the auto precharge controller (1
One address pin (A8) can be assigned to 2), and on the other hand, during test operation such as burn-in test,
The address is sent from the address pin (A8) to the address buffer (11), and the auto precharge signal (AP) is sent from the control terminal (TE2) to the auto precharge controller (1).
2) and can be input separately.

As a result, at the time of inspection, the pin to which the auto precharge signal (AP) is input and the pin to which the address is input are separated, so that the same pin is assigned to each function in a time division manner. Since it is not necessary to perform complicated control, it is easy to create a program for inspection and it is easy to perform inspection. In particular, it is effective for an inspection using an inspection device that operates with a simple control program such as a burn-in test.

Further, according to the present embodiment, the detection terminal (TE1) to which different voltages are applied during the normal operation and the inspection.
And detecting the voltage applied to the detection terminal (TE1),
It has a high voltage detector (13) for controlling the switching operation of the switching circuit (SW). For this reason,
For example, if the switching circuit (SW) operates above the normal operation above a predetermined voltage and operates below the inspection above a predetermined voltage, it is necessary even at the packaging stage. Depending on the external detection terminal (T
It becomes possible to easily switch the switching circuit (SW) by applying a voltage to E1).

Although it seems that it is necessary to provide the control terminal (TE2) in the above-mentioned synchronous DRAM, in reality there are pins that are not normally used in the semiconductor integrated circuit device such as the synchronous DRAM, that is, so-called empty pins. Therefore, if this is used, it is possible to implement without the need to provide a special pin. In this embodiment, the auto precharge controller is used as an example of the control circuit, but the present invention is not limited to this, and any control circuit for controlling the synchronous DRAM can be used. Even a circuit has the same effect.

Further, in this embodiment, the synchronous DRA is used.
Although M has been described, the present invention is not limited to this, and any semiconductor integrated circuit device such as a Rambus DRAM in which a control terminal and an address pin are shared can be used. Produce the effect of.

[0037]

As described above, according to the semiconductor integrated circuit device of the present invention, the address terminal is connected to the control circuit and the address buffer during the normal operation, and the control terminal and the control circuit are connected during the test operation. And a switching circuit that connects the address terminal and the address buffer.

As a result, at the time of inspection, the pin to which the control signal is input and the pin to which the address signal is input are separated from each other. Therefore, it is necessary to perform the complicated control of allocating the same pin to each function in a time division manner. Since it is eliminated, it becomes easy to create a program for inspection, and it becomes easy to perform inspection. In particular, it is effective for an inspection using an inspection device that operates with a simple control program such as a burn-in test.

In the present invention, a detection terminal to which a different voltage is applied during normal operation and an inspection and a detection circuit for detecting the voltage applied to the detection terminal and controlling the switching operation of the switching circuit are provided. Have. Therefore, for example, if it is set so that the switching circuit operates at the above-described normal operation at a predetermined voltage or higher, and operates at the inspection at the predetermined voltage or lower, it is detected from the outside depending on the situation. By applying a voltage to the terminals, the switching circuit can be easily switched.

[Brief description of drawings]

FIG. 1 is a principle diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an input / output unit of the synchronous DRAM according to the embodiment of the present invention.

FIG. 3 is a timing chart explaining the operation of the synchronous DRAM according to the embodiment of the present invention.

FIG. 4 is a configuration diagram of a semiconductor integrated circuit device according to a conventional example.

FIG. 5 is a diagram illustrating a configuration of an input / output unit of a general synchronous DRAM.

[Explanation of symbols]

 (11) Address buffer (12) Auto precharge controller (13) High voltage detector (SW) Switching circuit (TE1) Detection terminal (TE2) Control terminal (A8) Address pin (SS) Switching signal (RA8) Row address (AP ) Auto precharge signal

Claims (3)

[Claims] 1. A control terminal to which a control signal is input, a control circuit which controls the semiconductor integrated circuit device based on the control signal, an address terminal to which the control signal and an address are input, and an address buffer. And a switching circuit that connects the address terminal to the control circuit and the address buffer during normal operation, connects the control terminal to the control circuit during test operation, and connects the address terminal to the address buffer. A semiconductor integrated circuit device comprising: 2. A switching operation of the switching circuit is controlled by detecting a voltage applied to the externally provided detection terminal and the detection terminal to which different voltages are applied during normal operation and during inspection. The semiconductor integrated circuit device according to claim 1, further comprising a detection circuit. 3. The semiconductor integrated circuit device according to claim 1, wherein the control circuit is an auto precharge controller that controls auto precharge of the semiconductor integrated circuit device.