JPH08147013A - Programmable controller - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the data transfer time and PC scan execution time. [Structure] A CPU 1 for executing a sequence command, a sequence program memory 4 for storing the sequence command,
A sequence instruction having an I / O register as an operand, which decodes a sequence instruction executed by the CPU, and a CPU
Instruction word decoding circuit 5 for detecting the type of instruction specified by
And a command control circuit 6 for controlling input / output of data to / from the input / output register, and a data buffer 7 indicating permission / non-permission of writing to the input / output register and the data transfer instruction flag.
A data coincidence detection circuit 8 for determining whether the data existing in the input / output register and the write data after execution of the sequence instruction are the same; the input / output register 9 for storing transfer data with the input / output module; and the input / output module. And a data transfer instruction flag 10 for instructing whether or not to execute data transfer between them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller widely used for controlling industrial systems such as steel, public systems such as paper manufacturing plants and water and sewage systems, and automobile industry.

[0002]

2. Description of the Related Art Programmable controllers (hereinafter referred to as P
(Abbreviated as C) is usually an input module that converts the state of the controlled object into an electric signal and inputs it, and converts the electric signal into a signal level suitable for the peripheral device in order to operate an actuator or the like for controlling the controlled object. Have an output module that
An input / output module (hereinafter abbreviated as I / O) sends and receives an electrical signal as data from a PC via an I / O bus.

As shown in FIG. 6, the input / output modules and input / output registers of the PC have a one-to-one correspondence, and the result of the sequence program executed by the PC is temporarily written in the output register, and a series of programs are created. After being executed
The data is collectively output to the output module. Also, P
External data used by C in the program is input to the input register from the input module before the program is executed, and the contents of the input register are used when the program is executed. Such collective transfer between the input / output register and the input / output module during the execution of the program is called collective input / output.

[0004]

Generally, a medium-sized PC uses about 1000 I / O points. In order to execute input / output of this point, data transfer of 64 words (1 word = 16 bits) is usually required. The I / O data transfer time is usually about 100 times slower than the memory data transfer time, and the batch input / output time is a heavy load for scan execution. Furthermore, in an intelligent I / O such as a transmission module, the occupied input / output register is 1
Since it is about 000 words, the influence is particularly great.

The present invention has been made in view of the above circumstances. In data transfer between an input / output register of a PC and an input / output module, an operand of a sequence instruction is monitored during execution of a program, and execution of a CPU is executed. An object of the present invention is to reduce the data transfer time and the scan execution time of the PC by determining the state and detecting the input / output register that needs the data transfer and minimizing the data transfer amount.

[0006]

In order to achieve the above object, in a programmable controller according to claim 1 of the present invention, an input / output register for storing transfer data with an input / output module and an internal input / output register A data transfer instruction flag corresponding to each register and instructing whether or not to execute data transfer with the input / output module, a CPU executing a sequence instruction, and a sequence instruction executed by the CPU are decoded to Based on the output of the instruction decode circuit and the sequence instruction execution state of the CPU, a sequence instruction using a write output register as an operand and an instruction decode circuit for detecting an instruction of the type specified by the CPU A command control circuit for controlling data input / output, the input / output register and the data transfer instruction flow Data buffer that indicates whether or not writing to the memory is permitted, and when the CPU executes the sequence instruction, the data match detection that determines whether the data existing in the input / output register and the write data after the execution of the sequence instruction are the same. And a circuit.

In a programmable controller according to a second aspect of the present invention, in the programmable controller according to the first aspect, the sequence instruction detected by the instruction decoding circuit is a sequence instruction whose operand is a write operation in an input / output register. By doing so, the command control circuit and the data buffer read data from the corresponding input / output register and compare it with the write data from the CPU to determine whether the content of the input / output register has changed. The data transfer instruction flag is set in the input / output register when it is changed, and the data transfer instruction flag is set when data is exchanged between the input / output register and the input / output module. I / O module only for registered I / O registers And executes the data transfer between.

In a programmable controller according to a third aspect of the present invention, in the programmable controller according to the first aspect, the sequence instruction detected by the instruction decoding circuit is a sequence instruction whose operand is a read operation in an input / output register. As a result, the data transfer flag is set only in the I / O register used in the sequence program, and the data transfer is executed only from the I / O module corresponding to the I / O register in which the data transfer flag is set. Characterize.

In a programmable controller according to a fourth aspect of the present invention, in the programmable controller according to the first aspect, the sequence instruction detected by the instruction decoding circuit when executing the step step sequence program is executed. , Which has an input / output register as an operand, is a transition condition determination instruction between steps, and further determines the sequence instruction execution state of the CPU, so that only when the step is currently in a state in which there is a possibility of transition, By setting the data transfer instruction flag in the I / O register used by the sequence instruction, in the step-progressing type program, only the portion that may have a transition,
By inputting necessary data from the input / output module, the amount of data transfer is reduced, the data transfer time is shortened, and sequence execution is performed at high speed.

In a programmable controller according to a fifth aspect of the present invention, in the programmable controller according to the first aspect, an output port capable of designating an output from the CPU is provided, and the output signal of the output port is the instruction decoding circuit. The data transfer instruction flag is arbitrarily set in accordance with the output signal of the output port and the data is forcedly updated in the input / output register in the range designated by the CPU. .

In a programmable controller according to a sixth aspect of the present invention, in the programmable controller according to the fifth aspect, an I / O address determination circuit for determining the range of the input / output register corresponding to a specific I / O module. Is provided and the output of the I / O address determination circuit is used as the input of the command control circuit.
It is characterized by forcibly permitting / prohibiting the data update between the input / output register corresponding to and the I / O module according to the instruction of the CPU.

[0012]

In the programmable controller according to the first aspect of the present invention, in the PC which executes data transfer via the external I / O and the input / output register, the sequence instruction executed by the CPU is constantly monitored and input / output is performed. An input / output register is provided with an instruction decode circuit that detects a sequence instruction using a register as an operand and a specific instruction specified by the CPU, and comprehensively determines the output of this instruction decode circuit and the sequence instruction execution state inside the CPU, CPU to control the data buffer connected to the input / output register by giving an instruction to the command control circuit that controls the input / output of data to / from
Detects whether the data originally existing in the I / O register when writing the execution result of the sequence instruction to the I / O register is the same as the write data after execution of the sequence command, and if the data changes, When the data transfer instruction flag is set and data is exchanged between the input / output register and the input / output module, only the input / output register for which the data transfer instruction flag is set The data transfer time can be shortened by executing the transfer.

In a programmable controller according to a second aspect of the present invention, when the CPU executes a sequence instruction, if the operand is an input / output register and a write operation, the command control circuit and the data are written. By reading the data from the corresponding I / O register by the buffer and comparing it with the write data from the CPU, it is judged for each I / O register whether or not the contents of the I / O register have changed. When the data transfer instruction flag is set in the output register and data is exchanged between the input / output register and the input / output module, only the input / output module with the data transfer instruction flag set The data transfer time is shortened by executing data transfer between .

In the programmable controller according to claim 3 of the present invention, the sequence instruction detected by the instruction decoding circuit is a sequence instruction having an input register as an operand, so that the input register used in the sequence program A data transfer time between the input / output module and the input / output register is shortened by setting the data transfer flag only and executing the data transfer only from the input module corresponding to the input register.

In the programmable controller according to the fourth aspect of the present invention, the sequence instruction detected by the instruction decoding circuit when executing the step step sequence program has an input / output register as an operand.
By determining the transition condition between steps and determining the sequence instruction execution state of the CPU, the input / output registers used by the sequence instruction can be changed only when the step is currently in a state in which there is a possibility of transition. By setting the data transfer instruction flag, the data transfer amount can be reduced by inputting the necessary data from the input / output module only for the parts that may have transitions in the process step program. The feature is that the transfer time is shortened and the sequence is executed at high speed.

In a programmable controller according to a fifth aspect of the present invention, an output port capable of designating an output from a CPU is provided, and an output signal of the output port is used as an input of the instruction decoding circuit, and an output signal of the output port is output. According to the above, by configuring the data transfer instruction flag to be arbitrarily set, the CPU is configured to forcibly update the data of the input / output register in the range specified, and thus it was not used in the scan execution. The feature is that data transfer with the input / output module corresponding to the input / output register is also possible.

In the programmable controller according to claim 6 of the present invention, an I / O address judging circuit for judging the range of the input / output register corresponding to a specific I / O module is provided, and the output of the I / O judging circuit is provided. Is input to the command control circuit, the data update between the I / O module and the I / O module corresponding to the specific I / O is forcibly permitted / inhibited by the instruction of the CPU. The data transfer time is shortened by permitting and prohibiting data transfer with an intelligent I / O module having a large-capacity input / output register according to the usage status of the module.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the main structure of the present invention.
In FIG. 1, the programmable controller decodes the sequence instruction executed by the CPU, the CPU 1 for executing the sequence instruction, the CPU bus 2, the system memory 3, the sequence program memory 4 for storing the sequence instruction, and the input / output. An instruction word decoding circuit 5 for detecting a sequence instruction having a register as an operand and an instruction of a type designated by the CPU, a command control circuit 6 for controlling input / output of data to / from the input / output register, an input / output register and a data transfer instruction. A data buffer 7 indicating whether or not writing to the flag is permitted, a data match detection circuit 8 for determining whether the data existing in the input / output register and the write data after execution of the sequence instruction are the same, and the transfer data between the input / output module Between the I / O register 9 that stores A data transfer instruction flag 10 for indicating whether or not to execute data transfer, the I / O bus buffer 11, the I / O bus 12, the I / O modules 13,
The output port 14 and the I / O address determination circuit 15.

The data transfer instruction flag 10 has a one-to-one correspondence with the register in the input / output register 9 as shown in FIG. In the present embodiment, the CPU 1 has a sequence operation circuit 16 and a bit accumulator 17 that expresses ON / OFF of the sequence circuit 16. CPU1
Inputs data from the I / O module 13 and stores it in the input / output register 9. After that, the sequence instruction is read from the sequence program memory 4 and the sequence operation circuit 16 performs the operation. The output state of the sequence circuit is stored in the bit accumulator 17. Among the sequence instructions, the result output to the input / output module is that the data is written in the input / output register 9 and is output to the input / output module 13 at the time of batch input / output after the execution of the sequence program. The sequence program is executed by repeating the above operation.

Here, when the sequence instruction is read from the sequence program memory 4, the instruction code is input not only to the CPU 1 but also to the instruction word decoding circuit 5 so that the operand of the sequence instruction is a write signal of the input / output register. Let me judge. At this time, the command decoding circuit 5 outputs an operation start signal to the command control circuit 6. In this state, the command control circuit 6 is the CPU
When the write signal is output from 1, the command signal as shown in the timing chart of FIG. 3 is generated and output to the input / output register 9 and the data transfer flag 10.

As shown in FIG. 3, the command control circuit 6 is C
The write signal from PU1 is first converted into a read signal to the input / output register. At this time, the data buffer 7 is in a data passage prohibited state. Therefore, the data read from the input / output register 9 is the data coincidence detection circuit 8
Is output to. At this time, the data from the CPU is also directly input to the data coincidence detection circuit 10, and the data of both are compared here. This comparison result becomes a coincidence signal, which is input to the data transfer instruction flag 10.

Next, the command control circuit 6 stops the output of the read signal to the input / output register 9, and outputs the write signal from the CPU 1 as it is to the input / output register 9 and the data transfer instruction flag 10. At this point, the data buffer 7 is in the data passage permitting state, the data from the CPU is written in the input / output register 9, and the match signal (the valid mismatch signal) from the data match detection circuit 8 is written in the data transfer instruction flag 10. Be done. Data transfer instruction flag 10
Once the valid mismatch signal is written, the CPU
Nothing else is disabled by the reset signal from.

Therefore, once new data is written to a register having the input / output register 9, the same input / output register is used again in the subsequent program, and the same data as the current contents of the input / output register is written. Even
The data is finally output to the input / output module 13. When the batch input / output is completed, the CPU 1 outputs a reset signal to reset the data transfer instruction flag 10,
Prepare for the next scan.

As described above, in the PC of this embodiment, when the CPU 1 writes to the input / output register 9, it is detected by the instruction word decoding circuit, and by the operation of the data buffer 7 and the command control circuit 6. It is determined whether or not the data in the input / output register 9 before writing and the write data from the CPU 1 are the same. Only when they are not the same, the data transfer instruction flag 10 corresponding to each input / output register is set. At the time of batch input / output, the data is output only to the I / O module 13 corresponding to the input / output register in which the data transfer instruction flag 10 is set, and the batch input / output is performed for the I / O whose data has not changed. Since the output operation is not performed, the batch input / output time can be shortened and the total scan execution time can be shortened.

Next, a method of shortening the input time in batch input / output will be described. When the sequence instruction is read from the sequence program memory 4, the instruction code is input not only to the CPU 1 but also to the instruction word decoding circuit 5, and the instruction detected by the instruction decoding circuit 5 is read from the input / output register 9. Set as a command. At this time, the command decoding circuit 5 outputs an operation start signal to the command control circuit 6.

At this time, the operations of the command control circuit 6 and the data coincidence detection circuit 8 are changed as shown in FIG. CP
The read command from U1 becomes a read command to the input / output register 9, but at this time, the output of the data match detection circuit 8 is forcibly enabled (mismatch state), and the data transfer instruction flag 8 corresponding to the input register. Is set. By executing the sequence program to the end in this way, batch input will be executed only for the input registers used in the program,
Data is not input from unnecessary I / O modules, and data transfer is made efficient.

Next, the operation when executing the step progress type program will be described. Here, the process step program is an SFC (sequential function chart) type program as shown in FIG. In SFC, processes are connected under a transition condition, and when the transition condition is satisfied, control proceeds to the next process.

Now, assume that step N is being executed in FIG. At this time, the output is ON (=
1) is only the sequence instruction corresponding to the process N and the transition condition N. At this time, the bit accumulator 1-2 indicating the output state of the sequence operation is turned on.

Therefore, in the programs of the other processes, the sequence operation output is always OFF, so that no matter what value the input register has, it is not used in the sequence instruction, and it is not necessary to read it from the input module. . For example, the transition condition N is (IW001 = 100)
Under this condition, the SFC program checks the data of each scan input module until the input register IW001 reaches a value of 100, and when the condition is satisfied, the process proceeds to step N + 1. At this time, all outputs of the process N are turned off (= 0).

Therefore, when executing the step step program, the instruction detected by the instruction decoding circuit 5 is used as a transition condition instruction having the input / output register 9 as an operand, and data is transferred only when BR1-2 is ON. Instruction flag 10
By setting so that, the input / output module that is the target of batch input / output becomes the input / output module related to the process and transition condition currently being executed.
The data transfer amount can be significantly reduced. As described above, the data transfer time can be shortened.

Next, a method of permitting / prohibiting data transfer from the CPU 1 to any input / output register will be described. In the method described above, the target of batch input / output is only the input / output module corresponding to the input / output register used in the immediately preceding scan execution. Some programs run suddenly in.

When such a program is executed,
Since the I / O register used therein has not been used for the previous scan execution, it is inconvenient if the contents of the I / O register are not updated. So CP
By providing an output port 14 capable of setting an input / output register to be arbitrarily updated from U1, and by using the output thereof as an input of the instruction decoding circuit 5 to select a decoding operation, the input / output register in the range designated by the CPU is set. Force the data to be updated. By doing so, it becomes possible to transfer data to the input / output module corresponding to the input / output register not used in the previous scan execution.

Next, a method of controlling the data update of the input / output register corresponding to a specific I / O module will be described. In a PC, there are modules that occupy a large amount of input / output registers, such as a transmission module and a personal computer module. If such a module is, for example, a transmission module, two transmission modules are used, and one of them may be selected and used as a backup for one system. In such a case, I
It is effective to select the area of the input / output register corresponding to the / O module and make it the target of batch input / output.

Therefore, as shown in FIG. 1, an I / O address determination circuit 15 is provided to transfer data when the address of the input / output register corresponding to the I / O module designated by the CPU 1 is detected as a sequence instruction operand. By permitting the setting of the instruction flag, the data transfer amount can be controlled in I / O module units and the data transfer time can be shortened.

[0035]

As described above, according to the programmable controller of claim 1 of the present invention, when the CPU writes the execution result of the sequence instruction to the input / output register, the data originally existing in the input / output register, It is possible to shorten the data transfer time by determining whether the write data after executing the sequence instruction is the same and executing the data transfer with the I / O module only for the I / O register where the data has changed. .

According to the programmable controller of claim 2 of the present invention, by executing the data transfer with the input / output module only for the input / output register used as the operand by the sequence instruction for writing from the input / output register. It is possible to shorten the data transfer time.

According to the programmable controller of claim 3 of the present invention, the data transfer with the input / output module is executed only with respect to the input / output register used as the operand by the sequence instruction for reading from the input / output register. Thus, the data transfer time can be shortened.

According to the programmable controller of claim 4 of the present invention, in the step step type program, an input used as an operand of a sequence instruction used for a step and a transition condition in which a transition is possible. The data transfer time can be shortened by executing the data transfer with the input / output module only for the input / output register used by the output register program and the transition condition instruction.

According to the programmable controller of the fifth aspect of the present invention, by inputting the data from the input / output registers in an arbitrary range by the designation from the CPU, the input / output not used during the scan is executed. It is also possible to transfer data between registers and input / output modules.

According to the sixth aspect of the programmable controller of the present invention, the I / O address determination circuit allows / prohibits the data update between the specific I / O module and the corresponding input / output register. As a result, the data transfer time can be shortened.

[Brief description of drawings]

FIG. 1 is an embodiment diagram showing a configuration of a main part of a programmable controller according to the present invention.

FIG. 2 is a diagram showing configurations of an input / output register and a data transfer instruction flag.

FIG. 3 is an operation explanatory diagram of a command control circuit at the time of writing from the CPU.

FIG. 4 is an operation explanatory diagram of a command control circuit when reading from a CPU.

FIG. 5 is a diagram illustrating a configuration of a step-progressing type program.

FIG. 6 is a diagram illustrating a conventional batch input / output operation.

[Explanation of symbols]

 1 ... CPU 1-1 ... Sequence operation circuit 1-2 ... Bit accumulator (BR) 2 ... CPU bus 3 ... System memory 4 ... Sequence program memory 5 ... Instruction word decoding circuit 6 ... Command control circuit 7 ... Data buffer 8 ... Data Match detection circuit 9 ... I / O register 10 ... Data transfer instruction flag 11 ... I / O bus buffer 12 ... I / O bus 13 ... I / O module 14 ... Output port 15 ... I / O address determination circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G05B 19/05 L

Claims (6)

[Claims] 1. An input / output register for storing transfer data to / from an input / output module, and data corresponding to each register in the input / output register and instructing whether or not to perform data transfer with the input / output module. A transfer instruction flag, a CPU that executes a sequence instruction, and an instruction decoding circuit that decodes the sequence instruction executed by the CPU and detects a sequence instruction having the input / output register as an operand and an instruction of a type designated by the CPU A command control circuit for controlling input / output of data to / from the input / output register based on an output of the instruction decode circuit and a sequence instruction execution state of the CPU, and writing to the input / output register and the data transfer instruction flag A data buffer indicating permission / non-permission of, and when the CPU executes a sequence instruction, A programmable controller, comprising: a data coincidence detection circuit for determining whether the data existing in the input / output register and the write data after execution of a sequence instruction are the same. 2. The programmable controller according to claim 1, wherein the sequence instruction detected by the instruction decode circuit is a sequence instruction whose operand is a write operation in an input / output register, whereby the command control circuit and the data are stored. By reading the data from the corresponding I / O register by the buffer and comparing it with the write data from the CPU, it is judged for each I / O register whether or not the contents of the I / O register have changed. When a data transfer instruction flag is set in the output register and data is exchanged between the input / output register and the input / output module, only the input / output register for which the data transfer instruction flag is set is A programmer characterized by performing data transfers between Bull controller. 3. The programmable controller according to claim 1, wherein the sequence instruction detected by the instruction decoding circuit is a sequence instruction whose operand is a read operation in an input / output register, and is used in a sequence program. A programmable controller, wherein a data transfer flag is set only in an input / output register, and data transfer is executed only from an input / output module corresponding to the input / output register in which the data transfer flag is set. 4. The programmable controller according to claim 1, wherein a sequence instruction detected by the instruction decoding circuit when the step-progressing sequence program is executed has an input / output register as an operand.
By determining the transition condition between steps and determining the sequence instruction execution state of the CPU, the input / output registers used by the sequence instruction can be changed only when the step is currently in a state in which there is a possibility of transition. By setting the data transfer instruction flag, the data transfer amount can be reduced by inputting the necessary data from the input / output module only for the parts that may have transitions in the process step program. A programmable controller characterized by shortening the transfer time and performing sequence execution at high speed. 5. The programmable controller according to claim 1, wherein an output port capable of designating an output from a CPU is provided, an output signal of the output port is used as an input of the instruction decoding circuit, and an output signal of the output port is used in accordance with the output signal. A programmable controller characterized by forcibly updating data in an input / output register in a range designated by a CPU by arbitrarily setting a data transfer instruction flag. 6. The programmable controller according to claim 5, further comprising an I / O address determination circuit that determines a range of an input / output register corresponding to a specific I / O module, and an output of the I / O address determination circuit. Is an input to the command control circuit, the data update between the input / output register corresponding to a specific I / O and the I / O module is forcibly permitted or prohibited by the instruction of the CPU. controller.