JPH0814938B2 - Digital signal regenerator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing apparatus, and more particularly to an apparatus for reproducing a digital signal containing sync data from a recording medium on which a number of tracks arranged in parallel are formed.

[Conventional technology]

In this specification, a digital video tape recorder (DVTR) will be described as an example of this type of apparatus in this specification.

Generally, in a device that records a large amount of digital data such as DVTR on a recording medium, recording / reproduction is performed for each data group (sync block) in which a predetermined amount of information (video) data is added with a predetermined sync (synchronization) data. I do. This is because during data reproduction, data loss due to recording / reproduction system jitter or dropout and data reproduction timing shift occur, but data loss etc. occurs due to detection of periodically recorded sync data. The purpose is to prevent the occurrence of

However, the data reproduced through the recording / reproducing system causes a data error due to dropout or the like, and accordingly, erroneous detection in which the sync data is erroneously detected and sync loss in which the sync data cannot be detected often occur. When such synchronization loss occurs, the reproduction information (image) is seriously deteriorated.

Therefore, the timing at which the sync data is generated is predicted in advance, and the sync data is configured to be detectable only during a period of a few data to be played, so as to avoid erroneous detection. Has been subjected to so-called synchronization protection processing such as timing compensation in synchronization with sync data before that.

As a result, a stable reproduced image can be obtained without any problem during normal reproduction.

[Problems to be solved by the invention]

However, in the conventional apparatus as described above, when the reproduction head traces in the direction crossing the track, for example,
When performing special playback such as high-speed search playback or slow-motion playback in DVTR, the playback signal is not obtained intermittently and the continuity of sync data is lost. Therefore, it becomes difficult to perform the synchronization protection process as described above, and it becomes impossible to read the data during the special reproduction as described above, and it is impossible to obtain good reproduction data.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a digital signal reproducing device capable of reproducing a digital signal, capable of synchronizing protection even when the reproducing head traces in a direction intersecting with a track. It is an object.

[Means for solving problems]

Under such an object, according to the present invention, there is provided a device for reproducing a digital signal containing sync data from a recording medium on which a number of parallel tracks are formed, the reproducing head and the digital signal reproduced by the reproducing head. Means for detecting the sync data therein, means for generating a window pulse for defining the detection timing of the sync data for each predetermined period, and the generation timing of the window pulse is shifted according to the track jump of the reproducing head. In order to do so, a digital signal reproduction device is presented, comprising means for generating the window pulse at a period different from the predetermined period.

[Action]

With the above-mentioned configuration, even when the reproduction head traces in the direction intersecting with the track, the sync data immediately after the track jump can be extracted and the synchronization protection process can be performed. Therefore, even in the above case, the digital signal can be reproduced.

〔Example〕

 A DVTR as an embodiment of the present invention will be described below.

FIG. 1 is a diagram showing a schematic configuration of the VTR of this embodiment,
The steps will be described below in order. It is assumed that the luminance signal (Y) and the color difference signal (I, Q) of the video signal conforming to the NTSC signal are input in parallel to the terminal 1, and Y is 4fsc (fsc is the color subcarrier frequency), I, Q Is sampled at a frequency of 1/4 of that frequency, and in this output data, data is thinned out so that the sampling points are not vertically aligned between adjacent lines due to interlaced scanning. That is, the analog-digital (A / D) converter 2 performs so-called sub-sampling.

At this time, the sample points of Y are (3.
58M ÷ 15.75K) x 4/2, which is 455 pieces. Actually, only valid screens are converted into data, and 372 per 1H. Also I, Q
As for, about 1/4 will be 96 pieces. The output data of the A / D converter 2 is supplied to the memory 3 and ECC is added by an ECC (error correction code) adding circuit 4.

Here, the video data block, which is a unit to which ECC is added, has a data amount corresponding to an image of an area obtained by dividing one screen (one field) into vertical 4 × horizontal 3 as shown by the hatched portion in FIG. That is, if the number of effective horizontal scanning lines is 240,
Y at 60 (vertical) x 124 (horizontal) (= 372/3) sample points and 60 vertical
× Includes I and Q data at 32 (= 96/3) horizontal sample points. This is arranged on the memory 3 as shown in the lower diagram of FIG. 2, and the ECC codes C1 and C2 are added as shown in the figure, and (192 × 6
4) Get data blocks. Here, the number in the figure represents the number of bytes, and the data at each sampling point is 8 bits (1
Bytes).

Reference numeral 5 is a circuit for adding 1-byte sync data (Sync), 3-byte data (X) including additional data of each sync block and a redundant code for this additional data to each of the 384-byte data. Accompanying this is a sync block consisting of 392 bytes. Figure 3 shows video data Vd
It is a figure which shows one sync block containing. The data to which the sync data and the data X are added in the circuit 5 is converted into serial data in the parallel-serial (P / S) converter 7 after the direct current component is removed by, for example, 8-8 mapping encoding in the modulation circuit 6. To be converted.

Then, the serialized data is supplied as a digital signal to the recording / reproducing unit 9 via the recording amplifier 8 and recorded on a magnetic tape (not shown) by a rotating head (not shown).

FIG. 4 is a diagram showing a recording pattern on the magnetic tape by the DVTR of this embodiment. As shown in the figure, in the VDTR of this embodiment, + azimuth tracks and −azimuth tracks are alternately arranged. Since the data amount of each sync block is always constant and the rotation speed of the rotary head is always constant, the sync data recording position between adjacent tracks must be shifted by a constant amount in the track length direction. Become. In accordance with this, also between adjacent tracks of the same azimuth, the sync data recording position is similarly shifted in the track length direction by a constant amount. In addition, in FIG. 4, SB0-0, SB1-0, SB0-1, SB1-1, SB0
Symbols -2, SB0-3 and the like indicate the recording areas of the sync blocks, and the hatched portions indicate the portions where no data is recorded.

In FIG. 1, the signal reproduced from the recording / reproducing unit 9 is amplified by the reproducing amplifier 10 to a level convenient for signal processing. Reference numeral 11 denotes a clock reproduction circuit, which extracts the clock component included in the data from the output of the reproduction amplifier 10 using a technique such as PLL. The data shaping circuit 12 is a clock reproduction circuit 11
By using a clock of a constant frequency synchronized with the extracted reproduction signal, the signal distorted in the recording / reproduction system output from the reproduction amplifier 10 is synchronized and shaped into a data string with a timed timing. The shaped data string is supplied to the sync detection circuit 13 to detect the aforementioned 8-bit sync pattern included in the data string. That is, the sync pattern and the data shaping circuit
The data strings output in 12 are compared bit by bit, and if all the bits match, it is regarded as sync data and a sync pulse is output.

However, in this method, if the same specific bit pattern as this sync pattern appears in the reproduced data by accident, it may be mistakenly regarded as a sync pattern. This state is shown in Fig. 5 SY-1. SY in Figure 5
Reference numeral -1 indicates the output of the synchronization detection circuit 13, and the pulse indicated by X in the figure is a pulse associated with the above-mentioned erroneous detection. If the timing of each part of the apparatus is determined by the pulse resulting from such erroneous detection, all the reproduced data thereafter will be erroneous data.

Therefore, based on the clocks extracted by the clock reproduction circuit 11, a window pulse (window signal) indicating a period from the number before and after the sync data to several tens of clocks is created in the cycle in which the sync data will be reproduced, and this window is generated. The pulse obtained from the sync detection circuit 13 is gated by the AND gate 16 within the period indicated by the pulse, and the output of this AND gate 16 is used as a true sync pulse to prevent an error in the reproduced data due to the false detection of the sync data. it can. This window pulse (shown by W-1 in FIG. 5) is generated by the window signal generation circuit 15 using the pulse generated in the timing signal generation circuit 14 in the reproduction cycle of the sync data unless the track jump described later is generated. It

If this window pulse and the sync data detection timing are misaligned, or if the sync data to be played back is missing, it is detected that no sync pulse has been detected within the window pulse period. Circuit 17 detects. The loss detection circuit 17 counts up the counter 18 each time a loss of synchronization is detected. The count value M of the counter 8 indicates the number of consecutive synchronization losses, and this count value M is supplied to the window signal generation circuit 15 to determine the pulse width of the window pulse. That is, the pulse width of the window pulse becomes wider as the count value M of the counter 18 increases.

At the time of normal reproduction, the count value M of the counter 18 is 0 for most of the period, and becomes 1 only when a data error happens to occur in the sync data. Therefore, the synchronization disorder does not occur, and the data string output from the data shaping circuit 12 is generated by the timing pulse from the timing signal generation circuit 14 in the serial-parallel (S / P) conversion circuit 1.
After being converted into parallel data in 9, the data is demodulated in a demodulation circuit 20 which performs a process reverse to that of the modulation circuit 6 and then supplied to the memory 21. The data stored in the memory 21 is subjected to error correction by the ECC decoding circuit 22, and then digital-analog (D / D
A) It is returned to the original analog signal via the converter 23 and output from the rear terminal 24.

On the other hand, during special reproduction, for example, high-speed reproduction, the tape is conveyed by a tape drive system (not shown) at a speed several times faster than during recording, so that the envelope waveform of the reproduction signal is as shown by e in FIG. The dotted line Th in FIG. 6 shows the lowest level at which data can be detected. Therefore, at the time of high speed reproduction, a period in which data cannot be reproduced occurs intermittently. Of course, the sync data cannot be detected during this period, and the sync data reproduced before and after this period does not have continuity.

Reference numeral 25 in FIG. 1 denotes an envelope detection circuit, which envelope-detects the output of the reproduction amplifier 10 to obtain an output as shown by e in FIG. 6 (a). The output of this circuit 25 is compared with the above-mentioned level Th in the comparison circuit 26, and is shown in FIGS. 5E and 6 (b).
A signal as shown in is obtained. The output of the comparison circuit 26 is supplied to a falling edge detection circuit 27 that detects a falling edge. Comparison circuit
One cycle of the output of 26 indicates that the same head has moved between adjacent tracks of the same azimuth, which indicates one track jump. The trailing edge detection circuit 27 detects this track jump, and the output of this trailing edge detection circuit 27 outputs a pulse obtained in the sync data reproduction cycle generated by the timing signal generation circuit between adjacent tracks of the same azimuth. Shift is performed based on the shift amount of the recording position of the sync data. Along with this, as shown in FIG. 5W-2, the window pulse is shifted in timing immediately after the trailing edge of the signal E so that the sync data after the track jump can be detected. Moreover, since the window pulse is a wide pulse after the period in which the sync data cannot be detected, a slight deterioration in accuracy does not pose a problem.

Therefore, as long as the envelope has reached a level sufficient for data detection, the recorded data can be restored, and the image quality at high speed reproduction can be improved as compared with the conventional case.

FIG. 7 is a diagram showing a concrete configuration example of the timing signal generating circuit 14 of FIG. 1, in which CL is a clock supplied from the clock reproducing circuit 11, SY is a synchronizing pulse supplied from the AND gate 16, and EL Is a falling edge detection pulse output from the falling detection circuit 27. 51 is a counter that counts the clock CL. 52 is the number of clocks (bits) during the recording cycle of the sync data recorded in each track
A data generator that generates a number of data PD1 corresponding to a slightly larger number, 53 is a data generator that generates a number of data PD2 in which the number of clocks corresponding to the shift amount of sync data at the time of track jump is added to the above data PD1. It is a vessel. Since the pulse EL is not input in the steady state, the output of the flip-flop (FF) 55 becomes low level and the data selector
54 supplies the data PD1 to the comparator 56. The comparator 56 compares the data PD1 with the count value of the counter 51, and outputs a pulse to the window signal generation circuit 15 when they match. The OR gate 58 resets the counter 51 when either the output pulse of the comparator 56 or the synchronizing pulse SY is input.

Therefore, in the steady state, the count 51 is reset by the sync pulse when the sync pulse SY is input, and is reset at the same timing as the sync pulse SY even when the sync pulse SY is not input. Timing pulse generator 57 is counter 51
The timing pulses φ ₁ , φ ₂ , φ ₃ , φ ₄ for controlling each part of the apparatus are generated based on the count value of 1 to control the timing of each part of FIG.

On the other hand, when the track jump occurs, the pulse EL is input, so that the selector 54 supplies the data PD2 to the comparison circuit 54. Along with this, the generation timing of the output pulse of the comparator 56, that is, the window pulse output from the window signal generation circuit 15 is shifted. After the comparator 56 outputs a pulse, FF5 is reset and returns to the steady state again.

In the present specification, the DVTR is taken as an example, and high-speed playback is taken as an example of the playback accompanied by the track jump, but the scope of application of the present invention is not limited to this, and for example, additional information in a digital audio recorder. The same effect can be obtained when the tape is played back at a high speed.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain a digital signal reproducing apparatus capable of reproducing the digital signal more reliably and satisfactorily even when the reproducing head traces in the direction intersecting with the track. it can.

[Brief description of drawings]

1 is a diagram showing a schematic configuration of a DVTR as an embodiment of the present invention, FIG. 2 is a diagram for explaining video data to be recorded, FIG. 3 is a diagram showing a configuration of a video sync block, 4 The figure shows the recording pattern by the DVTR of FIG. 1, FIG. 5 shows the timing chart showing the operation of the DVTR of FIG. 1, and FIG. 6 shows the envelope waveform of the DVTR of FIG. 1 during high-speed reproduction. FIG. 7 is a diagram showing a configuration example of the timing signal generating circuit in FIG. In the figure, 5 is a sync data adding circuit, 9 is a recording / reproducing unit, 13
Is a synchronization detection circuit, 14 is a timing signal generation circuit, 15 is a window signal generation circuit, 16 is an AND gate, 17 is a sync loss detection circuit, 18 is a counter, 25 is an envelope detection circuit, 26 is a comparison circuit, and 27 is a falling edge. It is a detection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shin Shimogoriyama No. 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) Reference JP-A-59-104731 (JP, A)

Claims (1)

[Claims] 1. A device for reproducing a digital signal containing sync data from a recording medium on which a number of parallel tracks are formed, wherein a reproducing head and sync data in the digital signal reproduced by the reproducing head are detected. Means for generating a window pulse defining a detection timing of the sync data every predetermined period, and the predetermined period for shifting the generation timing of the window pulse according to a track jump of the reproducing head. And a means for generating the window pulse in a period different from the above.