JPH0817836A - Solder wire, solder bump electrode, and method for manufacturing solder bump electrode - Google Patents
Solder wire, solder bump electrode, and method for manufacturing solder bump electrodeInfo
- Publication number
- JPH0817836A JPH0817836A JP6149277A JP14927794A JPH0817836A JP H0817836 A JPH0817836 A JP H0817836A JP 6149277 A JP6149277 A JP 6149277A JP 14927794 A JP14927794 A JP 14927794A JP H0817836 A JPH0817836 A JP H0817836A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- chip
- electrode
- weight
- solder bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 93
- 238000000034 method Methods 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910052718 tin Inorganic materials 0.000 claims abstract description 11
- 229910052738 indium Inorganic materials 0.000 claims abstract description 10
- 229910052745 lead Inorganic materials 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 29
- 239000000203 mixture Substances 0.000 claims description 19
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 229910052725 zinc Inorganic materials 0.000 claims description 9
- 229910000765 intermetallic Inorganic materials 0.000 claims description 5
- 230000006866 deterioration Effects 0.000 abstract description 7
- 238000012545 processing Methods 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000012423 maintenance Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007712 rapid solidification Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000005491 wire drawing Methods 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】ＩＣチップＡｌ電極上の半田バンプをリフロー
処理するに際して、Ａｌ電極上に別工程で皮膜形成を行
う工程を省略しても、リフロー処理による接合強度の劣
化が小さいバンプ電極を提供する。
【構成】Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要元
素とし、且つＣｕ（０．０１〜５．０重量％），Ｎｉ
（０．０１〜５．０重量％），Ｚｎ（０．０１〜５．０
重量％）から選ばれる２種以上を含有した半田ワイヤを
用いて、ＩＣチップ１のＡｌ電極２上に半田バンプ３を
形成し、この半田バンプ３を介してＩＣチップ１と基板
４の電極２，５を接合した。この時、半田バンプ３をリ
フロー処理して電極２，５間の位置ずれを修正し、ＩＣ
チップ１と基板４の接合不良を防止する。半田バンプ３
はリフロー処理を行っても剪断強度の劣化を低く抑える
ことが出来、実用可能な剪断強度を得ることが出来た。
(57) [Abstract] [Objective] When reflowing a solder bump on an Al electrode of an IC chip, even if the step of forming a film on the Al electrode in a separate step is omitted, the deterioration of the bonding strength due to the reflow processing is small. Provide bump electrodes. [Structure] At least one of Pb, Sn, and In is a main element, and Cu (0.01 to 5.0% by weight) and Ni are used.
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
% By weight), solder bumps 3 are formed on the Al electrodes 2 of the IC chip 1 using solder wires containing two or more kinds selected from the solder bumps 3, and the electrodes 2 of the IC chip 1 and the substrate 4 are connected via the solder bumps 3. , 5 were joined. At this time, the solder bump 3 is subjected to reflow processing to correct the positional deviation between the electrodes 2 and 5,
A defective joint between the chip 1 and the substrate 4 is prevented. Solder bump 3
It was possible to suppress the deterioration of the shear strength to a low level even after the reflow treatment, and it was possible to obtain a practical shear strength.
Description
【０００１】[0001]
【産業上の利用分野】本発明はＩＣチップの接続方法及
びそれに用いる半田ワイヤに関し、詳しくは、バンプを
介したワイヤレスボンディング法によりＩＣチップを基
板に接続する方法及びそれに用いる半田ワイヤに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC chip connecting method and a solder wire used therefor, and more particularly to a method for connecting an IC chip to a substrate by a wireless bonding method via bumps and a solder wire used therefor.
【０００２】[0002]
【従来の技術】近年、半導体の高機能化に伴いＩＣの入
出力端子が増大する傾向にある。このため、ＩＣチップ
と基板を接続する方法として、フリップチップボンディ
グ等のバンプを介したワイヤレスボンディング方法が注
目を集めている。この方法は、ワイヤボンディング方法
がＩＣチップの周辺しか電極パッドを設けることが出来
ないのに対して、ＩＣチップの全面に電極パッドを形成
出来るため、電極パッド数を増やし実装密度を高める方
法に適している。2. Description of the Related Art In recent years, the number of input / output terminals of ICs has tended to increase as semiconductors have become more sophisticated. Therefore, as a method for connecting the IC chip and the substrate, a wireless bonding method using bumps such as a flip chip bond is attracting attention. This method is suitable for the method of increasing the number of electrode pads and increasing the mounting density because the wire bonding method can provide the electrode pads only around the IC chip, while the electrode pads can be formed on the entire surface of the IC chip. ing.
【０００３】ここで、バンプを介したワイヤレスボンデ
ィング方法の代表例としてフリップチップボンディング
について説明する。この方法は図１に示す通り、ＩＣチ
ップ１のＡｌ電極２に半田バンプ３を形成し、基板４に
は対応する位置に所定の電極５を形成する。このＩＣチ
ップ１と基板４はそれぞれ電極２，５と半田バンプ３を
介して接合される。この時、図２に示す様に、ＩＣチッ
プ１を基板４の所定位置に高精度で搭載することが困難
なため、電極２と５の位置にずれが生じることがある。
この様に電極２，５の中心線の位置がずれた状態でＩＣ
チップ１と基板４が接合された場合接合不良となり、半
導体の作動不良の原因となる。Here, flip chip bonding will be described as a typical example of a wireless bonding method via bumps. In this method, as shown in FIG. 1, solder bumps 3 are formed on the Al electrodes 2 of the IC chip 1 and predetermined electrodes 5 are formed on the substrate 4 at corresponding positions. The IC chip 1 and the substrate 4 are bonded to each other via the electrodes 2 and 5 and the solder bumps 3, respectively. At this time, as shown in FIG. 2, since it is difficult to mount the IC chip 1 at a predetermined position on the substrate 4 with high accuracy, the positions of the electrodes 2 and 5 may be displaced.
In this way, with the positions of the center lines of the electrodes 2 and 5 displaced, the IC
When the chip 1 and the substrate 4 are bonded, a bonding failure occurs, which causes a malfunction of the semiconductor.
【０００４】この対応として特開平６−１３２３５３号
公報等には、半田バンプをリフローさせて接合精度を向
上させることが提案されており、これはＩＣチップと基
板の電極位置に多少のずれがあっても両電極間に介在す
る半田バンプをリフローさせると、半田バンプが溶融し
た状態でその表面張力により表面積を極力小さくするよ
うに自己修正が行われ、ＩＣチップのずれを解消出来る
とするものである。この方法はＩＣチップ搭載上のずれ
を解消する方法として有効な方法であるが、ＩＣチップ
Ａｌ電極上の半田材料をリフローするとＩＣチップと半
田バンプの接合強度が低下するという問題が生じる。前
記接合強度低下の対応として、ＩＣチップＡｌ電極上に
Ｃｒ，Ｃｕ，Ａｕ又はＴｉ，Ｎｉ，Ａｕ等の多層スパッ
タ膜を形成することが試みられている。しかし乍らこの
方法は、工程が増えて時間を要するだけでなくコスト高
になるという問題を有する。In order to deal with this, Japanese Patent Laid-Open No. 6-132353 proposes to reflow solder bumps to improve the bonding accuracy. This is because the electrode positions of the IC chip and the substrate are slightly displaced. Even if the solder bumps interposed between the two electrodes are reflowed, the self-correction is performed so that the surface area of the solder bumps in the molten state is minimized by the surface tension, and the displacement of the IC chip can be eliminated. is there. This method is effective as a method for eliminating the deviation in mounting the IC chip, but when the solder material on the IC chip Al electrode is reflowed, there arises a problem that the bonding strength between the IC chip and the solder bump decreases. As a countermeasure against the decrease in the bonding strength, it has been attempted to form a multilayer sputtered film of Cr, Cu, Au or Ti, Ni, Au or the like on the Al electrode of the IC chip. However, this method has a problem that not only the number of steps is increased and time is required, but also the cost is increased.
【０００５】[0005]
【発明が解決しようとする課題】本発明は上記従来事情
に鑑み、ＩＣチップＡｌ電極上の半田バンプをリフロー
処理するに際して、Ａｌ電極上に別工程で皮膜形成を行
う工程を省略しても、リフロー処理による接合強度の劣
化が小さい半田ワイヤ、バンプ電極及びその製造方法を
提供せんとするものである。In view of the above-mentioned conventional circumstances, the present invention eliminates the step of forming a film on the Al electrode in a separate step when reflowing the solder bump on the IC chip Al electrode. It is intended to provide a solder wire, a bump electrode, and a method for manufacturing the same, in which the deterioration of the bonding strength due to the reflow treatment is small.
【０００６】[0006]
【課題を解決するための技術的手段】以上の目的を達成
するために本願第１発明は、半田材料の組成が下記〔組
成Ｉ〕であり、ＩＣチップのＡｌ電極上でリフローさせ
た後の剪断強度が１９ＭＰａ以上であることを特徴とす
るＩＣチップのバンプ電極用半田ワイヤである。 〔組成Ｉ〕Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要
元素とし、且つ、Ｃｕ（０．０１〜５．０重量％），Ｎ
ｉ（０．０１〜５．０重量％），Ｚｎ（０．０１〜５．
０重量％）から選ばれる２種以上を含有する。In order to achieve the above object, the first invention of the present application is such that the composition of the solder material is the following [composition I] and the reflow is performed on the Al electrode of the IC chip. A solder wire for a bump electrode of an IC chip, which has a shear strength of 19 MPa or more. [Composition I] At least one of Pb, Sn, and In is a main element, and Cu (0.01 to 5.0% by weight), N
i (0.01 to 5.0% by weight), Zn (0.01 to 5.
0% by weight).
【０００７】また本願第２発明は、ＩＣチップのＡｌ電
極上に形成された半田バンプ電極において、半田材料の
組成が下記〔組成Ｉ〕であり、且つ、ＩＣチップＡｌ電
極と半田バンプの境界にＣｕ，Ｎｉ，Ｚｎから選ばれる
２種以上を含有する金属間化合物層を形成してなること
を特徴とするＩＣチップの半田バンプ電極である。 〔組成Ｉ〕Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要
元素とし、且つ、Ｃｕ（０．０１〜５．０重量％），Ｎ
ｉ（０．０１〜５．０重量％），Ｚｎ（０．０１〜５．
０重量％）から選ばれる２種以上を含有する。According to the second invention of the present application, in the solder bump electrode formed on the Al electrode of the IC chip, the composition of the solder material is the following [composition I], and at the boundary between the IC chip Al electrode and the solder bump. A solder bump electrode for an IC chip, comprising an intermetallic compound layer containing two or more selected from Cu, Ni, and Zn. [Composition I] At least one of Pb, Sn, and In is a main element, and Cu (0.01 to 5.0% by weight), N
i (0.01 to 5.0% by weight), Zn (0.01 to 5.
0% by weight).
【０００８】さらに本願第３発明は、ＩＣチップＡｌ電
極と基板電極を半田バンプを介して接合するＩＣチップ
半田バンプ電極の製造方法において、ＩＣチップのＡｌ
電極上で下記〔組成Ｉ〕の半田材料をリフローさせるこ
とを特徴とするＩＣチップ半田バンプ電極の製造方法で
ある。 〔組成Ｉ〕Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要
元素とし、且つ、Ｃｕ（０．０１〜５．０重量％），Ｎ
ｉ（０．０１〜５．０重量％），Ｚｎ（０．０１〜５．
０重量％）から選ばれる２種以上を含有する。Further, the third invention of the present application relates to a method for manufacturing an IC chip solder bump electrode in which an IC chip Al electrode and a substrate electrode are joined via a solder bump.
A method for manufacturing an IC chip solder bump electrode, which comprises reflowing a solder material having the following [composition I] on the electrode. [Composition I] At least one of Pb, Sn, and In is a main element, and Cu (0.01 to 5.0% by weight), N
i (0.01 to 5.0% by weight), Zn (0.01 to 5.
0% by weight).
【０００９】[0009]
【作用】以下本発明の構成と作用についてさらに説明す
る。 〔半田材料〕 Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要元素と
する。ここで主要元素とは５０重量％以上含有されたも
のであり、好ましくは８０重量％以上含有されたもので
ある。 本発明では上記主要元素に加えて、次の２種以上を
含有することが必要である。 Ｃｕ（０．０１〜５．０重量％） Ｎｉ（０．０１〜５．０重量％） Ｚｎ（０．０１〜５．０重量％） 半田材料の主要元素に対してＣｕ，Ｎｉ，Ｚｎをこのよ
うに添加した合金半田は、Ａｌ電極上でリフローさせて
も半田バンプ材の剪断強度の劣化が小さく、いずれもリ
フロー前の剪断強度に対するリフロー後の剪断強度で表
した剪断強度維持率を５０％以上とすることが出来、リ
フロー後の剪断強度を１９ＭＰａ以上に出来る。このた
め、接合強度は充分得られる。Ｃｕ，Ｎｉ，Ｚｎの含有
量は、 Ｃｕ：０．０５〜５．０重量％ Ｎｉ：０．０５〜５．０重量％ Ｚｎ：０．０５〜５．０重量％ であることがより好ましい。この範囲の時、Ａｌ電極上
でリフローさせても半田バンプ材の剪断強度の劣化はさ
らに小さく、剪断強度維持率を６０％以上とすることが
出来、リフロー後の剪断強度を３０ＭＰａ以上に出来
る。The structure and operation of the present invention will be further described below. [Solder Material] At least one of Pb, Sn, and In is a main element. Here, the main element is contained in an amount of 50% by weight or more, preferably 80% by weight or more. In the present invention, it is necessary to contain two or more of the following in addition to the above main elements. Cu (0.01 to 5.0% by weight) Ni (0.01 to 5.0% by weight) Zn (0.01 to 5.0% by weight) Cu, Ni and Zn are added to the main elements of the solder material. The alloy solder thus added has a small deterioration in the shear strength of the solder bump material even when reflowed on the Al electrode, and in all cases, the shear strength maintenance ratio expressed by the shear strength after reflow with respect to the shear strength before reflow is 50%. %, And the shear strength after reflow can be 19 MPa or more. Therefore, sufficient bonding strength can be obtained. The content of Cu, Ni, and Zn is more preferably Cu: 0.05 to 5.0% by weight Ni: 0.05 to 5.0% by weight Zn: 0.05 to 5.0% by weight. In this range, the deterioration of the shear strength of the solder bump material is further small even when reflowing on the Al electrode, the shear strength maintenance rate can be set to 60% or more, and the shear strength after reflow can be set to 30 MPa or more.
【００１０】 その他成分 本発明においては半田材料を前記構成にすることに加え
て、半田材料として通常含有される成分を含み得るもの
である。例えば、冷間加工性を向上させるための０．２
〜１０重量％Ａｇ、半田材料の強度を向上させ取扱いを
容易にするための１〜１０重量％Ｓｂ等が例示出来る。 機構の推定 本発明において半田材料を前記構成にすることにより、
Ａｌ電極上でリフローさせても半田バンプ材の剪断強度
の劣化を小さく出来る理由は十分に解明されていないも
のの、Ａｌ電極上で半田バンプ材をリフローさせた場
合、従来はＡｌ成分が半田バンプ材中に拡散されてＡｌ
電極が消滅する傾向にあることに対し、本発明において
は図３に示すように、Ａｌ電極２と半田バンプ材3aとの
境界に金属間化合物６が形成され、この化合物６の中に
Ｃｕ，Ｎｉ，Ｚｎの内少なくとも２種を含むことが、Ａ
ｌ成分が半田バンプ材中に拡散されることを阻止する働
きをしているものと考えられる。Other Components In the present invention, in addition to the above-mentioned constitution of the solder material, a component usually contained as a solder material can be contained. For example, 0.2 to improve cold workability
Examples include 10 to 10 wt% Ag and 1 to 10 wt% Sb for improving the strength of the solder material and facilitating handling. Mechanism estimation By using the solder material having the above-described structure in the present invention,
Although the reason why the deterioration of the shear strength of the solder bump material can be reduced even if it is reflowed on the Al electrode has not been sufficiently clarified, when the solder bump material is reflowed on the Al electrode, conventionally, the Al component is the solder bump material. Al diffused in
In contrast to the tendency of the electrodes to disappear, in the present invention, as shown in FIG. 3, the intermetallic compound 6 is formed at the boundary between the Al electrode 2 and the solder bump material 3a. A containing at least two of Ni and Zn is
It is considered that it functions to prevent the l component from diffusing into the solder bump material.
【００１１】〔半田ワイヤの製造方法〕本発明になる半
田ワイヤの製造方法としては次の二つの方法が例示出来
る。第１の方法は前記構成の半田材料を溶解し、鋳造、
押出、伸線加工を行うことにより直径３０〜１００μｍ
のワイヤに仕上げる。第２の方法は前記構成の半田材料
を溶解し、該溶湯を水中に噴射する急冷凝固法により素
線を得、次いで伸線加工を行うことにより直径３０〜１
００μｍのワイヤに仕上げる。本発明においては第２の
方法である急冷凝固法が好ましく採用される。この理由
は、均一な組成が得られると共に良好な機械的性質が得
られ、バンプ形成のハンドリングが容易になるためであ
る。[Method for Manufacturing Solder Wire] As the method for manufacturing the solder wire according to the present invention, the following two methods can be exemplified. The first method is to melt the solder material having the above-mentioned structure and cast it.
Diameter of 30 to 100 μm by extrusion and wire drawing
Finish the wire. The second method is to melt the solder material having the above structure, obtain a wire by a rapid solidification method in which the molten metal is injected into water, and then perform wire drawing to obtain a diameter of 30 to 1
Finish to a wire of 00 μm. In the present invention, the second method, the rapid solidification method, is preferably adopted. The reason is that a uniform composition can be obtained, good mechanical properties can be obtained, and the handling of bump formation becomes easy.
【００１２】〔半田バンプの形成方法／ＩＣチップと基
板の接合〕図４を参照して半田バンプの形成方法及びＩ
Ｃチップと基板の接合を説明する。 半田ボールの形成 （ａ）図において、半田ワイヤ７はキャピラリ８からそ
の先端部を導出し、トーチ９を加熱源として半田ボール
１０を形成する。 半田ボールの圧着 （ｂ）図において、キャピラリ８を下降させることによ
り半田ボール１０はＩＣチップ１上のＡｌ電極２上に圧
着される。ここでＡｌ電極として、通常はＡｌ−Ｓｉや
Ａｌ−Ｃｕ−Ｓｉ等のＡｌ合金が用いられる。 半田バンプの形成 （ｃ）図において、キャピラリ８を引き上げることによ
り、半田ボール１０のネック部が破断して半田ボール１
０がＡｌ電極２上に残留する。この残留した半田ボール
１０を半田バンプ３と呼ぶ。 ＩＣチップ１と基板４の接合 （ｄ）図において、ＩＣチップ１と基板４はそれぞれの
電極２，５と半田バンプ３を介して接合される。この時
前述した様な、半田バンプ材を溶融状態に至る迄加熱す
る所謂リフロー処理を行う。このリフロー処理を行うこ
とにより、ＩＣチップ１と基板４の電極２，５の位置ず
れによる接合不良を、溶融した半田バンプ材の表面張力
を利用して自己修正させることが出来る。[Method of Forming Solder Bumps / Joining of IC Chip and Substrate] Referring to FIG. 4, a method of forming solder bumps and I
The bonding between the C chip and the substrate will be described. Formation of Solder Ball In FIG. 1A, the solder wire 7 is led out of its tip from the capillary 8 and the solder ball 10 is formed using the torch 9 as a heating source. Solder ball crimping (b) In the figure, the solder ball 10 is crimped onto the Al electrode 2 on the IC chip 1 by lowering the capillary 8. Here, an Al alloy such as Al-Si or Al-Cu-Si is usually used as the Al electrode. Formation of Solder Bumps In FIG. 1C, the capillary 8 is pulled up, the neck portion of the solder ball 10 is broken, and the solder ball 1
0 remains on the Al electrode 2. The remaining solder balls 10 are called solder bumps 3. Bonding of IC Chip 1 and Substrate 4 In the diagram (d), the IC chip 1 and the substrate 4 are bonded to each other via electrodes 2 and 5 and solder bumps 3. At this time, a so-called reflow process is performed to heat the solder bump material until it reaches a molten state as described above. By performing this reflow process, it is possible to self-correct the bonding failure due to the positional displacement of the electrodes 2 and 5 of the IC chip 1 and the substrate 4 by utilizing the surface tension of the melted solder bump material.
【００１３】[0013]
〔実施例１〕５０重量％Ｓｎ、０．０１重量％Ｃｕ、
０．５重量％Ｎｉ、５．０重量％Ｓｂ、５．０重量％Ａ
ｇ、残部Ｐｂとなるように、半田合金１００ｇをアルゴ
ンガス雰囲気中で溶解し、アルゴンガス圧で穴径３００
μｍの石英ノズルから噴出させ、２５０ｒｐｍで回転し
ている水層を形成した円筒ドラム内で急冷凝固させ半田
素線を得た。この素線を伸線加工して直径５０μｍの半
田ワイヤに仕上げた。ここで得られた半田ワイヤを用い
て、図４（ａ）〜（ｃ）の手順に従ってＩＣチップ１の
Ａｌ−Ｓｉ合金電極２上に半田バンプ３を形成した。図
４（ａ）〜（ｃ）と同様の手順に従って２０個の半田バ
ンプ試料を作成し、この内１０個の半田バンプ試料につ
いては日本アルファーメタルズ社製ロジン系フラックス
（商品名：α５００３ＴＲ）を塗布し、アルゴンガス雰
囲気中で加熱台を用いて５００Ｋまで加熱し、半田バン
プをリフローさせた。リフロー処理有り無しの各１０個
の半田バンプ材について剪断強度を測定した。その結果
を表２中に示す。次いで、Ｘ線回析装置を用いて図３に
示す金属間化合物６を測定した。確認出来たＣｕ，Ｎ
ｉ，Ｚｎ成分の種類を表２中に示す。[Example 1] 50 wt% Sn, 0.01 wt% Cu,
0.5 wt% Ni, 5.0 wt% Sb, 5.0 wt% A
g and the balance Pb, 100 g of the solder alloy is melted in an argon gas atmosphere, and the hole diameter is set to 300 by argon gas pressure.
It was ejected from a quartz nozzle of μm and rapidly solidified in a cylindrical drum having a water layer rotating at 250 rpm to obtain a solder wire. This wire was drawn to form a solder wire with a diameter of 50 μm. Using the solder wire obtained here, the solder bump 3 was formed on the Al—Si alloy electrode 2 of the IC chip 1 according to the procedure of FIGS. 20 solder bump samples were prepared according to the same procedure as in FIGS. 4 (a) to 4 (c), and 10 of these solder bump samples were coated with rosin-based flux (trade name: α5003TR) manufactured by Japan Alpha Metals. Then, the solder bumps were reflowed by heating up to 500 K using a heating table in an argon gas atmosphere. Shear strength was measured for each of 10 solder bump materials with and without reflow treatment. The results are shown in Table 2. Then, the intermetallic compound 6 shown in FIG. 3 was measured using an X-ray diffraction apparatus. Confirmed Cu, N
Table 2 shows the types of i and Zn components.
【００１４】〔剪断強度の測定方法〕半田バンプ材とＩ
ＣチップＡｌ電極の間の剪断荷重をボンディング強度試
験装置を用いて測定し、光学顕微鏡により測定した接合
面積当りの剪断強度（ＭＰａ）で表示した。[Method of Measuring Shear Strength] Solder bump material and I
The shear load between the C-chip Al electrodes was measured using a bonding strength tester, and the shear strength (MPa) per joint area measured by an optical microscope was displayed.
【００１５】〔実施例２〜２３、比較例１〜６〕半田ワ
イヤの組成を表１の様にしたこと以外は実施例１と同様
にして試験を行った。測定結果を表２に示す。Examples 2 to 23 and Comparative Examples 1 to 6 Tests were conducted in the same manner as in Example 1 except that the composition of the solder wire was as shown in Table 1. The measurement results are shown in Table 2.
【００１６】[0016]
【表１】 [Table 1]
【００１７】[0017]
【表２】 [Table 2]
【００１８】表１及び表２の実施例１〜２３から明らか
な様に、Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要元
素とし、且つ０．０１〜５．０重量％Ｃｕ，０．０１〜
５．０重量％Ｎｉ，０．０１〜５．０重量％Ｚｎの内２
種以上を含有した半田ワイヤを用いて半田バンプを形成
することにより、直接リフロー処理しても剪断強度はい
ずれも２０ＭＰａ以上であり、リフロー処理することに
よる剪断強度の劣化しにくさを表す剪断強度維持率はい
ずれも５０％以上であることが判る。ここで、２種以上
含有させるＣｕ、Ｎｉ、Ｚｎをそれぞれ０．０５〜５．
０重量％含有させるとさらに優れた効果を示し、直接リ
フロー処理しても剪断強度はいずれも３０ＭＰａ以上で
あり、剪断強度維持率はいずれも６０％以上であること
が判る。As is clear from Examples 1 to 23 in Tables 1 and 2, at least one of Pb, Sn, and In is the main element, and 0.01 to 5.0% by weight Cu, 0.01 ~
2 out of 5.0 wt% Ni and 0.01 to 5.0 wt% Zn
By forming a solder bump using a solder wire containing at least one kind, the shear strength is 20 MPa or more even if the reflow treatment is performed directly, and the shear strength indicating the difficulty of deterioration of the shear strength due to the reflow treatment. It can be seen that the maintenance rate is 50% or more. Here, each of Cu, Ni, and Zn contained in two or more types is contained in an amount of 0.05 to 5.
It can be seen that when the content of 0 wt% is more excellent, the shear strength is 30 MPa or more even if the direct reflow treatment is performed, and the shear strength maintenance ratio is 60% or more.
【００１９】これに対して、Ｐｂ，Ｓｎ，Ｉｎの内少な
くとも１種を主要元素としているものの、０．０１〜
５．０重量％Ｃｕ，０．０１〜５．０重量％Ｎｉ，０．
０１〜５．０重量％Ｚｎの内２種以上を含有していない
場合は、比較例１〜６から明らかな様に、直接リフロー
処理すると剪断強度はいずれも１０ＭＰａ以下であり、
剪断強度維持率はいずれも２５％以下であることが判
る。On the other hand, although at least one of Pb, Sn, and In is used as a main element, 0.01 to
5.0 wt% Cu, 0.01 to 5.0 wt% Ni, 0.
When two or more of 01 to 5.0 wt% Zn are not contained, as is clear from Comparative Examples 1 to 6, the shear strength is 10 MPa or less when subjected to direct reflow treatment.
It can be seen that the shear strength maintenance ratios are all 25% or less.
【００２０】[0020]
【発明の効果】以上説明したように本発明は、半田バン
プ形成に用いる半田材料の組成を上記構成とすることに
より、ＩＣチップＡｌ電極上の半田バンプ材料を直接リ
フロー処理を行っても剪断強度の劣化を低く抑えること
が出来、実用可能な剪断強度を得ることが出来た。従っ
て、Ａｌ電極上に別工程で皮膜形成を行わなければリフ
ロー処理後の剪断強度の劣化が大きいためＡｌ電極上の
半田バンプ材に直接リフロー処理が出来ない従来のもの
に比べて、バンプ電極の形成、半導体装置の製造にかか
る工程が減って時間を要せず、コストも低減出来る。As described above, according to the present invention, the composition of the solder material used for forming the solder bumps has the above-mentioned constitution, so that the shear strength can be obtained even when the solder bump material on the IC chip Al electrode is directly reflowed. Could be suppressed to a low level, and a practical shear strength could be obtained. Therefore, if a film is not formed on the Al electrode in a separate process, the shear strength after the reflow process is greatly deteriorated, and thus the solder bump material on the Al electrode cannot be directly reflowed. The number of steps required for formation and manufacturing of a semiconductor device is reduced, time is not required, and cost can be reduced.
【図１】フリップチップボンディング法の概要を示す簡
略図。FIG. 1 is a simplified diagram showing an outline of a flip chip bonding method.
【図２】フリップチップボンディング法においてＩＣチ
ップにずれが生じた場合を示す簡略図。FIG. 2 is a simplified diagram showing a case where an IC chip is displaced in a flip chip bonding method.
【図３】本発明に係る半田バンプ電極の一実施例を示す
簡略図で、リフロー処理した状態を表す。FIG. 3 is a simplified diagram showing an embodiment of a solder bump electrode according to the present invention, showing a state after reflow processing.
【図４】半田バンプの形成方法及びＩＣチップと基板の
接合の概要を示す簡略図。FIG. 4 is a simplified diagram showing an outline of a method of forming solder bumps and joining of an IC chip and a substrate.
１：ＩＣチップ ２：Ａｌ電極 ３：半田バンプ ４：基板 ５：電極 ６：金属間化合物 1: IC chip 2: Al electrode 3: Solder bump 4: Substrate 5: Electrode 6: Intermetallic compound
───────────────────────────────────────────────────── フロントページの続き (72)発明者 安部 武明 東京都三鷹市下連雀８−５−１ 田中電子 工業株式会社三鷹工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeaki Abe 8-5-1 Shimorenjaku, Mitaka City, Tokyo Tanaka Denshi Kogyo Co., Ltd. Mitaka Factory
Claims (3)
り、ＩＣチップＡｌ電極上でリフローさせた後の剪断強
度が１９ＭＰａ以上であることを特徴とするＩＣチップ
バンプ電極用半田ワイヤ。 〔組成Ｉ〕Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要
元素とし、且つ、Ｃｕ（０．０１〜５．０重量％），Ｎ
ｉ（０．０１〜５．０重量％），Ｚｎ（０．０１〜５．
０重量％）から選ばれる２種以上を含有する。1. A solder wire for an IC chip bump electrode, wherein the composition of the solder material is the following [Composition I], and the shear strength after reflowing on the IC chip Al electrode is 19 MPa or more. [Composition I] At least one of Pb, Sn, and In is a main element, and Cu (0.01 to 5.0% by weight), N
i (0.01 to 5.0% by weight), Zn (0.01 to 5.
0% by weight).
バンプ電極において、半田材料の組成が下記〔組成Ｉ〕
であり、且つ、ＩＣチップＡｌ電極と半田バンプの境界
にＣｕ，Ｎｉ，Ｚｎから選ばれる２種以上を含有する金
属間化合物層を形成してなることを特徴とするＩＣチッ
プ半田バンプ電極。 〔組成Ｉ〕Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要
元素とし、且つ、Ｃｕ（０．０１〜５．０重量％），Ｎ
ｉ（０．０１〜５．０重量％），Ｚｎ（０．０１〜５．
０重量％）から選ばれる２種以上を含有する。2. A solder bump electrode formed on an IC chip Al electrode, wherein the composition of the solder material is the following [composition I]:
The IC chip solder bump electrode is characterized in that an intermetallic compound layer containing two or more kinds selected from Cu, Ni and Zn is formed at a boundary between the IC chip Al electrode and the solder bump. [Composition I] At least one of Pb, Sn, and In is a main element, and Cu (0.01 to 5.0% by weight), N
i (0.01 to 5.0% by weight), Zn (0.01 to 5.
0% by weight).
ンプを介して接合するＩＣチップ半田バンプ電極の製造
方法において、ＩＣチップＡｌ電極上で下記〔組成Ｉ〕
の半田材料をリフローさせることを特徴とするＩＣチッ
プ半田バンプ電極の製造方法。 〔組成Ｉ〕Ｐｂ，Ｓｎ，Ｉｎの内少なくとも１種を主要
元素とし、且つ、Ｃｕ（０．０１〜５．０重量％），Ｎ
ｉ（０．０１〜５．０重量％），Ｚｎ（０．０１〜５．
０重量％）から選ばれる２種以上を含有する。3. A method for manufacturing an IC chip solder bump electrode, which comprises bonding an IC chip Al electrode and a substrate electrode via solder bumps, wherein the following [composition I] is formed on the IC chip Al electrode.
2. A method for manufacturing an IC chip solder bump electrode, comprising reflowing the solder material according to 1. [Composition I] At least one of Pb, Sn, and In is a main element, and Cu (0.01 to 5.0% by weight), N
i (0.01 to 5.0% by weight), Zn (0.01 to 5.
0% by weight).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6149277A JPH0817836A (en) | 1994-06-30 | 1994-06-30 | Solder wire, solder bump electrode, and method for manufacturing solder bump electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6149277A JPH0817836A (en) | 1994-06-30 | 1994-06-30 | Solder wire, solder bump electrode, and method for manufacturing solder bump electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0817836A true JPH0817836A (en) | 1996-01-19 |
Family
ID=15471701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6149277A Pending JPH0817836A (en) | 1994-06-30 | 1994-06-30 | Solder wire, solder bump electrode, and method for manufacturing solder bump electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0817836A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001504760A (en) * | 1997-02-10 | 2001-04-10 | アイオワ ステイト ユニヴァーシティ リサーチ ファウンデーション、インク． | Lead free solder |
| JP2002185130A (en) * | 2000-12-11 | 2002-06-28 | Fujitsu Ltd | Electronic circuit devices and electronic components |
-
1994
- 1994-06-30 JP JP6149277A patent/JPH0817836A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001504760A (en) * | 1997-02-10 | 2001-04-10 | アイオワ ステイト ユニヴァーシティ リサーチ ファウンデーション、インク． | Lead free solder |
| JP2002185130A (en) * | 2000-12-11 | 2002-06-28 | Fujitsu Ltd | Electronic circuit devices and electronic components |
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