JPH08180611A - Data recording and reproducing method and device and data transmitting method and device - Google Patents

Abstract

PURPOSE: To enhance the error correcting capability and to exactly reproduce data by restoring even such a continuous large error as to be uncorrectable in a min. distance between codes of a 1st error processing data to its original state. CONSTITUTION: At the time of a reproducing operation mode, an Mo signal obtained by an I-V matrix amplifier 16 from a detecting output of a photodetector 15 or an RF signal is clamped up to a prescribed voltage by a selector/ clamper circuit 33. Afterward, this signal is digitized by an A/D converter 34 and is supplied to a read/write circuit 38. In the circuit 38, the reproducing signal digitized by the converter 34 is processed with a digital filter to meet a partial response, and afterward, an NRZI group data is reprodeced by viterbi decoding. In this case, even such a continuous large error as to be uncorrectable in the min. distance between codes of the 1st error processing data can be restored to its original state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recording / reproducing method and its apparatus, and a data transmitting method and its apparatus, which are suitable for application to, for example, an optical disk drive.

[0002]

2. Description of the Related Art As an optical disk, a magneto-optical disk,
Phase change type optical disks, write-once disks, read-only optical disks, etc. have been proposed. These optical disks can be roughly classified into writable disks and read-only disks.

In a magneto-optical disk as a writable disk, if a defect (defective) sector is detected in disk certifying performed at the time of manufacturing, the sector next to the defective sector is set as a replacement sector and this information is read by an optical disk. It is recorded in a predetermined area of the magnetic disk, and at the time of reproduction, a replacement sector of the defective sector is used. When a new defective sector occurs after shipment, the replacement sector of the defective sector is set in the area dedicated to the replacement sector of the defective sector, and the data to be originally recorded in the defective sector is recorded in the replacement sector. The information is recorded in a predetermined area of the magneto-optical disk.

On the other hand, in a read-only optical disc, data is not recorded by an optical disc drive, and as is well known, data is recorded at the time of manufacture, and after shipment, only the data recorded at the time of manufacture is read. Is.

Further, when data is recorded on the magneto-optical disk by an optical disk drive, or when data is recorded on the read-only optical disk at the time of manufacturing, parity or error for error correction is added to each data. CRC (Cyclic Redundan) for checking
A parity such as cy check) is added. Therefore, at the time of reproduction, even if it is a magneto-optical disk,
Even with a read-only optical disc, error checking and error correction processing is performed on the reproduced data by parity.

As this parity, a parity for forming a Reed-Solomon code is known. In the Reed-Solomon code, when one symbol has 8 bits and data has k symbols, parity is added to the data of k symbols to make a total of n symbols. At this time, there is a word "minimum distance" as a word indicating the correction capability of the code for error correction.

For example, in the case where one symbol has one bit, the n symbols are represented by n bits.
There are 2 ⁿ binary data strings that the symbol can take. On the other hand, since only 2 ^k kinds of data except parity are required, 2 ^k kinds of data strings are extracted from the 2 ⁿ kinds of data strings, and a bit of different d bits is extracted between any two extracted data strings. When there was this d
About distance. Then, the minimum value when the distance is similarly obtained for all of the 2 ^k data strings is called the minimum distance. In the following description, this "minimum distance" will be referred to as the distance.

In general, the distance d of the code for correcting t1 errors must satisfy the following (formula 1).

D ≧ 2t1 + 1 (Equation 1)

For example, when the distance d is 17, t
1 becomes 8. In other words, it is possible to correct only up to 8 symbols.

In addition to the correction ability, the above-mentioned code
It also has the ability to detect when an error has occurred. If the number of error detections capable of detecting an error by the ability to detect the occurrence of this error is t2, this number of error detections t2
Can be expressed by the following (formula 2).

T2 = d− (2t1 + 1) (where t2 ≧ 0) (Equation 2)

For example, the number of error corrections t1 and the number of error detections t2 when the distance d is 17 are as shown in the following (Table 1).

0 symbol correction ... t1 = 0, t2 = 16 1 symbol correction ... t1 = 1, t2 = 14 2 symbol correction ... t1 = 2, t2 = 12 3 symbol correction ... t1 = 3, t2 = 10 4 symbol correction ... t1 = 4, t2 = 85 5 symbol correction ... t1 = 5, t2 = 6 6 symbol correction ... t1 = 6, t2 = 4 7 symbol correction ... t1 = 7, t2 = 2 8 symbol correction ... t1 = 8, t2 = 0 ... (Table 1)

As is clear from this (Table 1), the number of detected errors is "0" in the 8-symbol correction. Therefore, if an error of 9 symbols or more occurs, the error may not be correctly discriminated. It occurs. Therefore, if the distance d is set to a large value, the number of correctable points can be increased and the error detection capability can be maintained. The Reed-Solomon code configured as described above is an LDC (Long Distan) of (n, k, d) in the sense that the distance d is relatively large.
ce Code: Long Distance Code).

In a magneto-optical disk or a read-only optical disk, recording is performed after the above-described Reed-Solomon code is formed, so that a random error, a distance d value, an error correction number t1, an error detection number are reproduced. A burst error having a length corresponding to t2 can be corrected.

By the way, as can be seen from the above (Table 1), for example, when the distance d is 17, the maximum number of error corrections is eight. Therefore, when a burst error occurs in which 9 or more pieces of data are consecutively in error, error correction cannot be performed and incorrect data is used.

In a writable disc such as a magneto-optical disc, if there is a defective sector, replacement processing is performed so that data can be recorded in the replacement sector so that good reproduction can be always performed. In order to deal with the above burst error, a parity sector is provided at one location on one or more circumferences of the disk, and the exclusive OR of the data of other sectors on one or more circumferences of the disk is used as the parity. A method is also adopted in which data is recorded in a parity sector, and when a burst error occurs, error correction of data related to the error is performed based on the parity read from the parity sector.

However, when the method of performing the replacement process is adopted, the processing speed becomes slower by performing the replacement process. In particular, when processing data that must be processed in real time, such as in the case of moving image data, slow processing speed is a problem. Also, when a method of performing error correction using a parity sector is adopted, when a burst error occurs, the data recorded in the area is reread, and the reread data and the data recorded in the parity sector are recorded. Error correction must be performed using existing parity data. Therefore, when a burst error occurs, the time spent for error correction processing becomes long.

On the other hand, in the case of a read-only optical disc, the replacement process cannot be performed. Therefore, when a large error such as a burst error occurs at the time of reproduction, only the pre-recorded code for error correction is used. Must. Therefore, there is no choice but to adopt a method of making the distance d a large value or performing error correction using a parity sector. However, if the distance d is set to a large value, the redundancy of the code increases and the processing time increases, and the capacity for recording the original data decreases as much as the redundancy increases. . When a method of performing error correction using a parity sector is adopted, when a burst error occurs, the data of all sectors recorded in the area is reproduced again, and the reproduced data and the parity Error correction must be performed using the data as parity recorded in the sector,
When a burst error occurs, there is a problem that the time spent for the processing becomes long.

The present invention has been made in consideration of the above points, and even when a burst error occurs, it is possible to efficiently perform processing and perform good reproduction without reducing the data recording capacity. The present invention is intended to propose a data recording / reproducing method and a data transmission device which can be performed.

[0022]

One of the main inventions of the present invention is to: (a) generate a first error processing data for each of a series of data of a predetermined amount, and Second error processing data is generated for each of a plurality of blocks obtained by dividing the series of data, and (b) the series of data of the predetermined amount, the first error processing data, and the first series of data. Data of each recording unit is generated from the error processing data of 2, (c) the data of each recording unit is recorded on a recording medium, and (d) the data of each recording unit is reproduced from the recording medium, (E) Error correction is performed by the first error processing data for each recording unit on a series of data consisting of the predetermined amount of the reproduced data of each recording unit, and (f) the step. Error correction in (e) If not, at least error detection is performed on the series of data consisting of the predetermined amount for each block by the second error processing data, and (g) continuous N (N is a positive integer). ) When an error is detected in the blocks, all the data of at least one block which is not the end of the continuous N blocks is regarded as the lost data, and the first error processing data is used. The step of obtaining reproduced data by performing error correction on a series of data of the above-mentioned predetermined amount of the recording unit.

According to the present invention described above, even large continuous errors that cannot be corrected with the minimum code distance of the data for the first error processing are restored.

Further, according to the present invention described above, in the case where the error occurrence state is an error extending over a plurality of blocks, the data of at least one block in the approximate center of the plurality of blocks extending over the error, and It is considered that the data of the block adjacent to at least one block regarded as the erasure has disappeared, and the error correction processing is performed by the data for the first error processing.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the structure of an optical disk drive. This optical disk drive records data to and reproduces data from a magneto-optical disk and a write-once disk, reads data from a read-only optical disk, and writes to and reads from a so-called partial ROM, which includes a writable area and a writable area. Data can be written and read, and data can be read from the read-only area.

In FIG. 1, the drive 1 records data on the optical disc 4 and reproduces data from the optical disc 4. The drive controller 2 controls the drive 1. The drive 1 is a SCSI (Small Com) of the drive controller 2.
It is connected to the host computer 3 via an input / output terminal io1 dedicated to a computer system interface. Then, the drive 1 is accessed by the host computer 3 via the drive controller 2.

Here, as the optical disk 4, there are a magneto-optical disk, a phase change type optical disk, a write-once disk, a partial disk having a writable area (RAM) and a read-only area (ROM), a read-only optical disk, and the like. It can be used.

The drive 1 includes a loading mechanism 5 for loading an optical disc 4, and a loading mechanism 5.
A spindle motor 6 for rotating the optical disc 4 loaded by the driver 7, a driver 7 for driving the spindle motor 6, an optical block 8, a driver 14 for driving a laser diode 13 of the optical block 8,
A reproduction signal or the like from the optical block 8 is IV (current / current)
Voltage) conversion and supplies the voltage to a plurality of systems IV /
It is composed of a matrix amplifier 16, a magnetic head 17 for applying a magnetic field to the optical disc 4, and a driver 18 for driving the magnetic head 17. Here, the above IV
The / matrix amplifier 16 obtains an RF signal and an MO (magneto-optical) signal by combining a large number of outputs from the photo detector 15 of the optical block 8 described later.

The optical block 8 irradiates the optical disc 4 with the laser light from the laser diode 13, and the lens system 9 and the optical block 10 for causing the reflected light reflected by the optical disc 4 to enter the photodetector 15. Slide motor 10 for moving in the radial direction, galvano motor 11, focus actuator 12 for focusing, laser diode 13
Composed of.

Driver 1 for driving this magnetic head 17
8 is connected to the output terminal 2o1 of the drive controller 2 via the input terminal 1i1. The driver 14 for driving the laser diode 13 includes input terminals 1i2 and 1i2.
It is connected to the output terminals 2o2 and 2o3 of the drive controller 2 via i3, respectively. The IV / matrix amplifier 16 has output terminals 1o1, 1o2, 1o3, 1o4,
The input terminals 2i1, 2i2, 2i3, 2i4, 2i5 of the drive controller 2 are connected via 1o5, respectively. The focus actuator 12 has an input terminal 1i4.
Is connected to the output terminal 2o4 of the drive controller 2. The galvano motor 11 is connected to the output terminal 2o5 of the drive controller 2 via the input terminal 1i5. The slide motor 10 is connected to the output terminal 2o6 of the drive controller 2 via the input terminal 1i6. The driver 7 of the spindle motor 6 receives the output terminal 2 of the drive controller 2 via the input terminal 1i7.
connected to o7. The loading mechanism 5 has an input terminal 1
Output terminal 2o of the drive controller 2 via i8
8 is connected.

The process for sending and receiving commands and data is performed by the drive controller 2. At the time of recording, the drive controller 2 adds CRC or an error correction code to the data from the host computer 3 and transfers the data to the drive 1. At the time of reproduction, the drive controller 2 responds to the data from the drive 1. Then, error correction processing is performed and only the user data portion is transferred to the host computer 3. At the time of recording the data and reproducing the data, the commands to the servo system and each block of the drive 1 are issued to the drive controller 2
Done by

FIG. 2 is a block diagram showing a configuration example of the drive controller 2 shown in FIG. In FIG. 2, the input / output circuit 31 receives the bias data of the laser diode 13 supplied from the digital signal processing circuit 53 via the bus 43 from the DA converter 32 and the output terminal 2o.
2 is supplied to the driver 18 shown in FIG. The selector / clamp circuit 33 has input terminals 2i1 and 2i.
The output supplied from the IV / matrix amplifier 16 shown in FIG. 1 via 2 is selected based on the timing signal from the servo system timing generator 40 described later, and the selected output is clamped. The A / D converter 34 converts the output from the selector / clamp circuit 33 into digital data based on the selected servo system clock signal or data system clock signal from the selector 41.

The data system clock generation circuit 34 generates a data system clock signal based on the servo system clock signal from the servo system clock generation circuit 39. The data system timing generator 36 generates a data system timing signal based on the data system clock signal. The data phase control circuit 37 controls the phase of the data system clock signal from the data system clock generation circuit 35 on the basis of the phase reference data extracted from the reproduced data from the A / D converter 34 to read / write. The clock is supplied to the writing circuit 38 as a clock for reading, and the phase of the writing position control signal from the reading / writing circuit 38 is controlled,
Output through the output terminal 2o1.

At the time of reproduction, the read / write circuit 38 responds to a request signal from the controller 44 based on the data system clock signal from the data system clock generation circuit 35 and the data system timing signal from the data system timing generator 36. , A-D converter 3
The output of No. 4 is supplied to the controller 44, and an acknowledge signal is output. Further, the read / write circuit 38 outputs the data from the controller 44 at the time of recording to the output terminal 2o1 and the input terminal 1i shown in FIG.
1 to the driver 18.

The servo-system clock generation circuit 39 is AD
A servo system clock signal is generated from the output of the converter 34, and the servo system clock signal is supplied to the servo system timing generator 40, the selector 41, and the address decoder 42, respectively. The servo system timing generator 40 generates a servo system timing signal based on the servo system clock signal from the servo system clock generation circuit 39, and the servo system timing signal is sent to the selector 41, the address decoder 42, and the selector / clamp circuit 33. In addition to supplying respectively, the driver 1 of the laser diode 13 via the output terminal 2o3 and the input terminal 1i3 shown in FIG.
4

The multiplexer 45 is connected to I- shown in FIG.
V / matrix amplifier 16 to input terminals 2i3, 2i4
And the front APC (A
Automatic Power Control) signal, focus error signal and pull-in signal
Supply to the converter. The input / output circuit 47 supplies the output of the AD converter 46 to the digital signal processing circuit 53 via the bus 43. The PWM (pulse width modulation) circuit 48 modulates the data for driving the optical block 8 supplied from the digital signal processing circuit 53 via the bus 43.

The driver 49 has an output terminal 2o4 and FIG.
It is connected to the focus actuator 12 via the input terminal 1i4 shown in FIG. The driver 49 drives the focus actuator 12 shown in FIG. The driver 50 has an output terminal 2o5 and the input terminal 1 shown in FIG.
It is connected to the galvano motor 11 via i5. The driver 50 drives the galvano motor 10 shown in FIG. The driver 51 is connected to the slide motor 10 via the output terminal 2o6 and the input terminal 1i6 shown in FIG. The driver 51 drives the slide motor 11 shown in FIG.

The input / output circuit 52 supplies the drive signal from the digital signal processing circuit 53 to the spindle motor 6 via the output terminal 2i6 and the driver 7 shown in FIG. The digital signal processing circuit 53 is connected to the controller 44 via a bus shown by a thick solid line. And
The digital signal processing circuit 53 controls and drives each of the above blocks via the bus 43.

The digital signal processing circuit 53 is used when the optical disk 4 is mounted on the spindle motor 6 by the loading mechanism 5 in response to a request from the host computer 3 or when the automatic spin-up mode is set. When the optical disc 4 is loaded by the loading mechanism 5, the
The driver 7 is instructed to drive the spindle motor 6 to rotate.

When the spindle motor 6 reaches a predetermined number of rotations, the driver 7 outputs a lock signal to notify the digital signal processing circuit 53 that the rotation of the spindle motor 6 is stable. During this time, the digital signal processing circuit 53 causes the driver 51 to position the laser beam from the laser diode 13 outside the user area of the optical disc 4 via the PWM circuit 48, and causes the driver 51 to move the optical block 8 to the optical block 8. The optical disc 4 is moved to the outer or inner side.

When the focus is pulled in the user area, the data on the highly sensitive disc may be erased by mistake, but the optical block 8 is placed outside the user area.
Such erroneous erasure can be prevented by moving the mark and pulling the focus outside the user area.

When the spindle motor 6 rotates at a constant speed and the optical block 8 moves to the outer peripheral side, for example,
The digital signal processing circuit 53 includes an input / output circuit 31 and D
The laser diode 13 provided in the optical block 8 is provided to the driver 14 via the -A converter 32.
Of the servo system timing generator 4 for controlling the on / off of the laser diode 13 by setting the bias current of
A command is output to 0 to turn on the laser.

The laser beam emitted from the laser diode 13 is incident on the photodetector 15 provided in the optical block 8, and the photodetector 15 is provided with the photodetector 15.
Is converted into an electric signal by the above, supplied to the IV / matrix amplifier 16 as a detection output, converted into a voltage, and supplied to the multiplexer 45 as a front APC signal.

This front APC signal is a signal selected by the multiplexer 45 in a time division manner.
It is digitized by the A / D converter 46 and supplied to the digital signal processing circuit 53 via the input / output circuit 47 and the bus 43. The digital signal processing circuit 53 is
The light quantity of the laser beam emitted from the laser diode 13 is recognized by the digitized front APC signal, and the light quantity control data calculated by a digital filter (not shown) is used as the input / output circuit 31 and DA.
The power of the laser diode 13 is controlled to be constant by returning to the driver 14 via the converter 32.

Next, the digital signal processing circuit 53 causes the P
By passing a current from the WM circuit 48 to the driver 49, the focus actuator 12 of the optical block 8
The focus actuator 1 by driving the
2 is put into the focus search state. At this time, the laser beam reflected by the optical disk 4 is incident on the light receiving surface of the photodetector 15. The laser beam received by the photodetector 15 is converted into an electric signal and supplied to the IV / matrix amplifier 16 as a detection output. The IV / matrix amplifier 16 converts the laser beam into a voltage and amplifies the focus signal. The error signal is output and supplied to the multiplexer 45.

This focus error signal is sent to the front A
Similar to the PC signal, the signal selected in time division by the multiplexer 45 is digitized by the AD converter 46 and supplied to the digital signal processing circuit 53 via the input / output circuit 47 and the bus 43. It The digital signal processing circuit 53 feeds back focus control data obtained by digitally filtering the digitized focus error signal from the PWM circuit 48 to the driver 49, thereby performing focus control servo. Make a loop. When the focus control becomes stable, it is output from the photo detector 15,
The RF signal obtained through the IV / matrix amplifier 16 has a constant amplitude and is clamped to a predetermined potential by the selector / clamp circuit 33, and then A
Digitized by the -D converter 34.

The clock at this time has a frequency in the free running state of the servo system clock generation circuit 39. A signal obtained by dividing the frequency of the free run by a predetermined value is also used for the timing pulse for performing the clamp.

The servo-system clock generation circuit 39 uses AD
By checking the amplitude difference of the digitized RF signal by the converter 34, the pattern of pits formed on the optical disc 4 is checked to find the same pattern as the pit row in the servo area. Then, when the pattern is found, the servo system clock generation circuit 39 controls the clock selector 41 so as to open the window at the position where the next pattern should appear, and again checks whether the patterns match.

When this operation can be continuously confirmed a certain number of times, the servo system clock generation circuit 39 considers that the pattern of the pits of the optical disk 4 is locked. The phase information is obtained by taking the amplitude difference between both shoulders of the wobble pit in the servo area. Furthermore, by adding the phase information obtained from both of the two wobble pits, the gain fluctuation caused by the amplitude change due to the tracking position is absorbed.

When the servo system clock generation circuit 39 is locked, the position of each segment becomes clear and the position of the segment mark pit formed on the optical disk 4 can be recognized. The segment mark pit, the address mark pit, the sector flag A plurality of predetermined positions Ar1, Ar2, A for one pit and two sector flag pits
A position having the maximum amplitude is searched for in the RF signals sampled by r3 and Ar4.

When the result is Ar1, it is an address mark, this segment is an address segment, and the beginning of the frame can be recognized. Therefore, it is possible to establish frame synchronization by clearing the frame counter. . When one frame is composed of 14 segments, the clock selector 41 is controlled so as to open a window every 14 segments, and it is determined that the frame synchronization is locked when the address marks can be continuously recognized.

When the frame synchronization is applied, the position where the address is recorded on the optical disk 4 can be recognized, so that the address decoder 42 decodes the track address and the frame code. This address decoder 42
In this case, it is performed by checking that the pattern coded by 4 bits is gray-coded with the gray code table. However, because it is gray coded not only for 4 bits but for the whole, instead of simply looking for a match, comparison with a table inverted depending on whether the LSB of the upper 4 bits is "1" or "0" I do.

Here, the first decoded frame code is loaded into the frame counter, the numerical value obtained by incrementing this frame counter for each frame is compared with the actually reproduced frame code, and the consecutive frame codes are successively compared. When it is confirmed that they match, it is assumed that the rotation is synchronized. After that, the numerical value obtained by the frame counter is returned to the digital signal processing circuit 53 as a frame code so that the frame position is not erroneously recognized even if there are some defects.

Further, the digital signal processing circuit 53 calculates the speed of the optical block 8 while reading the gray coded track address, and the slide motor 1 of the optical block 8 is operated from the PWM circuit 48 via the driver 51.
By controlling 0, the optical block 8 is moved to the target track on the optical disc 4.

Then, the digital signal processing circuit 53 is
When the position of the optical block 8 reaches the target track position, the tracking operation starts. As described above, the tracking error signal is obtained by taking the difference between the amplitude values of the RF signal for the two wobble pits in the servo area. The digital signal processing circuit 53 controls the galvano motor 11 of the optical block 8 via the driver from the tracking control data obtained by digitally filtering this value, so that the low frequency component is obtained. And the tracking control is performed so that the spot of the laser beam from the laser diode 13 is located at the center of the track of the optical disc 4.

The digital signal processing circuit 53 detects the head position of the target sector in the tracking state as described above. As described above, the sector at the beginning of each sector and the segment immediately before the sector have sector marks, and each sector mark has the above-mentioned four positions Ar1 and Ar.
The selector 41 is controlled to open windows at 2, Ar3 and Ar4, and the four positions Ar1, Ar2, Ar
When the position where the maximum amplitude is among the RF signals sampled by 3 and Ar4 is position Ar2, it indicates that it is the first segment of the sector, and when it is position Ar3, it is the segment immediately before the beginning of the sector. Indicates that there is.

Basically, the segment at the beginning of a sector is determined by converting the sector address given by the host computer 3 into a physical sector and calculating which segment of which track the sector is. To be done. However, the probability that the two types of sector marks become defective at the same time is extremely low, and the probability of defective sectors due to this is extremely low.

Further, the data system clock generation circuit 35 is
A frame-synchronized servo clock obtained from the servo system clock generation circuit 39 is multiplied by M / N to generate a data clock, and this data clock is generated by the data system timing generator 36 and the read / write circuit 38.
Give each to.

In the recording operation mode, the recording data is supplied from the host computer 3 to the read / write circuit 38 via the controller 44. Then, the read / write circuit 38 performs a scramble process in sector units according to Y = X ⁷ + X + 1 by adding (exclusive OR) a random number of 127 cycles to the record data, and the scrambled record data is obtained. To NRZI series data synchronized with the data clock. At this time, the initial value is set to "0" for each segment,
The modulated signal is supplied to the magnetic head 17 via the driver 18.

The magnetic head 17 generates a magnetic field according to the modulation signal, and by applying this magnetic field to the data area of the optical disc 4 heated to the Curie temperature by the laser beam emitted from the laser diode 13,
Record the NRZI series of data.

In the reproducing operation mode, the MO signal or RF signal obtained by the IV / matrix amplifier 16 from the output detected by the photodetector 15 is clamped to a predetermined potential by the selector / clamp circuit 33, and then A- It is digitized by the D converter 34 and supplied to the read / write circuit 38. Then, the read / write circuit 38 performs digital filter processing on the reproduced signal digitized by the AD converter 34 in accordance with the partial response and then reproduces the NRZI series data by Vidabi decoding. Then, after converting this NRZI series data into NRZ series data in segment units, it is descrambled in sector units and converted into reproduction data, and this reproduction data is transferred to the host computer 3 via the controller 44. The MO signal and the RF signal are obtained as a result of being operated by different combinations among the many outputs from the photodetector 15.

FIG. 3 is a block diagram showing a configuration example of the controller 44 shown in FIG. Controller 44 shown in FIG.
A bus 61 including an address, data, and control bus is connected to the CPU 60, and a ROM 62 in which various program data, parameter data, and the like for performing processing during a reproducing operation are stored in the bus 61,
A RAM 63 used as an area for work such as program data stored in the ROM 62, an input / output port 64, a decoder 67 for performing error correction and error check on reproduced data, and parity for data supplied from the host computer 3. An encoder 68 for generating and adding the generated parity to the data, a buffer 70, and an interface circuit 71 are connected and configured.

The input terminal 65 is read / read as shown in FIG.
The write circuit 38 and the movable contact 66c of the switch 66 are respectively connected. One fixed contact a of this switch 66
Is connected to the input terminal of the decoder 67, and the switch 66
The other fixed contact b is connected to the output terminal of the encoder 68.

The data output terminal of the decoder 67 is connected to one fixed contact a of the switch 69. The input terminal of the encoder 68 is connected to the other fixed contact b of the switch 69. The movable contact c of this switch 69
Are connected to the input / output terminals of the buffer 70. The input / output terminal of the buffer 70 is the interface circuit 71.
Connected to the input / output terminals of. The input / output terminal of the interface circuit 71 is connected via the input / output terminal io1 as shown in FIG.
Connected to the input / output terminals of the host computer 3 shown in FIG.

Here, the decoder 67 performs error detection on the reproduction data supplied via the switch 66 using the first ECC, and the number of detected errors becomes a number that cannot be corrected. At the same time, an error check is performed using the CRC, and when an error is detected, an error detection process using the second ECC is further performed.

The decoder 67 has RAMs 67a and 67b.
By controlling the reproduction data written in the RAMs 67a and 67b, the error correction processing by the LDC, the error check by the CRC, and the 2ndEC at the time of the burst error that makes these corrections and checks impossible.
It is composed of a RAM controller 67c which detects an error in C. Hereinafter, error detection using the second ECC will be referred to as “error check”. Here, the RAM
67a and 67b each have a capacity of one sector (2352 bytes in this example) for storing reproduced data, and a capacity for storing various data generated in error detection processing and error correction processing described later. And has a total capacity of.

The output of this decoder 67 is the switch 69.
Is supplied to the buffer 70 via. Where 2ndE
The CC is a parity recorded in a predetermined area of a sector next to the sector among ECC parities generated by the data of the sector being recorded. And this 2nd ECC
Is 1stE for data of a certain sector when decoding
When the error correction by the parity as CC is impossible or when the error is detected when the error check by CRC is performed, the parity used for detecting the error position of the data of the sector. is there.

As shown in FIG. 3, the encoder 68 has RAMs 68a and 68 each having a storage capacity of one sector.
b and the input data written in the RAMs 68a and 68b, respectively, are controlled to generate the parity as the first ECC, the parity of the CRC, the parity as the second ECC, and the addition of these parities. However, the encoder 68 adds only the parity as the second ECC generated for the user data of a certain sector to the user data of the next sector.

The encoder 68 is the host computer 3
The above-mentioned parity is added to each of the data transferred from the above, and the parity as the second ECC of the preceding sector is added.

In the optical disk drive shown in FIG. 1, the check parity and the error correction parity can be recorded in the writable areas of the magneto-optical disk, the write-once disk and the partial disk. Therefore, in the case of a read-only area of a read-only optical disk or a partial disk, the parity is recorded when the disk is manufactured.

The input / output terminal 72 connected to the input / output port 64 is connected to the bus 43 of the digital signal processing circuit 53 shown in FIG. The output terminal 73 is connected to the input terminal for the acknowledge signal of the read / write circuit 38 shown in FIG. The input terminal 74 is connected to the output terminal for the request signal of the read / write circuit 38 shown in FIG.

First, a case where the data transferred from the host computer 3 is recorded on the optical disc 4 will be described. In this case, the CPU 60 uses the input / output port 64
A switching control signal is supplied to the switches 66 and 69 via the switch 66 to connect the movable contacts c of the switches 66 and 69 to the fixed contacts b. As a result, the recording data transferred from the host computer 3 is read out from the buffer 70 and then transmitted via the switch 69 to the encoder 6
8, the encoder 68 adds a code for error detection and error correction, and then supplies the read / write circuit 38 shown in FIG. 2 through the switch 66 and the output terminal 65. It is recorded in the user area of the optical disc 4.

At this time, the encoder 68 uses the RAM 68.
Parity is added to the data of a certain sector (N sector) stored in a, and when the processing for recording is completed, the data of the N sector is input / output terminal 65 through the switch 63. To the CPU 6 via the input / output port 64 and the bus 61.
Supply 0. As a result, the CPU 60 instructs the read / write circuit 38 shown in FIG. 2 to perform recording, and also controls the buffer 70 and the interface circuit 71 to receive the next input data.
As a result, all the data in the N sector is supplied to the drive 1 and recorded on the optical disc 4. Then, during this period, the next input data is written in the RAM 68b as the data of the next sector (N + 1 sector).

Next, the operation during reproduction will be described. C
The PU 60 receives the switch 66 via the input / output port 64.
And 69 are supplied with switching control signals, respectively, to connect the movable contacts c of the switches 66 and 69 to the fixed contact a. By this, it is read from the optical disc 4,
The reproduction data supplied through the read / write circuit 38, the input / output terminal 65 and the switch 66 is the decoder 6
7 and the decoder 67 performs error detection and error correction processing, and then the switch 69, the buffer 70, the interface circuit 71, and the input / output terminal i.
It is supplied to the host computer 3 shown in FIG. 1 via o1.

At this time, the decoder 67 has the RAM 67a.
When the error correction cannot be performed due to the error correction by the parity as the 1st ECC, the error check by the parity of the CRC, and the burst error or the like for the data of the N sector stored in the RAM 67b, the data is stored in the RAM 67b. 2ndEC out of N + 1 sector data
The parity as C is read, and the error position is detected by the parity of the 2nd ECC. Then, the decoder 67 recognizes the position of the error and again performs the 1st
Data of N sector is corrected by performing error correction with parity as ECC, and then error check with parity of CRC is performed.

The decoder 67 outputs the data of N sectors at the time when the reproduction process described above is completed, and
A signal indicating that the reproduction process is completed is input / output port 64.
And to the CPU 60 via the bus 61. As a result, the CPU 60 instructs the read / write circuit 38 shown in FIG. 2 to reproduce the next sector.
As a result, all the data in the N sector is stored in the buffer 7
0 is supplied. Then, the reproduction data of N + 2 sectors read from the optical disc 4 is supplied to the RAM 67a.

The optical disk drive shown in FIGS. 1 to 3 is a disk having only a writable area such as a read-only optical disk or a partial disk, a disk having a writable area in addition to the read-only area, a magneto-optical disk, and the like. A disc having only a read-only area such as a write-once disc or a disc having a readable area in addition to the write-only area can be used.

FIG. 4 is an explanatory diagram showing an example of the format of an optical disc to which the recording medium of the present invention is applied. FIG.
As shown in FIG. 2, a GC on which the disc type data and the like are recorded from the outermost circumference to the innermost circumference on the optical disc 4.
P (gray code part) area, CTL (control) area, TEST (test) area, BAND (band) 0 to BAND15 data area, TEST area, C
A TL (control) area and a GCP area are set.
The GCP area is an area in which additional information and address information are recorded, and a pit pattern is formed by a gray code. Therefore, the information in the GCP area can be read even during seeking. The CTL area is an area in which information indicating a media type is recorded and is a TEST area.
The area is an area for trial writing.

FIG. 5 is an explanatory diagram showing an example of a specific format of the optical disc shown in FIG. In FIG.
The GCP area in the top column is the optical disc 4 shown in FIG.
Corresponding to the outermost GCP area, and the areas from the top to the bottom in this order correspond to the areas from the outermost to the innermost areas of the optical disc 4 shown in FIG.

In this example, the case where the zone CAV is used will be described as an example. Therefore, as shown in FIG. 5, the data clock differs for each zone.

6 to 8 are explanatory views showing an example of the sector format. That is, the contents of one sector are shown in FIGS. As described above, when the optical disc 4 is a magneto-optical disc or a write-once disc, or when the recording is a writable area of a partial disc, each data forming the sector format shown in FIG. When the optical disc 4 is a read-only optical disc or is a writable area of a partial disc when recording is performed by the optical disc drive shown in FIG. Will be recorded.

In FIGS. 6 to 8, i indicates a codeword (row in the drawings), j indicates a byte, solid arrows indicate a writing direction, and data indicated by D0 to D2047 is user data. Indicates (P1, P2)
The data indicated by (P35, P36) is i = 1, respectively.
30-123, ..., The user data D0-D127, ..., D1920-D2 indicated by i = 10-3
047 indicates a parity, 0 (Q1, Q2) indicates the parity for P1 to P36, and (Q3, Q4) indicates a parity for P0.
1 to P36 and the parity for the parity (Q1, Q2), and the data indicated by CRC1 to CRC8 indicates the error checking parity for the user data D0 to D2047.

The data indicated by (E1, 1) to (E16, 16) is the user data D0 to D2047 indicated by j = 0 to j = 15 and the parities P1 to P3, respectively.
6 and CRC1 to CRC8 are Reed-Solomon code parities. That is, parity (E1, 1)-
The parity of j = 0 consisting of (E1, 16) is the data D
0, D16, ... D2032, and j = 0, i = 1
It is a parity for the data indicated by 30-0. Also, j = parity (E2, 1) to (E2, 16)
1, i = −1 to −16, the data is j = 1, i
= 130 to 0 is the parity for the data. Similar parity is provided for the other rows.

By the way, as described with reference to FIGS. 6 to 8, when the Reed-Solomon code is configured for the data of each row indicated by i = 147 to -16, the distance is as described above. Are 17 respectively. Therefore,
As can be seen from (Table 1), when errors occur continuously, up to 8 errors can be detected and corrected, but when 9 or more errors occur consecutively, the error can be corrected. Can't do.

Therefore, in this example, as described above, i = 130, j = 0 to i = 3, j = 15 and i =
Parities P1 to P36 as 2nd ECC for error check and correction are generated for each data indicated by 0, j = 15 to i = -16, j = 15, and are used at the time of reproduction.

Here, as for the parity (E1, 1) to the parity (E16, 16), the total data in each vertical direction is 147 bytes, and the user data D0 to D204 to be the parity target.
Since the vertical data length of 7 is 131 bytes and the vertical data length of parity is 16 bytes, the distance is 17. Therefore, the Reed-Solomon code is
(147, 131, 17). Incidentally, one codeword is one byte.

Here, 1 sector is 1 as described above.
6 bytes x 147 = 2352 bytes.

Next, the 7th row-8th row-7th row pattern for the sector data shown in FIGS. 6 to 8 will be described with reference to FIG.

As is apparent from FIG. 9, the parities P1 and P2 are generated for all the data of 7 rows from i = 130 to 124 shown in FIGS. 6 to 8, and i = 12.
Parities P3 and P4 are generated for all data of 8 rows from 3 to 116, and parities P5 and P of all data of 7 rows from i = 115 to 109.
6 is generated, and in the same manner, the parity is generated in the order of 7th row, 8th row, and 7th row.

That is, by generating the parities P1 to P40, (114, 112, 3) and (130, 12)
8, 3) and (114, 112, 3), three sets of Reed-Solomon codes are sequentially formed.

In the present example, as described above, when recording data on the optical disc 4, the parity as the first ECC for error correction of the data, the parity of the CRC for data check, and the parity as the second ECC. 7
When the optical disc 4 is a read-only disc, only the parity as the second ECC is recorded in a specific area in the n + 1 sector next to the n sector.

However, also in this example, there is a possibility that uncorrectable data may be generated depending on the manner of occurrence of the burst error during reproduction. Hereinafter, the reason will be described, and then, a method for coping with the occurrence of the burst error will be described with reference to the drawings.

FIG. 10 is an explanatory view showing an example in which one continuous burst error occurs in a sector.

In FIG. 10, SEC shows an arbitrary sector, and SEC 'shows an arbitrary sector SEC in detail. Further, the drawings of these sectors SEC and SEC 'are both based on the case where the 7th row-8th row-7th row pattern described with reference to FIG. 9 is used. Here, a block of data consisting of 7 lines or 8 lines is called a block.

During reproduction, the sector SE shown in FIG.
It is assumed that all the data in the shaded area in C has an error (burst error). Sector SEC
When a burst error as shown in (1) occurs, detection and correction cannot be performed using the above-described parity LDC as the first ECC. This is because the distance L of the parity LDC as the first ECC is “17”, and therefore only an error of 8 bytes can be detected and corrected. Therefore, the parity P as the second ECC described above is used.
1 to P40 can be used to detect erroneous blocks, and erasure correction can be performed by regarding erroneous blocks as erasures. This erasure correction can be performed in the case of the 7th row-8th row-7th row pattern when the burst error is just over the 7th row and the 8th row. In this case, the 15th erasure correction is performed. It should be noted that 16-erasure correction is the maximum in the case of a pattern having only 8 rows.

However, this burst error causes SE
As shown in C ′, when 11 rows are spread across 7-row block-8-row block-7-row block, 22 (= 7
+ 8 + 7) Erasure correction must be performed, and error correction cannot be performed even with the above-described second ECC parities P1 to P40.

Therefore, in this example, firstly, three consecutive blocks like this, for example, a 7-row block-8 is used.
Row block -7 Enables error correction even for a burst error extending over 7 row blocks. Specifically, in the case of this example, the parity P1 to P4 as the second ECC is used.
0 is used to perform error detection, and after that, it is considered that the data for the central 8 rows has been erased, and 8 erasure correction is performed by the parity LDC as the first ECC, and detection and correction is performed with the remaining 4 bytes. , Error detection is performed using the parity P1 to P40 as the second ECC, and after that, it is considered that the data for the central eight rows and the upper and lower N rows have been lost, and 8+ is obtained by the parity LDC as the first ECC.
A method of performing N erasure correction and detecting and correcting the remaining M bytes can be adopted. The pattern is shown below

8 erasure correction and 4 detection correction ... 12 lines 10 (8 + 1 line above and below) erasure correction and 3 detection correction 13 lines 12 (8 + top and bottom) 2 lines) Erasure correction and 2 detection corrections ... 14 lines 14 (8 + upper and lower 3 lines) Erasure correction and 1 detection correction ... 15 lines 16 (8 + upper and lower 4 lines) Erasure correction ...・ ・ ・ ・ ・ ・ 16 lines

The following is a case where the central block has 7 rows. 7 erasure correction and 4 detection correction ... 11 lines 9 (7 + 1 line above and below) Loss correction and 3 detection correction ... 12 lines 11 (7 + 2 lines above and below) ) Erasure correction and 2 detection correction: 13 lines 13 (7 + upper 3 lines) Loss correction and 1 detection correction: 14 lines 15 (7 + upper 4 lines) Loss correction ... .... 15 lines

In any of the patterns, the distance d is "17", and the condition is that it should not exceed "16".

FIG. 11 is an explanatory diagram showing an example in which a plurality of burst errors occur in a sector.

In FIG. 11, SEC shows an arbitrary sector in detail. In addition, this sector SEC
It is assumed that the 7th row-8th row-7th row pattern described with reference to FIG. 9 is used.

As shown in FIG. 11, in this example, 8
When a burst error of more than 8 lines occurs at a position including a block of lines, and a burst error occurs at the positions of two blocks of 7 lines that are respectively distant from the position where the burst error occurs, that is, at the distant positions. 3 shows the case where three burst errors occur.

As described above, when three burst errors occur at distant positions, the error detection is performed by the parities P1 to P40 as the second ECC, and the error flag obtained as a result of the error detection. Number is "3"
In addition, when it is detected that the error flags are continuous, it is considered that the burst errors at three positions at the distant positions occur, the data of any block is considered to be lost, and the loss correction is performed, Detection and correction are performed for blocks other than this.

For example, in this example, the data in the block of 8 rows in which a burst error has occurred is regarded as lost and 8 erasure correction is performed, and 4 detection corrections are made for the data in the block of 2 7 rows in which another burst error has occurred. To apply.

It should be noted that the block in which the burst error has occurred need not be three consecutive blocks, but two blocks may be consecutive and the remaining one block may be a single block.

12 to 15 are flow charts for explaining the operation during reproduction. 12 to 15
In explaining the operation at the time of reproduction using the flowchart shown in FIG. Further, the subroutines SUB1 to SUB3 shown in FIG.
Is for convenience of drawing, and is not made into a subroutine when actually creating a program.

In step S1, it is determined whether or not there is a command. That is, a command including a sector number and sector length data from the host computer 3 to the controller 2 is input / output terminal io1 and interface circuit 7
1 and input / output port 64 to determine whether or not the power is supplied. If "YES", the process proceeds to step S2.

In step S2, the sectors in the required range are sequentially read. However, one sector is read each time the processing shown in step S2 is performed once. That is, the CPU 60 of the controller 44 supplies the request signal to the read / write circuit 38 via the output terminal 73. As a result, as described above, the data of the sector is sequentially read from the optical disc 4 until the sector length designated by the host computer 3 is reached. The data read from the optical disc 4 is read / written by the read / write circuit 3
8 and the input terminal 65 to the switch 66. The CPU 60 supplies a switching control signal to the switches 66 and 69 to connect the movable contacts c of the switches 66 and 69 to the fixed contacts a. As a result, the reproduction data supplied to the switch 66 is supplied to the decoder 67 via the switch 66. Then, the process proceeds to step S3.

In step S3, LDC detection and correction are performed.
That is, in the decoder 67, the parity (E1,
1) to (E16, 16) are used to instruct to perform detection and correction. As a result, in the decoder 67, the data D
Detection and correction are performed on 0 to D2047. Then, the process proceeds to step S4.

At step S4, whether or not the correction is OK, that is,
It is determined whether or not the error can be corrected. If "YES", the process proceeds to step S5, and if "NO", step S5.
Go to 6.

In step S5, the CRC check is OK.
It is determined whether or not. That is, it is determined whether or not there is an error by checking the CRC. If “YES”, the process proceeds to step S6, and if “NO”, the process proceeds to step S9.

In step S6, it is determined whether the command has been completed. That is, it is determined whether or not the reading of all the sectors requested by the command input in step S1 has been completed. If "YES", the process ends, and if "NO", the process returns to step S2.

In step S7, error detection and flag addition by the second ECC are performed. That is, the decoder 67 is instructed to perform error detection using the above-mentioned parities P1 to P40. As a result, the decoder 67 performs error detection processing and error flag generation processing on the data D0 to D2047 for each block.

Specifically, error detection processing is performed for each block, and if there is an error, the block is considered to be lost and a flag indicating that the block is lost is added. For example, the presence / absence of an error is detected using P1 and P2 for the block of i = 130 to 124.
If there is an error, an error flag indicating that the block has a burst error is added. This process is performed for all blocks. And step S
Move to 8.

In step S8, it is determined whether or not the number of error flags ≧ 4 or 0. If “YES”, step S9
If it is "NO", the process proceeds to step S11. In this example, when burst errors occur in four or more blocks in one sector, error correction becomes impossible. Therefore, in step S8, it is determined whether the number of error flags is "4" or more. It should be noted that, when "0", an error is caused by the parity (E1, 1) to (E16, 1).
Even if an error is once detected by using 6), the number of error flags becomes “0” as a result of error detection with the parity P1 to P40 as the second ECC. This is because it is detection.

In step S9, an error message is displayed. Then, the process proceeds to step S10. In step S9, the CPU 60 supplies the message data stored in the ROM 62 to the host computer 3 to display it as a message image on the display of the host computer 3. As the message image, for example, the following message can be considered. "An error occurred, so the sector is being reread."

In step S10, reread of this sector is set. Then, the process proceeds to step S6 again.
In this step S10, the CPU 6 of the controller 44 is
0 indicates the read / write circuit 3 via the output terminal 73.
8 is supplied with a request signal indicating rereading of the sector. Thereby, as described above, the data of the sector is read out again from the optical disc 4.

In step S11, it is determined whether or not the number of error flags is 3, and if "YES", the process proceeds to step S12, and if "NO", the process proceeds to subroutine SUB2 as step 100. "3", which is the determination criterion in step S11, is the number of blocks in which a burst error occurs in one sector, which is the maximum error-correctable value.

In step S12, it is determined whether the flag is a 3 consecutive error flag. That is, it is determined whether or not the blocks to which the three error flags are added are three consecutive blocks, and if “YES”, the process proceeds to the subroutine SUB1 as step S50, and if “NO”, step S150. To the sub-routine SUB3. Here, the determination as to whether or not the three consecutive error flags are made is to determine whether the three blocks in which the burst error has occurred are continuous or distant from each other and perform the most suitable processing in each case.

FIG. 13 shows subroutines SUB1 and SUB.
2 are shown respectively. First, the subroutine SUB1 will be described.

If "YES" is determined in step S12 shown in FIG. 12, the process proceeds to step S51 of the subroutine SUB1. And this step S51
Then, one row of each of the central block and the preceding and following blocks on the central block side is regarded as an erasure and LDC, that is, i
The error erasure correction and the error detection correction are performed by the first ECC indicated by -13 to -16. And step S
It moves to 52. In this step S51, among the above-mentioned examples, the central block and the upper and lower rows of the central block are regarded as erasures and erasure correction is performed, and detection and correction is performed using the remaining distance. When the central block has 7 rows, 9 bytes of erasure correction is performed on these 7 rows and a total of 9 rows above and below the 7 rows, and detection and correction are performed using the remaining distance. In this case, up to 3 bytes can be detected and corrected. When the central block has 8 rows, 10-byte erasure correction is performed on the 8 row block and 10 rows above and below the 8 row block, and the remaining distance is used to perform 3 Detects and corrects up to bytes.

In step S52, it is determined whether the correction is OK. That is, it is judged whether or not the error is corrected, and "Y
If “ES”, the process proceeds to step S5 of the flowchart shown in FIG. 12 again, and if “NO”, step S53.
Move to

In step S53, an error message is displayed. Then, the process proceeds to step S54. In step S53, the CPU 60 supplies the message data stored in the ROM 62 to the host computer 3 to display it as a message image on the display of the host computer 3. As the message image, for example, the following message can be considered.
"An uncorrectable burst error has occurred, so the sector is being reread."

In step S54, reread of this sector is set. Then, the process again proceeds to step S6 of the flowchart shown in FIG. In step S54, the CPU 60 of the controller 44 supplies the read / write circuit 38 via the output terminal 73 with a request signal indicating rereading of this sector. by this,
As described above, the data of the sector is read again from the optical disc 4.

Next, the subroutine SUB2 will be described.

If "NO" is determined in step S11 shown in FIG. 12, the process proceeds to step S101 of the subroutine SUB2. And this step S10
In No. 1, error erasure correction and error detection correction by LDC are performed. Then, the process proceeds to step S102. This step S101 is a burst error if the number of error flags is "2" or "1", that is, if a burst error occurs across two blocks, if a burst error occurs in two separate blocks, respectively. Is a step for performing processing in any of the cases where occurs in one block. Therefore, in this step S101, erasure correction processing is performed by assuming that one block or two blocks of data has disappeared, and error detection (check) is performed when there are two blocks in the remaining distance, and error is detected when one block is lost. Detect and correct.

In step S102, it is determined whether the correction is OK. In other words, determine whether the error could be corrected,
If "YES", the process exits this subroutine SUB2 and moves to step S5 of the flowchart shown in FIG. 10, and if "NO", moves to step S103.

In step S103, an error message is displayed. Then, the process proceeds to step S104. In step S103, the CPU 60 supplies the message data stored in the ROM 62 to the host computer 3 to display it as a message image on the display of the host computer 3. As the message image, for example, the following message can be considered. "We have corrected a correctable burst error, but an error has occurred in the error check, so the sector is being reread."

In step S104, reread of this sector is set. Then, the process again proceeds to step S6 of the flowchart shown in FIG. This step S10
4, the CPU 60 of the controller 44 uses the output terminal 7
3 is supplied to the read / write circuit 38 with a request signal indicating rereading of the sector. by this,
As described above, the data of the sector is read again from the optical disc 4.

14 and 15 show the subroutine SUB3 shown in FIG.

If it is determined in step S12 of the flowchart shown in FIG. 12 that the flag is not the three consecutive error flag, the process proceeds to step S151 of the subroutine SUB3 shown in FIG. In the flow charts shown in FIGS. 14 and 15, a burst error has occurred in three blocks, and at least one block has the other two.
This is the case when they are located apart from one block. Here, if 8 bytes are regarded as lost, error detection up to 4 bytes can be performed with the remaining distance.

In step S151, the first block,
That is, the erasure correction is performed by regarding the top block in FIG. 13 as erasure, and the second and third blocks are
Detect and correct. Incidentally, with respect to the second and third blocks, it is possible to detect and correct an error of up to 4 bytes.

In step S152, it is determined whether or not the correction is OK. If "YES", the process proceeds to step S5 of the flowchart shown in FIG. 12, and if "NO", the process proceeds to step S514.

In step S153, erasure correction is performed by regarding the second block, that is, the middle block in FIG. 13, as erasure, and detection correction is performed on the first and third blocks. Incidentally, with respect to the first and third blocks, it is possible to detect and correct an error of up to 4 bytes.

In step S154, it is determined whether or not the correction is OK. If "YES", the process proceeds to step S5 in the flowchart shown in FIG. 12, and if "NO", the process proceeds to step S154.

In step S155, the erasure correction is performed by regarding the third block, that is, the bottom block in FIG. 13 as erasure, and the detection correction is performed on the first and second blocks. Incidentally, with respect to the first and second blocks, it is possible to detect and correct an error of up to 4 bytes.

In step S156, it is determined whether or not the correction is OK. If "YES", the process proceeds to step S5 in the flowchart shown in FIG. 12, and if "NO", the process proceeds to step S160 in the flowchart shown in FIG. To do.

In step S160, it is determined whether or not there are two consecutive lines. That is, it is determined whether two of the three blocks are continuous blocks, and if “YES”, the step S
If it is “NO”, the process proceeds to step S166.

In step S161, the data for one block extending over two blocks is regarded as lost and the remaining data is detected and corrected. The data in these two blocks which are not considered to be lost can be detected and corrected for errors of up to 4 bytes. And step S
Transition to 162.

In step S162, it is determined whether an error has been detected. If "YES", step S1
If it is “NO”, the process returns to step S164.

In step S163, the error is corrected. Then, the process proceeds to step S165.

In step S164, the position of one block of data regarded as lost is shifted by one row. Then, the process proceeds to step S161. Here, the reason for shifting by one line is that error correction may be possible by shifting the position of the block considered to be lost.

At step S165, the error correction is OK.
If “YES”, the process proceeds to step S6 of the flowchart shown in FIG.
If “O”, the process proceeds to step S166.

In step S166, an error message is displayed. Then, the process proceeds to step S167. In step S166, the CPU 60 supplies the message data stored in the ROM 62 to the host computer 3 to display it as a message image on the display of the host computer 3. As the message image, for example, the following message can be considered. "We have corrected a correctable burst error, but since the correction result is an error, we are re-reading the sector."

In step S167, reread of the sector is set. Then, the process proceeds to step S5. In this step S167, the CPU 60 of the controller 44
Is a read / write circuit 38 via an output terminal 73.
A request signal indicating re-reading of the sector.
Thereby, as described above, the data of the sector is read out again from the optical disc 4.

[Modification] In the above process, the re-reading of the sector may be performed only in step S10, and if an error occurs in another step, the re-reading of the sector may not be performed. For example, step S5
If the error cannot be recovered by rereading the sector in step 4, step S104, or step S167, there is a possibility that a failure of the optical disk drive or a considerable burst error may occur, and the processing loops. This is because there is a possibility that 4 cannot be taken out. If an error occurs even after re-reading the sector three times, the optical disk drive tells the host computer 3 "A large unrecoverable burst error has occurred or the optical disk drive may have failed, so the optical disk is forcibly ejected. It is also possible to forcibly eject the optical disc 4 after supplying a message such as "Yes".

As described above, in this example, the data can be recovered even if a burst error which has been uncorrectable until now occurs.

[Other Embodiments]

FIG. 16 shows an example of the internal structure of the level detection circuit required when detecting the length and position of the burst error by detecting the RF level instead of the parity as the second ECC used in the first embodiment. It is a block diagram which shows.

The level detection circuit 200 shown by the broken line in FIG.
As an example of the internal configuration of the above, the configuration shown in FIG.

In the figure, 201 is an input terminal to which the RF signal before the clamp processing from the selector / clamp circuit 33 shown in FIG. 2 is applied, and 202 is the data clock from the data system clock generation circuit 35. Input terminal supplied. 203 is an averaging circuit, which is an input terminal 20
The RF signal supplied via 1 is smoothed in accordance with the timing of the data clock supplied via the input terminal 202 to obtain a DC voltage signal. The DC voltage signal from the averaging circuit 203 is supplied to the comparator 204 and compared with the reference voltage from the reference power source 205 of the comparator 204. In the case of the sample servo method, for example, the reference voltage from the reference power source is obtained in advance as a representative level when the RF level is lowered due to a tracking deviation caused by the lack of wobble pits formed by 1 byte per 20 bytes of data. Since it is easy to keep it, the level is set higher than that level and smaller than the RF level in the state where there is no tracking error.

This comparator 204 has a reference power source 205.
When the DC voltage signal from the averaging circuit 203 is smaller than the reference voltage from, the signal "1" indicating an error is output. This output is supplied to the delay circuit 206. In this delay circuit 206, the output from the comparator 204 is delayed by the processing time of the main line signal so that it can be supplied to the detection system when detecting an error in the reproduced data.

FIG. 17 is a block diagram showing a configuration example of a controller used when a burst error is detected by detecting an RF level instead of the second ECC.
The second embodiment has the same configuration except that the internal configuration of the controller 44 shown in FIG. 3 is different and that the level detection circuit 200 is added to the drive controller 2 shown in FIG. , Only the internal configuration example of the controller is shown. 17, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 17, reference numeral 65 is an input / output terminal connected to the read / write circuit 38 shown in FIG. 2, and this input / output terminal 65 is a movable contact 66 of the switch 66.
connected to c. One fixed contact a of this switch 66
Is connected to the input terminal of the decoder 300, and the switch 66
The other fixed contact b is connected to the output terminal of the encoder 301.

The data output terminal of the decoder 300 is connected to one fixed contact a of the switch 69, the input terminal of the encoder 301 is connected to the other fixed contact b of the switch 69, and the movable contact of this switch 69 is connected. c is connected to the input / output terminal of the buffer 70. Also, buffer 7
The input / output terminal of 0 is connected to the input / output terminal of the interface circuit 71, and the input / output terminal of the interface circuit 71 is connected to the input / output terminal of the host computer 3 shown in FIG. 1 through the input / output terminal io1.

Here, the decoder 300 has the switch 66.
Error detection and error correction processing is performed on the reproduced data supplied via the input / output port, and when a request is made from the CPU 60 via the input / output port, based on the detection result from the burst detection circuit 302 described later. Error correction processing. As shown in FIG. 17, this decoder 300 has
For example, a RAM 300a with a capacity of 2 sectors and this RA
By controlling the reproduction data written in the M300a, error correction processing by LDC, error check by CRC, and parity of LDC based on the detection result from the burst detection circuit 302 when a burst error occurs in which these corrections and checks cannot be performed. RAM for error correction
The controller 300b is used.

As shown in FIG. 17, the encoder 301 includes a RAM 301a having a storage capacity of 2 sectors,
By controlling the input data written in the RAM 301a, the parity is generated as the first ECC, and the CR is generated.
The C parity is generated and these parities are added.

The encoder 301 converts the data to be recorded, which is transferred from the host computer 3, temporarily written in the buffer 70 via the interface circuit 71, read from the buffer 70 and then supplied via the switch 69. On the other hand, parity for error detection, parity as CRC for error correction, and parity as first ECC are added respectively.

In the optical disc drive shown in FIG. 1, the check parity and the error correction parity can be recorded in the writable area of the magneto-optical disc, the write-once disc and the partial disc. Both the encoder side and the decoder side are involved, but in the case of the read-only area of the read-only or partial disc, the above-mentioned parity etc. and data will be recorded at the time of manufacturing the disc, so the encoder side is not Instead, only the decoder side will be involved.

The burst detection circuit 302 has an input terminal 30.
When the burst error occurs, the magnitude and position of the burst error are detected by the detection result from the level detection circuit 200 shown in FIG. 16 via 3 and the detection result is supplied to the decoder 300 via the input / output port 64.

Only the main operation during reproduction will be described below. When reproducing the data recorded on the optical disk 4, the CPU 60 supplies a switching control signal to the switches 66 and 69 via the input / output port 64, and the movable contacts c of the switches 66 and 69 are fixed to the fixed contact a. Connect to. As a result, the reproduction data read from the optical disk 4 and supplied through the read / write circuit 38, the input / output terminal 65 and the switch 66 is supplied to the decoder 300, and error detection and error correction processing is performed in this decoder 300. After being applied, it is supplied as reproduction data to the host computer 3 shown in FIG. 1 through the switch 69, the buffer 70, the interface circuit 71 and the input / output terminal io1.

At this time, the decoder 67 has the RAM 67a.
Of the data of two sectors stored in the above, the error correction by the parity as the first ECC, the error check by the parity of the CRC, and the error correction and check by the parity of the CRC become impossible for the data of one sector. In this case, the size and the position of the burst error are recognized based on the detection result from the burst detection circuit 302, and thereafter, the error correction by the parity as the first ECC and the error check by the parity of the CRC are performed again and the sector of the sector is checked. When the data is obtained and the reproduction process is completed, the data of the sector is output, and a signal indicating that is supplied to the CPU 60 via the input / output port 64 and the bus 61. As a result, the CPU 60 is
The read / write circuit 38 shown in FIG. 2 is instructed to reproduce the next sector, whereby all the data of the sector is supplied to the buffer 70, and then the next sector read from the optical disc 4 is read. Playback data is RA
It is supplied to M67a.

FIG. 18 is a flow chart for explaining the operation at the time of reproduction when the burst error is detected by detecting the RF level instead of the second ECC.
Note that this FIG. 18 corresponds to FIG. 12 of the first embodiment, and the same processing is performed for FIGS. 13 to 15 of the first embodiment. Attachment is omitted. Further, in FIG. 18, parts corresponding to those in FIG. 12 are designated by the same reference numerals, and detailed description thereof will be omitted.

If correction becomes impossible in step S4, the process proceeds to step S200, and this step S20
At 0, the burst error length and position are obtained from the RF level detection result. Then, the process proceeds to step S201.
In this step S200, the burst detection circuit 302 shown in FIG. 17 obtains the number, length and position of burst errors in one sector based on the detection result from the level detection circuit 200 shown in FIG.

In step S201, it is determined whether the correction is impossible. If "YES", the process proceeds to step S8 and "N" is entered.
If “O”, the process proceeds to step S202. In step S201, when the number of burst errors in one sector is 4 or more, it is determined that the error cannot be corrected.

In step S202, it is determined whether or not the number is 3, and if "YES", the process proceeds to step S203,
If “NO”, the process proceeds to a subroutine S100 as step S100. In step S202, it is determined whether or not the number of burst errors is "3". This "3" is substantially the same as the number "3" of error flags in the first embodiment.

In step S203, it is determined whether or not three consecutive lines are present. If "YES", the process proceeds to the subroutine SUB3 as step S150, and if "NO", the process proceeds to the subroutine SUB1 as step S50. In this step S203, it is determined whether or not there are three consecutive burst errors.

Each of the following subroutines SUB1 and SUB2
And the processing in SUB3 is the same as in the first embodiment. By not using the second ECC, the error correction processing speed can be improved. Further, in this second embodiment, when the parities P1 to P40 as the second ECC are recorded as in the case of the first embodiment and are used at the time of reproduction, the detection and correction 8 bytes by the LDC are up to 16 bytes. It is also possible to obtain a great effect that the bite can be increased.

[0171]

According to the present invention, it is possible to recover even large continuous errors that cannot be corrected with the minimum inter-code distance of the data for the first error processing, and this makes it possible to perform simple processing. Even if a burst error that was originally uncorrectable occurs, the data can be restored, the error correction capability can be further improved, and the data can be reliably reproduced.

Furthermore, according to the present invention, it is possible to improve the error correction capability when an error occurs over a plurality of units.

Further, according to the present invention, in the case where the error occurrence state is an error extending over a plurality of blocks, the data of at least one block in the substantially center of the plurality of blocks extending over the error and the disappearance thereof. Since it is assumed that the data in the block adjacent to at least one block that has been considered to have disappeared and the error correction processing is performed by the data for the first error processing described above, when an error across multiple blocks occurs. It is possible to further improve the error correction capability, to efficiently correct the error and perform good reproduction, and to prevent the recording capacity of the recording medium from decreasing.

[0174]

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of an optical disk drive of the present invention.

FIG. 2 is a configuration diagram showing a drive controller shown in FIG.

3 is a configuration diagram showing a controller of the optical disc drive shown in FIG. 1. FIG.

FIG. 4 is an explanatory diagram showing an example of a format of an optical disc of the present invention.

5 is an explanatory diagram showing an example of the size of each area of the optical disc shown in FIG. 4 and the frequency of a data clock used in each area.

FIG. 6 is an explanatory diagram showing an example of a sector format of the optical disc of the present invention.

FIG. 7 is an explanatory diagram showing an example of a sector format of the optical disc of the present invention.

FIG. 8 is an explanatory diagram showing an example of a sector format of the optical disc of the present invention.

FIG. 9 is a diagram for explaining the addition of parity as the second ECC according to the 7th row-8th row-7th row pattern of the optical disc of the present invention.

FIG. 10 is a diagram for explaining a coping method when one burst error occurs in a sector.

FIG. 11 is a diagram for explaining a coping method when a plurality of burst errors occur in a sector.

FIG. 12 is a flowchart for explaining a data processing operation at the time of reproduction of the optical disc drive of the present invention.

FIG. 13 is a flowchart for explaining a data processing operation at the time of reproduction of the optical disc drive of the present invention.

FIG. 14 is a flowchart for explaining a data processing operation during reproduction of the optical disc drive of the present invention.

FIG. 15 is a flowchart for explaining a data processing operation during reproduction of the optical disc drive of the present invention.

FIG. 16 is a configuration diagram showing a configuration of a level detection circuit according to another embodiment of the present invention.

FIG. 17 is a diagram showing an internal configuration of a controller according to another embodiment of the present invention.

FIG. 18 is a flowchart for explaining the operation of another embodiment of the present invention.

[Explanation of symbols]

 4 optical disk 60 CPU 61 bus 62 ROM 63 RAM 64 input / output port 67, 300 decoder 68, 301 encoder 200 level detection circuit 302 burst detection circuit

Claims (16)

[Claims] 1. (a) First error processing data is generated for each of a series of data of a predetermined amount, and the first series of data is divided into a plurality of blocks obtained by dividing each of the series of data of the predetermined amount. 2) error-processing data is generated, and (b) data of each recording unit is generated by the series of data consisting of the predetermined amount, the first error-processing data, and the second error-processing data, (C) recording the data of each recording unit on a recording medium, (d) reproducing the data of each recording unit from the recording medium, and (e) the predetermined amount of the reproduced data of each recording unit. Error correction is performed for each of the recording units by the first error processing data, and (f) when the error correction cannot be performed in the step (e), the second error processing is performed. For error handling At least an error is detected by the data in the series of data of the predetermined amount for each block, and (g) when an error is detected in N consecutive N (N is a positive integer) blocks, All data of at least one block which does not become an end of the continuous N blocks is regarded as lost data, and is converted into a series of data of the predetermined amount of the recording unit by the first error processing data. A data recording / reproducing method comprising the step of obtaining reproduced data by performing error correction on the other hand. 2. In the step (a), the second
2. The data recording / reproducing method according to claim 1, wherein the error processing data is composed of a plurality of parities in a direction according to a reproduction order from the recording medium with respect to a series of data having the predetermined amount. 3. In the step (g), all data of at least one block out of the N consecutive blocks and data of a part of a block adjacent to this block are regarded as lost data. 2. The data recording / reproducing method according to claim 1, wherein the first error processing data is used to perform error correction on a series of data of a predetermined amount of the recording unit. 4. In the step (g), when an error is detected in two consecutive blocks,
One block of data that spans the above two consecutive blocks is regarded as lost data, and the first error processing data is used to perform error correction on a series of data consisting of the predetermined amount of the recording unit. The data recording / reproducing method according to claim 1, wherein when the error correction is impossible, the position of the data for one block regarded as the lost data is shifted and the error is corrected again by the first error processing data. 5. (a) First error processing data is generated for each of a series of data of a predetermined amount, and a first block is obtained for each of a plurality of blocks obtained by dividing the series of data of the predetermined amount. (2) generating transmission data of each unit from the series of data consisting of the predetermined amount, the first error processing data, and the second error processing data, (C) The transmission data of each unit is transmitted, and (d) the transmitted transmission data of each unit is error-corrected by the first error processing data for each recording unit, (f) ) When the error cannot be corrected in the step (d), at least an error is detected in the transmission data of each block by the second error processing data, and (g) consecutive N (N) Is 3 When an error is detected in (upper integer) blocks, all the data of at least one block which is not the end of the continuous N blocks is regarded as lost data, and the first error processing is performed. A data transmission method comprising the step of performing error correction on the above-mentioned predetermined amount of data of the transmission terminal by using the data for use. 6. In the step (a), the second
6. The data transmission method according to claim 5, wherein the error processing data is composed of a plurality of parities in a direction according to a reproduction order from the recording medium for a series of data of the predetermined amount. 7. In the step (g), all data of at least one block which is not an end of the N consecutive blocks and some data of a block adjacent to this block are regarded as lost data. 6. The data transmission method according to claim 5, wherein the first error processing data is used to perform error correction on a series of data consisting of the predetermined amount of the recording unit. 8. In the step (g), when an error is detected in two consecutive blocks,
One block of data that spans the above two consecutive blocks is regarded as lost data, and the first error processing data is used to perform error correction on a series of data consisting of the predetermined amount of the recording unit. The data transmission method according to claim 5, wherein when the error cannot be corrected, the position of one block regarded as the lost data is shifted and the error is corrected again by the first error processing data. 9. Regarding a series of data consisting of a predetermined amount,
Error processing data generating means for generating the first error processing data respectively, and generating the second error processing data for each of a plurality of blocks obtained by dividing the series of data of the predetermined amount. By the series of data consisting of the predetermined amount, the first error processing data and the second error processing data,
Recording unit data generating means for generating data of each recording unit, recording / reproducing means for recording the data of each recording unit on a recording medium and reproducing the data of each recording unit from the recording medium, and the recording / reproducing means. For a series of data consisting of the predetermined amount of the data of each recording unit reproduced by
When the error is corrected by the first error processing data for each recording unit and the error cannot be corrected,
By the second error processing data, at least error detection is performed on a series of data consisting of the predetermined amount for each block, and an error is detected in N consecutive N (N is a positive integer) blocks. At this time, all the data of at least one block that is not an end of the continuous N blocks is regarded as lost data, and a series of the predetermined amount of the recording unit is set by the first error processing data. A data recording / reproducing apparatus comprising: an error correcting unit that performs error correction by performing error correction on the data. 10. The error processing data generating means comprises:
10. The data recording device according to claim 9, wherein, as the second error processing data, a plurality of parities in a direction according to a reproduction order from the recording medium are generated for a series of data of the predetermined amount. 11. The error correction means includes the consecutive N
All the data of at least one block that is not the end of the blocks and the data of a part of the blocks adjacent to this block are regarded as lost data, and the first error processing data causes the above-mentioned recording unit to be recorded. The data recording / reproducing apparatus according to claim 9, wherein error correction is performed on a series of data of a predetermined amount. 12. The error correction means, when an error is detected in two consecutive blocks,
One block of data that spans two consecutive blocks is regarded as lost data, and the first error processing data is used to perform error correction on a series of data consisting of the above-mentioned amount of the recording unit. 10. The data recording / reproducing apparatus according to claim 9, wherein when the error cannot be corrected, the position of one block of data regarded as lost data is shifted and error correction is performed again by the first error processing data. 13. A second error is generated for each of a plurality of blocks obtained by generating first error processing data for a series of data of a predetermined amount and dividing the series of data of the predetermined amount, respectively. Error processing data generating means for generating processing data, a series of data consisting of the predetermined amount, the first error processing data and the second error processing data,
Transmission data generation means for generating transmission data for each unit, transmission means for transmitting transmission data for each unit, and the first error processing for each recording unit for the transmitted transmission data for each unit. Error correction is performed by using the second data, and when the error correction cannot be performed, at least error detection is performed on the transmission data of each block by the second error processing data, and consecutive N
When an error is detected in (N is an integer of 3 or more) blocks, all data of at least one block that is not the end of the N consecutive blocks is regarded as lost data and the A data transmission device comprising: an error correction means for performing error correction on a series of data of a predetermined amount in the transmission unit by the error processing data of 1. 14. The error processing data generating means comprises:
14. The data transmission device according to claim 13, wherein, as the second error processing data, a plurality of parities in a direction according to a reproduction order from the recording medium with respect to a series of data of the predetermined amount are generated. 15. The error correction means includes the consecutive N
All the data of at least one block which is not the end of each block and the data of a part of the blocks adjacent to this block are regarded as lost data, and the above-mentioned portion of the recording unit is determined by the first error processing data. The data transmission device according to claim 13, wherein error correction is performed on a series of data consisting of a fixed amount. 16. The error correction means, when an error is detected in two consecutive blocks, the two consecutive blocks are detected.
One block of data spanning each block is regarded as lost data, and the first error processing data is used to perform error correction on a series of data consisting of the above-mentioned predetermined amount of the recording unit, and error correction is impossible. 14. The data transmission device according to claim 13, wherein the position of the data for one block regarded as the lost data is shifted, and the error is corrected again by the first error processing data.