JPH08195090A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to an electrically rewritable non-volatile memory, and in a flash memory in which memory cells are divided into blocks, even if a row decoder is shared between the blocks, the configuration is simple and high. The purpose is to ensure performance. [Structure] A plurality of word lines WL and a plurality of bit lines BL
And a plurality of cells Ce and a row decoder 1, and each of the plurality of cells Ce is divided into a plurality of blocks in a group of cells connected to the same word line. A plurality of power source selecting means 3-1, 3-2, ..., 3-m for outputting the first voltage or the second voltage according to a selection signal provided for each, and arranged for each block to output an access signal. , 2-m for applying a voltage from the power source selecting means to the word line of the selected block, and the row decoder also applies the voltage from the power source selecting means to the word line to be accessed. To configure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable non-volatile semiconductor memory device called a flash memory (hereinafter simply referred to as a non-volatile memory), and more particularly to a flash memory which can be rewritten for each block.

[0002]

2. Description of the Related Art There is an E ² PROM as an electrically rewritable non-volatile memory, and among them, there is a flash memory as a batch erasable or partial batch erasable memory, which has recently attracted attention because it can be highly integrated. ing. The present invention is applied to this flash memory.

FIG. 5 is a diagram showing an example of the structure of a memory cell of a flash memory. As shown, the gates are a control gate (CG) 201 and a floating gate (F).
G) It has a two-layer structure of 202,
1, when a predetermined voltage is applied to the drain (D) 204 and the source (S) 203, the drain 204 and the source 20
Storage is performed by utilizing the fact that the current flowing between 3 changes depending on whether or not charges are injected into the floating gate 202. In a flash memory, a logical value “H” is generally associated with an erased state, that is, a state where no charges are injected into the floating gate 202, and a logical value “L” is associated with a state where charges are injected into the floating gate 202. Injecting charges into the floating gate 202 is called writing. As will be described later, in the flash memory, the plurality of word lines WL and the plurality of bit lines BL are arranged vertically.
The control gate 201 of each memory cell is the word line W
The drain 204 is connected to the bit line BL.

A method of writing, reading and erasing information in the memory cell having the structure shown in FIG. 5 will be described. FIG. 6 is a diagram showing an example of voltage conditions applied to each unit when writing, reading and erasing information in the memory cell of the flash memory. At the time of writing, a high voltage VPP (about 12V) is applied to the control gate (CG), about 6V is applied to the drain (D), and 0V is applied to the source (S).
At this time, some of the electrons flowing in the memory cell are accelerated by a high electric field in the vicinity of the drain (D) to acquire energy, and are injected into the floating gate (FG) over the energy barrier of the gate insulating film. Since the floating gate (FG) is electrically insulated from other circuit parts, it is possible to store charges semipermanently.

At the time of reading, the control gate (CG)
Power supply voltage VCC (about 5V) and drain (D) about 1
V and 0 V are applied to the source (S). The threshold value of the cell transistor changes depending on the presence or absence of charges stored in the floating gate (FG), and the current flowing through the selected memory cell changes. Information is read out by detecting and amplifying this current.

At the time of erasing, the control gate (CG)
Is applied to the source (S) and a high voltage VPP (about 12 V) is applied to the source (S). As a result, charges are extracted from the floating gate (FG) to the source (S). FIG. 7 is a diagram showing a configuration of a conventional general flash memory. In the drawings, the same functional portions will be denoted by the same reference numerals including the description of the prior art and the description of the embodiments of the present invention.

In FIG. 7, reference numeral WL is a word line, BL is a bit line arranged vertically to the word line WL, SL is a source line provided for each row, and MSL is each. A main source line commonly connecting the source lines SL, Ce is a memory cell arranged corresponding to the intersection of the word line WL and the bit line BL, and 1 is a row decoder for selectively controlling the word line. Yes, 4 is a source line control unit, 5 is a column decoder, 6 is a column gate composed of a transistor Y driven by a bit line selection signal from the column decoder 5, and 7 is an address signal input. 8 is a sense amplifier / write amplifier, 9 is a data input / output buffer, and 10 is a control unit for controlling the entire memory.

As shown in FIG. 7, the memory cell Ce is arranged corresponding to the intersection of the word line WL and the bit line BL, the control gate of each memory cell Ce is connected to the word line WL, and the drain is the bit line BL. , And the source is connected to the source line SL. The row decoder 1 decodes the row address signal of the address signals and selectively applies the row address signal to the word lines, and the column decoder 14 decodes the column address signal of the address signals and outputs the bit line selection signal. Output and transistor Y
Are selectively conducted. Transistor Y is bit line BL
And the sense amplifier / write amplifier 8 are controlled.
In this way, the memory cells connected to the selected word line and bit line are accessed at the time of reading and writing. Therefore, at the time of reading, VCC is applied to the selected word line, 0V is applied to the other word lines, and the selected bit line is connected to the sense amplifier / write amplifier 8 and about 1V is applied thereto. Bit lines other than the above are open. At this time, the source line SL
Are all set to 0V by the source line control unit 4. Also,
At the time of writing, VPP is applied to the selected word line and 0V is applied to the other word lines, and the selected bit line is connected to the sense amplifier / write amplifier 8 and the voltage of about 6
V is applied and other bit lines are open
State. Also at this time, the source line SL is set to 0V by the source line control unit 4.

Erasing is performed by applying a high voltage from the source line control unit 4 to the source line commonly connected to each memory cell and applying 0V corresponding to a non-selection signal to each word line WL. Therefore, the memory cells commonly connected to the source line are collectively erased. The flash memory has a large storage capacity. When increasing the capacity, all the memory cells shown in FIG. 5 are connected to a common source line and all the memory cells are erased at once. There are various inconveniences such as the necessity of erasing and the inability to perform detailed management. Therefore, in a large capacity flash memory, memory cells are divided into a plurality of blocks so that each block can be erased.

FIG. 8 is a diagram showing a structure of a memory cell portion of a conventional flash memory in which a memory cell is divided into a plurality of blocks so that each block can be erased.
As shown in FIG. 8, the bit line is divided into a plurality of blocks (here, m blocks), and the memory cells are also divided into groups connected to the bit lines of each block. That is, the memory cells connected to the same word line WL are divided into a plurality of blocks. Source line control unit 4-for each block
1, ... 4-m are provided, and when erasing data of a certain block, the high voltage VPP is applied to the source line of the block by the source line control unit connected to the block. In this way, it becomes possible to erase in block units.

On the other hand, the flash memory guarantees the number of times rewriting can be performed. In the past, it was general to guarantee rewriting from 10,000 to 100,000 times, but in recent years, the guaranteed number of times of rewriting is further increased. Therefore, the structure of the memory cell is determined so that such specifications can be satisfied. Further, as a matter of course, in the flash memory, it is necessary that the data stored in a certain memory cell does not change due to the read and write operations to the other memory cell. To ensure this, the structure of the memory cell and the voltage application. The conditions are set. However, the flash memory has a structure in which a thin gate oxide film is provided so that charges can be injected into and extracted from the floating gate as shown in FIG. 5, but since the gate oxide film is thin, the writing shown in FIG. Even if a condition is not added, a slight amount of charge may be injected into the floating gate. During erase operation, a high voltage is applied only to the source line of the block to be erased, so there is no particular problem.
Since a voltage is applied as an access signal to a word line to which a memory cell to be accessed is connected during a write operation or a read operation, even if the memory cell is not accessed, the control gate of the memory cell connected to that word line A voltage will be applied to. Of course, the voltage shown in FIG. 6 is not applied to the bit line which is not accessed, but the condition shown in FIG. 6 is not realized. However, since a voltage is applied to the control gate of the memory cell, a small amount of charge is applied to the floating gate. It can happen to be injected. This is called gate disturb. The effect of gate disturb varies geometrically depending on the voltage applied to the control gate. As shown in FIG. 6, the voltages applied to the control gates during writing and reading differ greatly, so that a particular problem is a writing operation to another memory cell connected to the same word line. When writing to a memory cell, a high voltage VPP (about 12V) is applied to the word line connected to the memory cell, about 6V is applied to the bit line connected to the memory cell, and another word is written. 0V is applied to the line and the bit line. Therefore, 0V is applied to the drain of the unaccessed memory cell connected to the word line, but VP is applied to the control gate.
In this state, P is applied. The gate disturb at this time is a particular problem. This condition occurs when writing to another memory belonging to the same word line. In the case of the configuration not divided into the blocks shown in FIG. 7, if the number of memory cells connected to the same word line is n, the above condition occurs at most (n-1) times. The structure of the memory cell and the voltage application conditions are determined so that the stored data does not change even if such gate disturb occurs (n-1) times. In the following description, the gate disturb for a memory cell other than the accessed memory cell at the time of writing is simply referred to as a gate disturb, and other gate disturbs are ignored.

[0012]

On the other hand, in a flash memory having a structure divided into a plurality of blocks as shown in FIG. 8, erasing is performed for each block, but word lines for writing are used. High voltage VPP to
Is applied to all blocks in common. Therefore, when considering a memory cell of a certain block, there is a possibility that rewriting is performed by the guaranteed number of times of rewriting in another block, and the number of times of gate disturb due to writing to another memory cell increases dramatically. For example, if the number of memory cells connected to the same word line in a block is n, the number of blocks is m, and the guaranteed number of times of rewriting is f, the number of gate disturbs is (n-1) +
It becomes n * (m-1) * f. The guaranteed number of rewritings f is on the order of 10,000 to 1,000,000, and the number of gate disturbs becomes very large. Therefore, it can be seen that it is not easy to guarantee that the data stored under this condition is correctly retained. In order to make such a guarantee, it is necessary to make the structure of the memory cell and the voltage application conditions strict, which causes an increase in the area of the memory cell and an increase in the applied voltage due to the increase in the thickness of the gate oxide film, and There is a possibility that problems such as decrease in power consumption and increase in cost may occur.

In order to solve such a problem, it is considered that a row decoder is also provided for each block so that the high voltage applied to the word line at the time of writing does not affect other blocks. FIG. 9 is a diagram showing a configuration of a conventional flash memory in which a row decoder is provided for each block. The flash memory having such a configuration is disclosed in, for example, Japanese Patent Laid-Open Nos. 5-54682 and 6-103790.

The source line control unit is a simple circuit, and even if it is provided for each block, the increase in area does not pose a problem, but the row decoder is a circuit that requires a large and large area, and especially memory capacity. Is a circuit in which the area increases in proportion to the increase in the number of word lines. Therefore, as shown in FIG. 9, if a row decoder is provided for each block, the area occupied by the entire row decoder becomes very large, which is a problem in achieving high integration. Further, it is necessary to input a row address signal of about 8 bits to 10 bits to each row decoder, and when the row address signal is supplied to the row decoders arranged over the entire surface of the element, the area required for wiring is large. There is also the problem of becoming.

The present invention has been made in view of the above problems, and in a flash memory in which memory cells are divided into blocks, high performance can be guaranteed with a simple configuration even if a row decoder is shared between the blocks. The purpose is to More specifically, it is an object of the present invention to realize a flash memory with a small area in which stored data is not rewritten even if a large number of times of rewriting is guaranteed.

[0016]

FIG. 1 is a principle block diagram of a nonvolatile semiconductor memory device of the present invention. In FIG. 1, reference numeral WL is a plurality of word lines, BL is a plurality of bit lines arranged perpendicularly to the word lines WL, and Ce is arranged corresponding to the intersections of the word lines WL and the bit lines BL. A plurality of cells, 1 denotes a row decoder that outputs an access signal to any of the word lines according to the position of the cell to be accessed. The plurality of cells Ce are divided into a plurality of blocks so that a cell group connected to the same word line is divided into a plurality of blocks. In addition to such a conventional element, the nonvolatile semiconductor memory device of the present invention is provided for each block in order to achieve the above-mentioned object, and outputs a first voltage or a second voltage according to a selection signal. , 3-m and the power source selecting means 3-1, 3-2, ... Are arranged so as to divide each word line between blocks, and receive the first voltage or the second voltage output from the power source selecting means. , When the access signal is output to the word line, the block buffers 2-2, ..., 2-m for applying the first voltage or the second voltage output from the power source selection means to the word line of the block, The row decoder 1 receives the first voltage or the second voltage output from the power supply selection means and outputs the first voltage output from the power supply selection means as an access signal to one of the word lines depending on the position of the cell to be accessed. Voltage or second voltage It applied, characterized in that.

Further, the power source selecting means 3-1, 3-2, ...
3-m outputs the second voltage when reading the data stored in the cell, and when writing the data to the cell, only the power supply selection means corresponding to the block to which the data is written outputs the first voltage. , The other power source selecting means outputs the second voltage.

[0018]

In the nonvolatile semiconductor memory device of the present invention, the power source selecting means 3-1, 3-2, ..., 3-m are provided for each block, and the first voltage or the second voltage is set in accordance with the selection signal. Output. For example, if the selection signal is a signal for selecting a block to be accessed at the time of writing, only the power supply selecting means corresponding to the written block outputs the first voltage, and the other power supply selecting means outputs the second voltage. Will be output. Any of the row decoder 1 or the block buffers 2-2, ..., 2-m corresponds to each block. The row decoder 1 outputs an access signal according to the voltage output from the corresponding power supply selection means. That is, when the memory cells of the block assigned to the row decoder 1 are accessed, the access signal of the first voltage is output, and when the memory cells of the other blocks are accessed, the access signal of the second voltage is output. To do. The block buffers 2-2, ..., 2-m apply the voltage output from the corresponding power supply selecting means to the word line of the allocated block to the word line to which the access signal is applied. Therefore, when the memory cell of the allocated block is accessed, the first voltage is output from the corresponding power supply selecting means, so that the first voltage is applied to the word line to which the access signal in the block is applied. When a memory cell other than the assigned block is accessed, the second voltage is output from the corresponding power supply selecting means, so that the second voltage is applied to the word line to which the access signal in the block is applied. Is applied. In other words, the word line is separated for each block, and of the word lines to which the access signal is applied, only the word line of the block in which the memory cell to be accessed has the high voltage that needs to be applied at the time of writing is applied. Therefore, only a low voltage is applied to the word lines of the other blocks. As a result, a write operation in one block does not cause gate disturb in another block.

Power source selecting means 3-1, 3-2, ..., 3-m
Can be realized by a simple circuit since it simply selects the first voltage or the second voltage according to the selection signal. The block buffers 2-2, ..., 2-m only receive the access signal of the block in the preceding stage and perform voltage conversion for outputting the voltage output from the corresponding power supply selecting means, and are also simple circuits. realizable. Therefore, the circuit of the nonvolatile semiconductor memory device of the present invention is simpler and can be realized in a smaller area than the conventional circuit of FIG. Moreover, the write operation to a certain block is similar to the circuit of FIG. 9 in that the gate disturb does not occur in another block, and it is easy to guarantee the number of rewritable times.

[0020]

FIG. 2 is a diagram showing the overall configuration of a flash memory according to an embodiment of the present invention. In FIG. 2, reference numeral WL
Is a plurality of word lines, BL is a plurality of bit lines arranged perpendicularly to the word lines WL, SL is a source line for each row, and MSL is a main source line connecting the source lines for each block. , Ce denote a plurality of memory cells arranged corresponding to the intersections of the word lines WL and the bit lines BL. As shown, the memory cell is divided into blocks each including a group of a plurality of bit lines as a group. That is, the memory cells connected to the same word line are divided into a plurality of blocks. Here, it is divided into m blocks.

Reference numeral 1 is a row decoder, 2-m is a block buffer arranged between each block except the first block and the preceding block, 3-1, ..., 3-m are provided for each block. The first voltage or the second voltage according to the selection signal.
, 4-m are source line control units connected to the main source line MSL of each block, 5 is a column decoder, 6 is a column gate, and 7 is a column gate.
Is an address buffer, 8 is a sense amplifier / write amplifier, 9 is a data input / output buffer, and 10 is a controller. The parts other than the row decoder 1, the block buffer 2-m, and the power supply selection units 3-1, ..., 3-m are the same as those of the conventional flash memory, and the description thereof is omitted here.

The memory cell is divided into blocks for each set of a plurality of bit lines, and the selection of the block is substantially the selection of the set of bit lines. Therefore, since the block selection signal is generated in the middle of the decoding signal in the column decoder 5, the block selection signal is generated.
..., supply to 3-m. FIG. 3 is a diagram showing a circuit configuration of each power source selection unit.

As shown in FIG. 3, the power supply selection circuit is supplied with a block selection signal and a signal PRG. The block selection signal is a signal that becomes VCC (“high (H)”) when there is a memory cell that accesses the block, and becomes a ground level (“low (L)”) when there is no memory cell to access the block. is there. Further, PRG is a signal which becomes "H" during the write operation and becomes "L" during the other operations. Therefore, when the memory cell to be written is in that block, both the block selection signal and PRG become "H". As a result, the p-channel transistors TP2 and TP3 are turned off, the n-channel transistors TN3 and TN4 are turned on, and the nodes a and b are turned on.
Becomes "L". Since the node b is "L", the p-channel transistor TP5 is turned on, the p-channel transistor TP4 is turned off, the n-channel transistor TN7 is turned off, and the node c is "H". Since the node c is "H", the depletion transistor TD2 is turned on, and VPPn is the high voltage V
Become PP. At this time, since the node b is "L", the depletion transistor TD3 is off.

PRG is "L" except for the write operation.
Is. When the memory cell of the block is not accessed, the block selection signal is "L". When either the block selection signal or PRG is "L", T
At least one of P2 and TP3 is turned on, and TN
Since at least one of 3 and TN4 is turned off, the nodes a and b become "H". Therefore, node c is "L"
Then, TD2 is turned off and TD3 is turned on at the same time, so that VPPn becomes the normal voltage VCC.

As described above, the power source selecting section 3-1,
..., 3-m are arranged for each block, and the high voltage V is set only when the memory cells in the block are accessed at the time of writing.
It outputs PP, and otherwise outputs the normal voltage VCC. FIG. 4 is a diagram showing a circuit configuration of the block buffer. As shown in FIG. 4, in this circuit, the depletion transistor TD1 and the n-channel transistor TN are used.
A buffer circuit 21 composed of 1 and TN2 and a p-channel transistor TP1 is provided for each word line. VPPn is supplied to the buffer circuit 21 from the power supply selection unit. VCC or VP on the word line of the previous block
When the access signal of P is applied, TN1 is turned on and the node d becomes "L", so that TP1 is turned on and TN2 is turned off, and VPPn is supplied to the word line of the block. It If the access signal is not applied to the word line of the previous block and is "L", TN1
Turns off and node d goes to "H", so TP
1 is turned off, TN2 is turned on, and the word line of the block becomes "L". As described above, VPPn is the high voltage VPP only when the memory cells in the block are accessed at the time of writing, and is the normal voltage VCC at other times. Therefore, when writing is performed to the memory cells in the block, the high voltage VPP is applied only to the word line to be accessed, and the voltage close to zero V is applied to the other word lines. At the time of writing, when the memory cell in the block is not written and at the time of reading, the normal voltage VC is applied only to the word line to be accessed.
C is applied, and a voltage close to zero V is applied to the other word lines. In this way, the access signal is sequentially sent to the subsequent stage, and the high voltage is applied at the time of writing only in the accessed block.

The row decoder 1 is assigned to the first block. The conventional row decoder circuit can be applied as it is to the portion for decoding the row address signal. The conventional row decoder circuit has a driver for driving a signal for accessing each word line obtained by decoding. If a circuit similar to that shown in FIG. 4 is used for this driver, the memory cell of the first block is The high voltage VPP is output to the word lines that are accessed only when the write operation is performed, the voltage close to zero V is output to the other word lines, and the read operation or the memory cell write in the blocks other than the first block is performed. When performed, the normal voltage VCC is output to the word line to be accessed, and the voltage close to zero V is output to the other word lines.

As shown in FIGS. 3 and 4, the power supply selection unit and the block buffer are both simple circuits. Although it is necessary to provide the buffer circuits 21 for the number of word lines in the block buffer, the circuit is much simpler and the area can be reduced as compared with the case where the row decoder is provided for each block shown in FIG. Moreover, since the gate disturb at the time of writing does not affect other blocks as in the circuit of FIG. 9, if the number of memory cells connected to one word line in the block is n, that is, in the block. Assuming that the number of bit lines is n, the number of times gate disturb occurs due to writing to another memory cell connected to the same word line is (n-1) as in the circuit of FIG. Therefore, it is easy to guarantee a large number of rewritable times.

Although the embodiment of the present invention has been described above by taking the flash memory having the 1-bit configuration as an example, the same applies to the flash memory having the multi-bit configuration.

[0029]

As described above, according to the present invention,
In a non-volatile semiconductor memory device composed of a plurality of blocks and having a common row decoder, the influence on the stored data of other memory cells connected to the same word line when writing to the memory cell is performed in the same block. Since it is possible to prevent the memory cells of other blocks from being affected, it is possible to guarantee a large number of rewritable times with a simple circuit. Therefore, the reliability of the nonvolatile semiconductor memory device can be improved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram showing a configuration of a flash memory of the present invention.

FIG. 2 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 3 is a diagram illustrating a circuit configuration of a power supply selection circuit according to an embodiment.

FIG. 4 is a diagram showing a block buffer circuit according to an embodiment.

FIG. 5 is a diagram showing a structure of a memory cell of a flash memory.

FIG. 6 is a diagram showing conditions of reading, writing and erasing of the flash memory.

FIG. 7 is a diagram showing a circuit configuration of a conventional flash memory having one block as a whole.

FIG. 8 is a diagram showing a circuit configuration of a conventional flash memory divided into a plurality of blocks and capable of erasing each block.

FIG. 9 is a diagram showing a circuit configuration of a conventional flash memory in which a row decoder is provided for each block.

[Explanation of symbols]

 Reference numeral 1 ... Row decoder 2-2, ..., 2-m ... Block buffer 3-1, ..., 3-m ... Power source selection means 4-1, ..., 4-m ... Source line control unit 5 ... Column decoder 6 ... Column gate 7 ... Address buffer 8 ... Sense amplifier / write amplifier 9 ... Data input / output buffer 10 ... Control unit

Claims (3)

[Claims] 1. A plurality of word lines (WL), a plurality of bit lines (BL) arranged perpendicularly to the word lines, and a plurality of bit lines (BL) arranged corresponding to intersections of the word lines and the bit lines. A nonvolatile semiconductor memory device comprising a plurality of cells (Ce) and a row decoder (1) for outputting an access signal to any one of the word lines according to a position of a cell to be accessed. ) Is divided such that a group of cells connected to the same word line is divided into a plurality of blocks, and a plurality of power supplies that are provided for each block and that output a first voltage or a second voltage according to a selection signal. Selection means (3-1, 3)
-2, ..., 3-m) are arranged so as to separate each word line between blocks, and receive the first voltage or the second voltage output from the power source selection means to access the word line. When a signal is output, a block buffer (2-2, ..., 2-m) for applying the first voltage or the second voltage output from the power source selection means to the word line of the block is provided. The row decoder (1) receives the first voltage or the second voltage output from the power supply selecting means and selects the power supply as an access signal to any one of the word lines depending on a position of a cell to be accessed. A non-volatile semiconductor memory device, wherein the first voltage or the second voltage output from the means is applied. 2. The plurality of power source selecting means (3-1, 3-)
2, ..., 3-m) outputs the second voltage when reading the data stored in the cell, and when writing the data to the cell, only the power supply selecting means corresponding to the block to which the cell to which the data is written belongs. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device outputs a first voltage, and the other power source selection means outputs the second voltage. 3. The plurality of power source selecting means (3-1, 3-)
2, ..., 3-m), the selection signal is input to the plurality of bit lines (B
The non-volatile semiconductor memory device according to claim 2, wherein the non-volatile semiconductor memory device is output from a column decoder which outputs a signal for selecting any one of L).