JPH08195383A - Dry etching method and semiconductor device manufacturing method - Google Patents

Abstract

(57) [Abstract] [Purpose] The present invention relates to a dry etching method and a semiconductor device manufacturing method, in which a forward tapered mesa etching with an accurate etching depth or a vertical etching with an accurate etching depth is performed depending on the shape of the mask. It is easy to realize, does not cause disconnection at the step of the mesa, and allows the gate recess to have an accurate depth and be miniaturized. [Structure] Graded layer 15 and electrode contact layer 16
InGa after etching on the InGaAs layer such as
An insulating film made of, for example, SiON, which has a sidewall having the same angle as the sidewall of the As layer and acts as an etching mask, is formed, and the insulating film is used as a mask and C
A dry etching method using a mixed gas of H _4, H ₂ and CO ₂ as an etching gas is applied to obtain the InGaA
The s layer is etched to form a mesa having a forward tapered side wall or a gate recess 14 having a vertically raised side wall.
Form A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is suitable for arbitrarily dry etching an InGaAs layer so that the side wall has a forward taper or the side wall is substantially vertical, and the technique thereof is used. Utilizing high performance and fine high electron mobility transistor (high electron
The present invention relates to a dry etching method and a method for manufacturing a semiconductor device, which are suitable for manufacturing a semiconductor device including an availability transistor (HEMT).

At present, in the field of HEMT,
As part of high performance and miniaturization, various developments and researches for forming non-alloyed ohmic electrodes are being conducted. However, the underlying semiconductor layer is etched to have a preferable shape. Was difficult, but the present invention eliminates the difficulty.

[0003]

It is needless to say that in general, in order to form a non-alloyed ohmic electrode, the underlying semiconductor electrode contact layer should have high conductivity.

Since InGaAs has a Fermi level in the conduction band in the energy band, it has high conductivity and is therefore suitable as a semiconductor forming an electrode contact layer for forming a non-alloyed ohmic electrode. Is.

By the way, in the HEMT as well, by adopting the non-alloyed ohmic electrode, it is possible to prevent the crystallinity of good quality of the semiconductor from being destroyed by heat and to maintain high performance such as its high speed. In this case, of course, InGaAs is often used as the base of the non-alloyed ohmic electrode.

At present, the HEMT is being miniaturized for integration, and conventionally, the wet etching method has been applied to the processing of the InGaAs layer, but in terms of the microfabrication and controllability. It is considered to apply a good dry etching method.

The InGaAs layer is processed when the portion other than the element region is mesa-etched for element isolation and when it is etched to form a gate recess. By the way, InGaAs is GaAs
Unlike AlGaAs and AlGaAs, it cannot be made insulating by ion implantation of oxygen or the like.

FIG. 6 is a HEMT for explaining a conventional technique.
FIG. 4 is a perspective view showing a main part of the cutting. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an i-GaAs channel layer, and 3 is n.
-AlGaAs electron supply layer, 4 n-GaAs cap layer, 4A gate recess, 5 n ⁺ -InGaAs graded layer, 6 n ⁺ -InGaAs electrode contact layer, 7 insulating region, and 8 and 9 non- Alloyed ohmic electrodes and 10 respectively indicate gate electrodes. The ohmic electrode 8 may be a source electrode and the ohmic electrode 9 may be a drain electrode.

In the HEMT shown in FIG. 6, n ⁺ -
The InGaAs graded layer 5 is an underlying n-GaAs
The In composition is gradually increased from the GaAs of the cap layer 4 to make it graded, and the In composition on the n ^{+ layer is} uniform.
-InGaAs electrode contact layer 6 is reached.

For element isolation, wet etching is applied to perform mesa etching from the surface of the n ⁺ -InGaAs electrode contact layer 6 to the n-GaAs cap layer 4.

Further, in order to form the gate recess 4A,
Similarly to the above, by applying the wet etching method, n-AlGaA is penetrated from the surface of the n ⁺ -InGaAs electrode contact layer 6 through the n-GaAs cap layer 4.
s Etching to reach the electron supply layer 3 is performed.

[0012]

As described above, when the wet etching method is applied to the mesa etching, the side wall of the mesa becomes almost vertical,
Also, there is no controllability of the etching depth. Further, when the wet etching method is applied to the etching for forming the gate recess 4A, side etching occurs, so that the fine workability is poor and the etching depth is not controllable.

Therefore, when an ohmic electrode is formed, disconnection is likely to occur at the step portion of the mesa, for example, as indicated by an arrow on the ohmic electrode 9 in FIG. 6, and it is difficult to miniaturize the gate. The shape of the n-GaAs cap layer 4 is varied, and the FET characteristics such as the source resistance are varied, which is disadvantageous.

According to the present invention, both forward tapered mesa etching with an accurate etching depth and vertical etching with an accurate etching depth can be arbitrarily realized, and the ohmic electrode is formed at the step portion of the mesa. Disconnection does not occur, and the gate recess has an accurate depth and can be miniaturized, so that a highly miniaturized HEMT having high reliability and high performance can be obtained.

[0015]

In the present invention, InGaAs is dry-etched by using a mixed gas of CH ₄ , H ₂ and CO ₂ as an etching gas, and the side walls are forward tapered. In order to perform such etching, a sidewall having a forward tapered shape is used as an etching mask, and in order to perform etching so that the sidewall is vertical, the sidewall is almost vertical as an etching mask. The basis is to use things.

FIG. 1 is a perspective view of an essential part showing a HEMT in a process step for explaining the principle of the present invention.

In the figure, 11 is a semi-insulating GaAs substrate, 12 is an i-GaAs channel layer, and 13 is n ⁺ -Al.
GaAs electron supply layer, 14 n-GaAs cap layer,
14A is a gate recess, 15 is an n ⁺ -InGaAs graded layer, 15A is a GaAs etching stop layer formed in the graded layer 15, 16 is n ⁺ -InGa
As electrode contact layer, 17 is an insulating region, 18 and 1
Reference numeral 9 is a non-alloyed ohmic electrode, and 20 is a gate electrode. Also here, the ohmic electrode 18 may be the source electrode and the ohmic electrode 19 may be the drain electrode.

According to the present invention, as seen in FIG.
In the mesa etching process for element isolation, a slow mesa step is formed, and in the gate recess etching process, a gate recess 14A is formed in which the sidewall is raised and is substantially vertical. , And n-GaA
There is no variation in the shape of the s-cap layer 14.

FIG. 2 is an In diagram for explaining the case where the mesa etching suitable for the mesa etching and the etching of the gate recess is performed along the above-mentioned basic point.
It is a principal part cutting side view showing the etching shape of a GaAs layer.

In the figure, (A) is a side surface of a mesa having a forward tapered side wall, and (B) is a side surface of a mesa having a vertically raised side wall, and 21 is n ⁺ -InGaAs.
A layer, 22A is a mask film made of SiON having a forward tapered side surface, and 22B is a SiON having a vertically raised side surface.
Each of the mask films is shown.

As is apparent from FIG. 2, the mask film 22A
When the side surface has a forward taper and the etching gas is a mixed gas of CH ₄ , H ₂ , and CO ₂ , the underlying n ⁺ -InGaAs layer 21 inherits the side surface shape of the mask film 22A as it is. Is mesa-etched so as to have a forward taper.

When the mesa etching is performed, Si
The mask film 22A made of ON is hardly etched, and a mesa having a forward taper can be realized in the n ⁺ -InGaAs layer 21, and the pattern dimension is not reduced.

Further, like the mask film 22B, the side surface is vertically raised, and the etching gas is C
When a mixed gas of H ₄ , H ₂ and CO ₂ is used, the underlying n ⁺ -InGaAs layer 21 is mesa-etched so as to have the side wall shape of the mask film 22B as it is and to have a substantially vertical side wall. .

As is clear from the above-mentioned phenomenon, the mesa etching mechanism according to the present invention is not a normal mesa etching mechanism.
It is understood that the mechanism in etching is different. Next, this will be described by taking a case of forming a forward tapered mesa as an example.

FIG. 3 is a cross-sectional side view of a main part showing the etching shape of the InGaAs layer for explaining the mesa etching mechanism. The same symbols as those used in FIG. 2 represent the same parts or the same. It has meaning.

In the figure, (A) is a side surface of a main part for explaining a case where a normal mesa etching is performed, and (B).
Shows a side surface of a main part for explaining the case where the mesa etching according to the present invention is carried out, and 23 shows a reaction product generated by carrying out the etching.

Normal mesa etching is realized by the fact that the pattern of the mask film 22A is consumed and receded as the etching progresses, as shown in FIG.

In the mesa etching according to the present invention,
As shown in (B), the mask film 22A is not consumed and receded, the etching proceeds while the reaction product 23 is deposited on the side wall, and the surface covered with the reaction product 23 is not etched. The mesa of will be realized.

From the above, in the dry etching method and the semiconductor device manufacturing method according to the present invention, (1) the InGa after etching on the InGaAs layer is performed.
Forming an insulating film having sidewalls at the same angle as the sidewalls required for the As layer to act as an etching mask, and then using the insulating film as a mask and mixing CH _4, H ₂ and CO ₂ . Or a step of etching the InGaAs layer by applying a dry etching method using a gas as an etching gas, or

(2) An InGaAs layer (eg, graded layer 35, graded layer 37, electrode contact layer 38) which is a contact layer of an unalloyed ohmic electrode (eg, source electrode and drain electrode) on a substrate (eg, substrate 31). And the like, and a forward taper required for the InGaAs layer after etching is formed on the InGaAs layer. Has the same forward tapered side wall as the side wall of
Insulating film acting as a mask (eg SiON film 39)
And then etching a mixed gas of CH _4, H ₂ and CO _{2 using} the insulating film as a mask.
InG by applying dry etching method using gas
A step of etching from the surface of the aAs layer to the etching stop layer and then etching the etching stop layer and the underlying InGaAs layer by applying a wet etching method to complete a mesa having a forward tapered sidewall. And then InGa forming the mesa
Or a step of forming a pair of non-alloyed ohmic electrodes (for example, ohmic electrodes 42 and 43) in ohmic contact with at least the top surface of the As layer, or

(3) Non-alloyed ohmic electrodes (eg ohmic electrodes 42 and 43) on a substrate (eg substrate 31) with a carrier supply layer (eg electron supply layer 33) as a base.
InGaAs layer (eg, graded layer 35, graded layer 37, electrode contact layer 3)
8) and an etching stop layer (for example, an etching stop layer 36) made of GaAs are formed in the middle of the stacked body, and then the above-mentioned InGaAs layer after the etching is formed on the InGaAs layer. Forming an insulating film (for example, insulating film 41) having an opening (for example, opening 41B) of the substantially vertical vertical side wall and acting as an etching mask, and then masking the insulating film; And CH ₄ and H
A dry etching method using a mixed gas of ₂ and CO ₂ as an etching gas is applied to etch from the surface of the InGaAs layer to the etching stop layer to form a gate recess (eg, gate
Forming a recess 34A), and then etching the etching stop layer and the underlying InGaAs layer (for example, the graded layer 35) by applying a wet etching method to form the substantially vertical side wall. Further extending the gate recess having the substantially vertical raised sidewalls by applying a dry etching method to etch until reaching the carrier supply layer. Or a step of forming a gate electrode (for example, the gate electrode 44) in the gate recess by applying a lift-off method, or

(4) In the above (2) or (3),
InGa as a contact layer of non-alloyed ohmic electrode
The In composition in the As layer gradually increases from the substrate side to the surface side (for example, 0 → 0.5) and maintains a constant value (for example, 0.5) near the surface. .

[0033]

By adopting the above means, I for element isolation can be obtained.
When nGaAs mesa etching is performed, the side wall of the mesa becomes a forward taper shape, so even if the ohmic electrode is pulled out, no disconnection occurs at the step portion of the mesa, and the dry process for forming the mesa is performed. Since the etching is surely stopped at the etching stopper layer, and the remaining extremely thin layer is removed by wet etching after that, accurate control of the etching depth is easy.
Also, when etching is performed to form the gate recess, vertical side walls can be formed, which is effective for miniaturization. Also, in this case, the etching depth must be accurately controlled. You can For this reason, it is possible to easily manufacture a semiconductor device including a miniaturized HEMT that does not change in characteristics and can maintain high reliability and high performance.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 4 and 5 are side sectional views of the essential part of a HEMT in the process steps for explaining one embodiment of the present invention.
The following is a description with reference to these figures.

See FIG. 4A. 4- (1) Metalorganic chemical vapor deposition
chemical vapor deposition
n: MOCVD method is applied to form a channel layer 32, an electron supply layer 33, a cap layer 34, a graded layer 35, an etching stop layer 36, a graded layer 37 on the substrate 31.
The electrode contact layer 38 is grown.

The following is an example of the main data relating to each of the above-mentioned components. Substrate 31 Material: Semi-insulating GaAs channel layer 32 Material: i-GaAs Thickness: 2000 [Å]

Electron supply layer 33 Material: n ⁺ -AlGaAs Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 300 [Å] Cap layer 34 Material: n-GaAs Impurity concentration: 2 × 10 ¹⁸ [cm ^{− 3} ] Thickness: 1000 [Å]

Graded layer 35 Material: n ⁺ -InGaAs (In composition increases toward the surface side) Impurity concentration: 1 × 10 ¹⁹ [cm ⁻³ ] Etching stop layer 36 Material: GaAs Thickness: 30 [Å]

Material of graded layer 37: n ⁺ -InGaAs (In composition is increased toward the surface side, and specifically, the In composition is 0 → 0.5 in the entire graded layer 35 + graded layer 37. ) Impurity concentration: 1 x 10 ¹⁹ [cm ^-3 ] Thickness: 500 [Å] (Graded layer 35 ⁺ Graded layer 37) Electrode contact layer 38 Material: n ⁺ -InGaAs (In composition is 0.5) Impurity concentration: 1 x 10 ¹⁹ [cm ^-3 ] Thickness: 500 [Å]

4- (2) Chemical vapor deposition
position (CVD) method,
A thickness of, for example, about 1000 is formed on the electrode contact layer 38.
A SiON film 39 of [Å] is formed.

4- (3) A resist film (not shown) covering the element region is formed by applying a resist process in the lithography technique.

4- (4) By applying the ion implantation method, the step 4-
Oxygen ions are implanted using the resist film formed in (3) as a mask to form the insulating region 40.

As the conditions for the ion implantation, for example, a dose amount, for example, 2 × 10 ¹² [cm ⁻² ] ion acceleration energy: 150 [keV] may be adopted.

Of course, the insulating region 40 formed here needs to have a depth enough to reach the substrate 31 made of semi-insulating GaAs.

4- (5) By the way, InGaAs cannot be insulated by implantation of oxygen ions. Therefore, in order to separate the elements from the electrode contact layer 38 on the surface to the graded layer 35 between elements, it is necessary to form a mesa.

Therefore, first, by applying a wet etching method using buffered hydrofluoric acid as an etchant, the SiON film 39 is patterned using the resist film formed in the step 4- (3) as a mask. .

The SiON film 3 was dipped in a resist stripping solution.
The resist film used as a mask for patterning 9 is removed.

As a result, the SiON film 39 is in a state of covering the element region and capable of acting as an etching mask having sidewalls that are forward tapered.

4- (6) By applying the dry etching method in which the etching gas is a mixed gas of CH ₄ , H ₂ , and CO ₂ , the mesa reaching from the surface electrode contact layer 38 to the etching stop layer 36. -Perform etching.

As described above, the side wall of the mesa thus formed has a forward taper like the side wall of the SiON film 39. Here, the etching gas used was CH ₄ : H ₂ = 1: 4, to which 8% CO ₂ was added.

4- (7) Mesa etching of the etching stop layer 36 and the graded layer 35 is performed by applying a wet etching method using HF + H ₂ O ₂ + H ₂ O as an etchant.

As described above, since the etching stop layer 36 and the graded layer 35 are thin, the etching control thereof is easy and an error hardly occurs.

4- (8) Immersing in buffered hydrofluoric acid to remove the SiON film 39 to complete a mesa having a forward tapered side wall.

See FIG. 4B. 4- (9) By applying the CVD method, the thickness is, for example, 3000.
An insulating film 41 made of SiON which is [Å] is formed.

4- (10) Resist process in lithography technology, and
By applying a wet etching method using buffered hydrofluoric acid as an etchant, the insulating film 41 made of SiON is etched to form the ohmic electrode contact window 41A.

4- (11) An Al film having a thickness of 2500 [Å] is formed by applying the vacuum deposition method and the lift-off method with the resist film formed in the step 4- (10) remaining. The ohmic electrodes 42 and 43 are formed.

See FIG. 5 5- (1) Forming a gate recess by applying a resist process in the lithography technique and a dry etching method using an etching gas of C ₂ F ₆ + CHF ₃ + He. The portion of the insulating film 41 made of SiON corresponding to the planned portion is etched to form the opening 41B.

Opening 4 formed by the etching
The side wall exposed in 1B has a vertical shape.

5- (2) Etching reaching the etching stop layer 36 from the electrode contact layer 38 on the surface by applying a dry etching method using a mixed gas of CH ₄ , H ₂ and CO _{2 as} an etching gas. To form part of the gate recess 34A.

Gate recess 3 formed by this
Part of 4A has SiON on the exposed sidewall.
Like the side wall of the insulating film 41 made of, it becomes substantially vertical. Here, again, as the etching gas, CH ₄ : H ₂ = 1: 4, and 8 [%]
Of CO ₂ was used.

5- (3) The etching stop layer 36 and the graded layer 35 are etched by applying a wet etching method using HF + H ₂ O ₂ + H ₂ O as an etchant to extend the gate recess 34A. To do.

5- (4) The cap layer 34 is etched by applying a dry etching method using a chlorine-based gas or a fluorine-based gas as the etching gas to further extend the gate recess 34A. Note that this etching automatically stops at the surface of the electron supply layer 33.

5- (5) By applying the vacuum deposition method while leaving the resist film used as the etching mask of the gate recess 34A as it is, the Al film having a thickness of 3000 [Å] is applied.
Form a film.

5- (6) The Al film formed in the step 5- (5) is immersed in a resist stripping solution to dissolve and remove the resist film used as the etching mask of the gate recess 34A. Is patterned by the lift-off method to form the gate electrode 4
4 is formed.

The present invention is not limited to the above-described embodiments, and many other modifications can be realized.

For example, although Al is used as the material of the ohmic electrode or the gate electrode in the above-mentioned embodiment,
For this, another material such as Ti / Pt / Au stacked in order from the substrate side may be used.

[0067]

In the dry etching method and the method for manufacturing a semiconductor device according to the present invention, etching is performed with a sidewall having the same angle as that of the sidewall of the InGaAs layer after etching on the InGaAs layer. An insulating film acting as a mask is formed, the insulating film is used as a mask, and CH
_The InGaAs layer is etched by applying a dry etching method using a mixed gas of ₄ and H ₂ and CO ₂ as an etching gas.

According to the above structure, when InGaAs mesa etching for element isolation is performed, the side wall of the mesa has a forward taper shape. There is no disconnection in the part, and furthermore, the dry etching that forms the mesa surely stops at the etching stopper layer, and then the remaining ultra-thin layer is removed by wet etching. Accurate control of the etching depth is easy. Also, when etching is performed to form the gate recess, vertical side walls can be formed, which is effective for miniaturization. Also, in this case, the etching depth must be accurately controlled. You can For this reason, it is possible to easily manufacture a semiconductor device including a miniaturized HEMT that does not change in characteristics and can maintain high reliability and high performance.

[Brief description of drawings]

FIG. 1 is a fragmentary oblique view showing a HEMT in a process main part for explaining the principle of the present invention.

FIG. 2 is a fragmentary side view showing the etching shape of an InGaAs layer for explaining the case of performing mesa etching suitable for mesa etching and gate recess etching along the basic points.

FIG. 3 is a cutaway side view of a main part showing an etching shape of an InGaAs layer for explaining a mesa etching mechanism.

FIG. 4 is a side sectional view of a main part of a HEMT in a process key part for explaining an embodiment of the present invention.

FIG. 5 is a side sectional view of a main part of the HEMT in a process main part for explaining one embodiment of the present invention.

FIG. 6 is a fragmentary perspective view showing a HEMT for explaining a conventional technique.

[Explanation of symbols]

11 semi-insulating GaAs substrate 12 i-GaAs channel layer 13 n ⁺ -AlGaAs electron supply layer 14 n-GaAs cap layer 14A gate recess 15 n ⁺ -InGaAs graded layer 15A GaAs etching formed in the graded layer 15 Stop layer 16 n ⁺ -InGaAs electrode contact layer 17 Insulating region 18 Non-alloyed ohmic electrode 19 Non-alloyed ohmic electrode 20 Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/778 21/338 29/812 H01L 29/44 C 7376-4M 29/80 H

Claims (4)

[Claims] 1. The I after etching on an InGaAs layer.
forming an insulating film having sidewalls at the same angle as that required for the nGaAs layer and acting as an etching mask; and then using the insulating film as a mask and mixing CH _4, H ₂ and CO ₂ . Dry with gas as etching gas
And a step of etching the InGaAs layer by applying an etching method. 2. A step of forming an InGaAs layer, which is a contact layer of the non-alloyed ohmic electrode, on the substrate with an etching stopper layer made of GaAs interposed therebetween, and then the step of etching the I-layer on the InGaAs layer.
forming an insulating film having the same forward tapered sidewall as that required for the nGaAs layer and acting as an etching mask; and then using the insulating film as a mask and CH _4, H ₂ and CO Dry with ₂ mixed gas as etching gas
A step of applying an etching method to etch from the surface of the InGaAs layer to the etching stop layer, and then etching the etching stop layer and the underlying InGaAs
Completing the mesa with forward tapered sidewalls by etching the layer by applying a wet etching process, and then a pair of non-alloys that make ohmic contact with at least the top surface of the InGaAs layer forming the mesa. And a step of forming a patterned ohmic electrode. 3. InGaAs which is a contact layer of a non-alloyed ohmic electrode with a carrier supply layer as a base on a substrate.
A step of forming a layer with an etching stop layer made of GaAs interposed therebetween, and then forming the I-layer after the etching on the InGaAs layer.
forming an insulating film having substantially the same vertical vertical side wall opening required for the nGaAs layer and acting as an etching mask; and then using the insulating film as a mask and CH Dry gas containing ₄ and H ₂ and CO ₂ as etching gas
An etching method is applied from the surface of the InGaAs layer to the etching stop layer to form a gate recess having substantially vertical side walls; and then, the etching stop layer and the underlying InGaAs
Stretching the gate recess with substantially vertical raised sidewalls by etching the layer by applying a wet etching method, and then applying a dry etching method to reach the carrier supply layer And further extend the gate recess having the substantially vertical raised sidewalls by etching to complete, and then a lift-off method is applied to form a gate electrode in the gate recess. And a step of manufacturing the semiconductor device. 4. The In composition of the InGaAs layer, which is the contact layer of the non-alloyed ohmic electrode, is such that the In composition gradually increases from the substrate side to the surface side and maintains a constant value near the surface. The method of manufacturing a semiconductor device according to claim 2,