JPH08191072A - Thin film circuit element terminal electrode structure - Google Patents
Thin film circuit element terminal electrode structureInfo
- Publication number
- JPH08191072A JPH08191072A JP1834295A JP1834295A JPH08191072A JP H08191072 A JPH08191072 A JP H08191072A JP 1834295 A JP1834295 A JP 1834295A JP 1834295 A JP1834295 A JP 1834295A JP H08191072 A JPH08191072 A JP H08191072A
- Authority
- JP
- Japan
- Prior art keywords
- conductive resin
- thin film
- circuit element
- film circuit
- electrode structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 32
- 239000011347 resin Substances 0.000 claims abstract description 34
- 229920005989 resin Polymers 0.000 claims abstract description 34
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 239000010931 gold Substances 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000007747 plating Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子機器に用いられる
薄膜回路素子又は配線板の端子電極構造に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal electrode structure of a thin film circuit element or wiring board used in electronic equipment.
【０００２】[0002]
【従来の技術】図１６は薄膜回路素子の接続用端子電極
の従来の構造例を示す断面図である。図１６は、例え
ば、シリコン（Ｓｉ）の薄膜回路素子１に形成されたア
ルミニウムパッド２の上に中間金属膜（めっき用）２１
を設け、銅めっき２２を行い、その上に、はんだめっき
等で接続用の突起（バンプ）２３を設けたものである。2. Description of the Related Art FIG. 16 is a sectional view showing an example of a conventional structure of a connecting terminal electrode of a thin film circuit element. FIG. 16 shows, for example, an intermediate metal film (for plating) 21 on an aluminum pad 2 formed on a silicon (Si) thin film circuit element 1.
Is provided, copper plating 22 is performed, and projections (bumps) 23 for connection are provided thereon by solder plating or the like.
【０００３】図１７は従来の端子電極構造の説明図であ
り、（Ａ）は金ボール２４を薄膜回路素子１上に金バン
プを形成する説明図、（Ｂ），（Ｃ）は薄膜回路素子１
上に金ボール２４が設けられた素子を配線基板２５に実
装する構造の側面図である。（Ａ）に示したように、上
から金線を挿入し、その先端部分を高電圧でスパークさ
せ加熱溶融してできた金ボール２４を薄膜回路素子１上
のアルミニウムパッド上に超音波及び熱により圧着しバ
ンプを形成する。（Ｂ）のように、配線基板２５の配線
導体パッド２６上に、予めはんだプリコート２７（予備
はんだ）を設けておき、その部分に素子の金ボール２４
を対応させ、（Ｃ）のように、両者を圧着して加熱し、
金ボール２４とはんだプリコート２７を溶融接合させ
る。FIG. 17 is an explanatory view of a conventional terminal electrode structure. (A) is an explanatory view of forming gold bumps on a gold ball 24 on a thin film circuit element 1, and (B) and (C) are thin film circuit elements. 1
6 is a side view of a structure in which an element having a gold ball 24 provided thereon is mounted on a wiring board 25. FIG. As shown in (A), a gold wire is inserted from above, and the gold ball 24 formed by heating and melting the tip portion of the gold wire by sparking with a high voltage is ultrasonically and heat-treated on the aluminum pad on the thin film circuit element 1. To form bumps. As shown in (B), a solder precoat 27 (preliminary solder) is previously provided on the wiring conductor pad 26 of the wiring board 25, and the gold ball 24 of the element is provided at that portion.
Correspond to each other, and as shown in (C), press and heat both,
The gold ball 24 and the solder precoat 27 are melt-bonded.
【０００４】[0004]
【発明が解決しようとする課題】しかし、上記従来の構
造では、図１６の例の場合、めっき工程等が必要となり
複雑な製造手順をとるため薄膜回路素子のコストが高く
なる。また、図１７の例の場合、各パッド１つ１つに金
ボールの圧着を行うため、パッド数（電極数）が増える
と工数がかかり同じくコスト高になってしまう問題があ
る。また、突起（バンプ）の高さや形状についても、前
記従来の工法だとあまり高くできず、高さの精度につい
てもコントロールが難しく、バンプの形状も球形や半球
形もしくは、だ円形状の物しかできない等の問題があ
る。However, in the above-described conventional structure, in the case of the example of FIG. 16, a plating process and the like are required and a complicated manufacturing procedure is taken, so that the cost of the thin film circuit element becomes high. Further, in the case of the example of FIG. 17, since a gold ball is pressure-bonded to each pad, there is a problem in that the number of pads (the number of electrodes) increases and the cost also rises. Also, the height and shape of the bumps (bumps) cannot be increased so much with the above-mentioned conventional method, and it is difficult to control the height accuracy, and the bumps can only be spherical, hemispherical, or elliptical. There are problems such as not being able to.
【０００５】本発明の目的は、従来技術の問題点であっ
た端子電極の複雑な製造手順を排除して低コスト化を実
現し、かつ、従来の寸法や精度の制約を大幅に改善した
薄膜回路素子の端子電極構造を提供することにある。The object of the present invention is to realize a cost reduction by eliminating the complicated manufacturing procedure of the terminal electrode, which is a problem of the prior art, and to greatly improve the conventional restrictions on the size and accuracy. It is to provide a terminal electrode structure of a circuit element.
【０００６】[0006]
【課題を解決するための手段】本発明の薄膜回路素子の
端子電極構造は、薄膜回路素子の端子配置位置に設けら
れたパッド上に導電性樹脂端子部を備えたことを特徴と
するものである。A terminal electrode structure of a thin film circuit element according to the present invention is characterized in that a conductive resin terminal portion is provided on a pad provided at a terminal arrangement position of the thin film circuit element. is there.
【０００７】さらに、薄膜回路素子の端子配置位置に設
けられたパッド上に第１の導電性樹脂端子部と該第１の
導電性樹脂端子部の上に第２の導電性樹脂端子部を備え
たことを特徴とするものである。上記第２の導電性樹脂
端子部は、角柱形，円錐形，四角錐形，円柱形のいずれ
かであることを特徴とする。Further, a first conductive resin terminal portion is provided on a pad provided at a terminal arrangement position of the thin film circuit element, and a second conductive resin terminal portion is provided on the first conductive resin terminal portion. It is characterized by that. The second conductive resin terminal portion is characterized in that it has any one of a prism shape, a cone shape, a quadrangular pyramid shape, and a column shape.
【０００８】[0008]
【実施例】図１は請求項２に記載した本発明の第１の実
施例を示す側面図であり、１は薄膜回路素子、２はアル
ミニウムパッド、３及び４は導電性樹脂端子部である。
図２は上記本発明の端子部４の各種形状例を示す斜視図
である。（Ａ）は円錐形、（Ｂ）は円錐台形、（Ｃ）は
四角錐形、（Ｄ）は四角台形、（Ｅ）は円柱形を示す。1 is a side view showing a first embodiment of the present invention as set forth in claim 2, 1 is a thin film circuit element, 2 is an aluminum pad, and 3 and 4 are conductive resin terminal portions. .
FIG. 2 is a perspective view showing various examples of the shape of the terminal portion 4 of the present invention. (A) shows a cone, (B) shows a truncated cone, (C) shows a pyramid, (D) shows a trapezoid, and (E) shows a cylinder.
【０００９】以下、上記図１に示した本発明の第１の実
施例の製作手順について説明する。図３〜図８は第１の
実施例の製作過程の説明図である。いずれも縦切断部分
端面図である。図３は、薄膜回路素子１の引出電極部分
にアルミニウムパッド２が形成された状態を示す。図４
は治具として用いてる突起形成板５を示し、離型性の良
い材質又は、表面に離型処理を施した平板に薄膜回路素
子１の電極パッド２の位置と相対する位置に、必要とす
る突起（バンプ）寸法と同じ大きさのくぼみ６を設けた
突起形成板５である。次に、図５のように、突起形成板
５に導電性樹脂４を印刷し、くぼみ６にスキージ７によ
って導電性樹脂４を充填する。そして、突起形成板５を
加熱炉（オーブン）に入れて導電性樹脂４を硬化させ
る。次に、図６に示すように、硬化後、硬化させた樹脂
４の上に再度導電性樹脂３をスキージ７によって印刷す
る。次に、図７のように、突起形成板５のくぼみ６の位
置と薄膜回路素子１のパッド２の位置を合わせて貼り合
わせる。そして、加熱炉（オーブン）に入れて導電性樹
脂３を硬化させると同時に先に硬化させた導電性樹脂４
と接合する。次に、図８のように、突起形成板５から、
導電性樹脂端子部３，４が形成された薄膜回路素子１を
外す。このようにして、図１に示した本発明の第１の実
施例の端子電極構造が得られる。The manufacturing procedure of the first embodiment of the present invention shown in FIG. 1 will be described below. 3 to 8 are explanatory views of the manufacturing process of the first embodiment. Both are vertical cut partial end views. FIG. 3 shows a state in which the aluminum pad 2 is formed on the extraction electrode portion of the thin film circuit element 1. FIG.
Indicates a projection forming plate 5 used as a jig, which is required at a position opposite to the position of the electrode pad 2 of the thin film circuit element 1 on a material having a good releasability or a flat plate whose surface is subjected to a release treatment. The projection forming plate 5 is provided with a recess 6 having the same size as the size of the projection (bump). Next, as shown in FIG. 5, the conductive resin 4 is printed on the protrusion forming plate 5, and the recess 6 is filled with the conductive resin 4 by the squeegee 7. Then, the protrusion forming plate 5 is placed in a heating furnace (oven) to cure the conductive resin 4. Next, as shown in FIG. 6, after the curing, the conductive resin 3 is printed again on the cured resin 4 with the squeegee 7. Next, as shown in FIG. 7, the projection 6 and the pad 2 of the thin film circuit element 1 are aligned in position with the depressions 6 and bonded. Then, the conductive resin 3 is placed in a heating oven (oven) to cure the conductive resin 3 and at the same time, the conductive resin 4 previously cured.
Join with. Next, as shown in FIG. 8, from the projection forming plate 5,
The thin film circuit element 1 on which the conductive resin terminal portions 3 and 4 are formed is removed. In this way, the terminal electrode structure of the first embodiment of the present invention shown in FIG. 1 is obtained.
【００１０】図９は請求項１に記載した本発明の第２の
実施例を示す側面図である。図１０〜図１５は図９の第
２の実施例の製作過程を示す説明図である。いずれも縦
切断部分端面図である。先ず、図１０のように、離型性
の良い材質又は、表面に離型処理を施した平板に薄膜回
路素子の電極パッドと同じ位置に、必要とする突起（バ
ンプ）寸法と同じ大きさのくぼみ６を設けた突起形成板
５と、それと同じ位置に穴１１を明けたメタルマスク１
０を用意する。これらはいずれも治具として使用する。
次に、図１１のように、突起形成板５とメタルマスク１
０とをくぼみ６と穴１１の位置を合わせてセットする。
次に、図１２のように、導電性樹脂をスキージ７で充填
し印刷する。次に、図１３のように、メタルマスク１０
をとり外した後、突起形成板５のくぼみ６の位置に形成
された導電性樹脂端子部９と薄膜回路素子１のパッド２
の位置を合わせ、図１４のように貼り合わせる。そのま
ま加熱炉（オーブン）に入れて導電性樹脂９を硬化させ
る。次に、図１５のように、突起形成板５から、導電性
樹脂端子部９が形成された薄膜回路素子１を外す。この
ようにして、図９に示した本発明の第２の実施例の端子
電極構造が得られる。FIG. 9 is a side view showing a second embodiment of the present invention described in claim 1. 10 to 15 are explanatory views showing the manufacturing process of the second embodiment of FIG. Both are vertical cut partial end views. First, as shown in FIG. 10, a material having a good releasability or a flat plate having a surface subjected to a releasability treatment is placed at the same position as the electrode pad of the thin film circuit element and has the same size as a required bump (bump) dimension. A projection forming plate 5 having a recess 6 and a metal mask 1 having a hole 11 at the same position as the projection forming plate 5.
Prepare 0. All of these are used as jigs.
Next, as shown in FIG. 11, the protrusion forming plate 5 and the metal mask 1
Set 0 and 0 so that the recesses 6 and the holes 11 are aligned.
Next, as shown in FIG. 12, a conductive resin is filled with a squeegee 7 and printed. Next, as shown in FIG. 13, the metal mask 10
After the removal, the conductive resin terminal portion 9 and the pad 2 of the thin film circuit element 1 formed at the position of the recess 6 of the projection forming plate 5 are removed.
And align as shown in FIG. The conductive resin 9 is cured by placing it in a heating furnace (oven) as it is. Next, as shown in FIG. 15, the thin film circuit element 1 on which the conductive resin terminal portion 9 is formed is removed from the projection forming plate 5. In this way, the terminal electrode structure of the second embodiment of the present invention shown in FIG. 9 is obtained.
【００１１】[0011]
【発明の効果】本発明を実施することにより、次の効果
が得られる。 （１）接続用端子電極形成が容易になり、作業工程が簡
素化される。 （２）薄膜回路素子、又は配線板を複数個一括して多数
の端子電極を同時に形成することができる。例えば、ウ
ェハや多数個取付された配線板での処理が可能となる。 （３）上記（１）の理由から従来のプロセスと比較し工
数が減るため、低コスト化が図れる。 （４）接続用端子電極の形状，寸法を必要に応じて所望
の形状に容易に形成できる。又、高さも高くでき精度も
向上する。 （５）上記（４）の理由より、次工程の配線基板への実
装工程で実装歩留まりが良くなり、装置の品質，信頼性
の向上につながる。The following effects can be obtained by implementing the present invention. (1) The connection terminal electrode can be easily formed, and the work process can be simplified. (2) A large number of thin film circuit elements or a plurality of wiring boards can be collectively formed to simultaneously form a large number of terminal electrodes. For example, it is possible to perform processing on a wafer or a wiring board to which a large number of wafers are attached. (3) Because of the above-mentioned reason (1), the number of steps is reduced as compared with the conventional process, so that the cost can be reduced. (4) The shape and size of the connecting terminal electrode can be easily formed into a desired shape as required. Also, the height can be increased and the accuracy is improved. (5) Due to the reason (4) above, the mounting yield is improved in the subsequent step of mounting on the wiring board, which leads to improvement in the quality and reliability of the device.
【図１】本発明の第１の実施例を示す側面図である。FIG. 1 is a side view showing a first embodiment of the present invention.
【図２】図１の端子部の各種形状を示す斜視図である。FIG. 2 is a perspective view showing various shapes of a terminal portion of FIG.
【図３】本発明を適用する薄膜回路素子本体の側面図で
ある。FIG. 3 is a side view of a thin film circuit element body to which the present invention is applied.
【図４】本発明の第１の実施例の製作過程説明図であ
る。FIG. 4 is an explanatory view of the manufacturing process of the first embodiment of the present invention.
【図５】本発明の第１の実施例の製作過程説明図であ
る。FIG. 5 is an explanatory diagram of the manufacturing process of the first embodiment of the present invention.
【図６】本発明の第１の実施例の製作過程説明図であ
る。FIG. 6 is an explanatory view of the manufacturing process of the first embodiment of the present invention.
【図７】本発明の第１の実施例の製作過程説明図であ
る。FIG. 7 is an explanatory diagram of the manufacturing process of the first embodiment of the present invention.
【図８】本発明の第１の実施例の製作過程説明図であ
る。FIG. 8 is an explanatory diagram of the manufacturing process of the first embodiment of the present invention.
【図９】本発明の第２の実施例を示す側面図である。FIG. 9 is a side view showing a second embodiment of the present invention.
【図１０】本発明の第２の実施例の製作過程説明図であ
る。FIG. 10 is an explanatory view of the manufacturing process of the second embodiment of the present invention.
【図１１】本発明の第２の実施例の製作過程説明図であ
る。FIG. 11 is an explanatory view of the manufacturing process of the second embodiment of the present invention.
【図１２】本発明の第２の実施例の製作過程説明図であ
る。FIG. 12 is an explanatory diagram of the manufacturing process of the second embodiment of the present invention.
【図１３】本発明の第２の実施例の製作過程説明図であ
る。FIG. 13 is an explanatory view of the manufacturing process of the second embodiment of the present invention.
【図１４】本発明の第２の実施例の製作過程説明図であ
る。FIG. 14 is an explanatory view of the manufacturing process of the second embodiment of the present invention.
【図１５】本発明の第２の実施例の製作過程説明図であ
る。FIG. 15 is an explanatory diagram of the manufacturing process of the second embodiment of the present invention.
【図１６】従来の端子電極構造例図である。FIG. 16 is a diagram showing an example of a conventional terminal electrode structure.
【図１７】従来の端子電極構造の説明図である。FIG. 17 is an explanatory diagram of a conventional terminal electrode structure.
１ 薄膜回路素子 ２ アルミニウムパッド ３，４ 導電性樹脂端子部 ５ 突起形成板 ６ くぼみ ７ スキージ ８ マスク ９ 導電性樹脂端子部 １０ メタルマスク １１ 穴 ２１ 中間金属膜 ２２ 銅めっき層 ２３ はんだバンプ ２４ 金ボール ２５ 配線基板 ２６ 配線導体パッド ２７ はんだプリコート DESCRIPTION OF SYMBOLS 1 Thin film circuit element 2 Aluminum pad 3,4 Conductive resin terminal portion 5 Protrusion forming plate 6 Recess 7 Squeegee 8 Mask 9 Conductive resin terminal portion 10 Metal mask 11 Hole 21 Intermediate metal film 22 Copper plating layer 23 Solder bump 24 Gold ball 25 wiring board 26 wiring conductor pad 27 solder precoat
Claims (6)
たパッド上に導電性樹脂端子部を備えたことを特徴とす
る薄膜回路素子の端子電極構造。1. A terminal electrode structure of a thin film circuit element, comprising a conductive resin terminal portion on a pad provided at a terminal arrangement position of the thin film circuit element.
たパッド上に第１の導電性樹脂端子部と該第１の導電性
樹脂端子部の上に第２の導電性樹脂端子部を備えたこと
を特徴とする薄膜回路素子の端子電極構造。2. A first conductive resin terminal portion is provided on a pad provided at a terminal arrangement position of a thin film circuit element, and a second conductive resin terminal portion is provided on the first conductive resin terminal portion. A terminal electrode structure of a thin film circuit element characterized by the above.
であることを特徴とする請求項２記載の薄膜回路素子の
端子電極構造。3. The terminal electrode structure for a thin film circuit element according to claim 2, wherein the second conductive resin terminal portion has a prismatic shape.
であることを特徴とする請求項２記載の薄膜回路素子の
端子電極構造。4. The terminal electrode structure for a thin film circuit element according to claim 2, wherein the second conductive resin terminal portion has a conical shape.
形であることを特徴とする請求項２記載の薄膜回路素子
の端子電極構造。5. The terminal electrode structure for a thin film circuit element according to claim 2, wherein the second conductive resin terminal portion has a quadrangular pyramid shape.
であることを特徴とする請求項２記載の薄膜回路素子の
端子電極構造。6. The terminal electrode structure for a thin film circuit element according to claim 2, wherein the second conductive resin terminal portion has a cylindrical shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1834295A JPH08191072A (en) | 1995-01-11 | 1995-01-11 | Thin film circuit element terminal electrode structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1834295A JPH08191072A (en) | 1995-01-11 | 1995-01-11 | Thin film circuit element terminal electrode structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08191072A true JPH08191072A (en) | 1996-07-23 |
Family
ID=11968991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1834295A Pending JPH08191072A (en) | 1995-01-11 | 1995-01-11 | Thin film circuit element terminal electrode structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08191072A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100426914B1 (en) * | 1997-07-15 | 2004-04-13 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and method of fabrication thereof |
| WO2008065926A1 (en) * | 2006-11-28 | 2008-06-05 | Panasonic Corporation | Electronic component mounting structure and method for manufacturing the same |
| JP2009272383A (en) * | 2008-05-01 | 2009-11-19 | Fujitsu Ltd | Semiconductor device and bonding method of substrate |
-
1995
- 1995-01-11 JP JP1834295A patent/JPH08191072A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100426914B1 (en) * | 1997-07-15 | 2004-04-13 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and method of fabrication thereof |
| US7390732B1 (en) | 1997-07-15 | 2008-06-24 | Hitachi, Ltd. | Method for producing a semiconductor device with pyramidal bump electrodes bonded onto pad electrodes arranged on a semiconductor chip |
| WO2008065926A1 (en) * | 2006-11-28 | 2008-06-05 | Panasonic Corporation | Electronic component mounting structure and method for manufacturing the same |
| US8120188B2 (en) | 2006-11-28 | 2012-02-21 | Panasonic Corporation | Electronic component mounting structure and method for manufacturing the same |
| JP2009272383A (en) * | 2008-05-01 | 2009-11-19 | Fujitsu Ltd | Semiconductor device and bonding method of substrate |
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