JPH08204177A - Manufacture of high breakdown voltage mos transistor - Google Patents

Abstract

PURPOSE: To provide a manufacturing method of a high breakdown MOS transistor which can realize fine structure and high level of integration. CONSTITUTION: A process for forming a thermal oxide film 10 thicker than a gate electrode 4 on an N-type silicon substrate 1 between the end of the gate electrode 4 and a heavily doped drain diffusion layer 8 is introduced. The layer which electric lines of force passes through when they go from the end of a depletion layer to the gate electrode 4 is the thick thermal oxide layer, whose dielectric strength is high as compared with an interlayer insulating film composed of a BPSG film formed by the conventional CVD method. Hence the possibility that a gate oxide film 3 is broken down as in the conventional case does not exist, and a high drain breakdown voltage can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an open-drain type output transistor such as a microcomputer, and more particularly to a high breakdown voltage MOS transistor which is used as a driving transistor for an FLT (fluorescent display tube) and requires a drain breakdown voltage of about 45V. It relates to a manufacturing method.

[0002]

2. Description of the Related Art A method of manufacturing a high breakdown voltage transistor of this type will be described with reference to FIG. Reference numeral 51 shown in FIG. 9 is a semiconductor substrate of one conductivity type, for example, an N-type silicon substrate. First, a selective oxide film 52 (LOCOS) for element isolation is formed on the substrate 51. In the next step, a gate oxide film 53 is formed on the N-type silicon substrate 51 excluding the selective oxide film 52, and then a gate electrode 54 made of, for example, polysilicon is formed on the gate oxide film 53.

Next, the entire surface of the substrate 51 is coated with a lyoxide film 55 to form a low concentration P- drain diffusion layer 56 in the drain region adjacent to the gate electrode 54.
Subsequently, a P + high-concentration source diffusion layer 57 is formed in the source region adjacent to the gate electrode 54, and a high-concentration source diffusion layer 57 in the low-concentration drain diffusion layer 56 is separated from the gate electrode 54. A P + drain diffusion layer 58 is formed.

Then, an interlayer insulating film 59 made of a BPSG film is formed by a CVD method, a contact hole is formed in the interlayer insulating film 59 by using a photoresist film (not shown) as a mask, and the source diffusion is performed through the contact hole. Layer 57
A source electrode 60 and a drain electrode 61 made of aluminum and connected to the drain diffusion layer 58 are formed.

A region shown by a dotted line in the drawing is a depletion layer which expands when a high voltage is applied to the drain electrode 61. In such a high breakdown voltage MOS transistor, a negative high voltage (for example, Vd =
-45V), and the ground voltage (Vg = Vs = 0) is applied to the gate electrode 54 and the source electrode 60, the strong electric field applied to the gate oxide film 53 is weakened. Therefore, it is used as a high breakdown voltage MOS transistor. To be done.

However, with the recent miniaturization and high integration of LSI, the gate oxide film of the transistor is inevitably thin. For example, 170 Å for 0.8 μm rule LSI and 1 for 0.5 μm rule LSI
It is as thin as 00Å to 90Å. As a result, the electric field applied to the gate oxide film becomes strong, and the drain breakdown voltage deteriorates. Therefore, conventionally, as shown in FIG. 9, the distance L between the gate electrode 54 and the drain diffusion layer 58 is 9 μm.
Although it had to be designed for a long time, this would increase the pattern size, which would violate the demand for high integration of the LSI.

On the other hand, a thin gate oxide film for a normal transistor and a thick gate oxide film for a high voltage transistor are used.
Although it is conceivable to form different types, it is not preferable because the number of manufacturing processes for the gate oxide film selection mask and oxidation increases. Further, at this time, since the gate oxide film has a different thickness, a mask for adjusting the threshold voltage is required, and two masks are added. In addition, the thick gate oxide film reduces the driving capability of the high breakdown voltage transistor.

[0008]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method of manufacturing a high breakdown voltage MOS transistor which enables miniaturization and high integration.

[0009]

Therefore, the invention of claim 1 forms a selective oxide film on a semiconductor substrate of one conductivity type, and forms a gate oxide film on the semiconductor substrate excluding the selective oxide film. A step of forming a gate electrode through the gate oxide film, a step of forming a low-concentration reverse-conductivity-type drain diffusion layer in contact with one end of the gate electrode, and the other of the gate electrodes A high-concentration reverse-conductivity type source diffusion layer is formed so as to be in contact with an end of the gate electrode, and a high-concentration reverse-conductivity type drain diffusion is formed in the low-concentration drain diffusion layer with a distance from one end of the gate electrode. A step of forming a layer, and a step of forming a thermal oxide film having a thickness larger than that of the gate oxide film on the semiconductor substrate between one end of the gate electrode and the high-concentration drain diffusion layer. is there.

According to a second aspect of the present invention, a step of forming a selective oxide film on the semiconductor substrate of one conductivity type, a step of forming a gate oxide film on the semiconductor substrate excluding the selective oxide film,
Forming a gate electrode through the gate oxide film, forming a low-concentration reverse-conductivity-type drain diffusion layer in contact with one end of the gate electrode, and forming another end of the gate electrode at the other end. A high-concentration reverse-conductivity type source diffusion layer is formed so as to be in contact with the low-concentration drain diffusion layer, and a high-concentration reverse-conductivity type drain diffusion layer is formed in the low-concentration drain diffusion layer at a distance from one end of the gate electrode And a step of forming a silicon nitride film on the entire surface, and a step of selectively removing the silicon nitride film between at least one end of the gate electrode and the high-concentration drain diffusion layer to form an opening. And performing a selective oxidation using the silicon nitride film as a mask, thereby forming a thermal film having a thickness larger than that of the gate oxide film on the semiconductor substrate between one end of the gate electrode and the high-concentration drain diffusion layer. And a step of forming a monolayer.

Further, the invention of claim 3 comprises the steps of forming a selective oxide film on the semiconductor substrate of one conductivity type, and forming a gate oxide film on the semiconductor substrate excluding the selective oxide film.
Forming a gate electrode through the gate oxide film, forming a low-concentration reverse-conductivity-type drain diffusion layer in contact with one end of the gate electrode, and forming another end of the gate electrode at the other end. A high-concentration reverse-conductivity type source diffusion layer is formed so as to be in contact with the low-concentration drain diffusion layer, and a high-concentration reverse-conductivity type drain diffusion layer is formed in the low-concentration drain diffusion layer at a distance from one end of the gate electrode. And a step of forming a silicon nitride film on the entire surface, and a step of selectively removing the silicon nitride film between at least one end of the gate electrode and the high-concentration drain diffusion layer to form an opening. And a step of injecting an impurity of opposite conductivity type from the opening to form a compensation diffusion layer of a high concentration drain diffusion layer, and performing selective oxidation using the silicon nitride film as a mask, On a semiconductor substrate between the drain diffusion layer one end and the high concentration of and a step of forming a thermal oxide film having a larger thickness than the gate oxide film.

[0012]

According to the present invention, the selective oxide film is formed on the semiconductor substrate of one conductivity type, the gate oxide film is formed on the semiconductor substrate excluding the selective oxide film, and the gate oxide film is formed. A gate electrode is formed through the drain electrode, a low-concentration reverse conductivity type drain diffusion layer is formed so as to be in contact with one end of the gate electrode, and a high-concentration reverse conductivity is formed so as to be in contact with the other end of the gate electrode. Type source diffusion layer is formed, and a high-concentration reverse conductivity type drain diffusion layer is formed in the low-concentration drain diffusion layer at a distance from one end of the gate electrode. By forming a thermal oxide film having a thickness greater than that of the gate oxide film on the semiconductor substrate between the edge and the high-concentration drain diffusion layer, there is no risk of the gate oxide film being destroyed by a strong electric field, Drain breakdown voltage realized Kill.

According to the invention of claim 2, after forming each diffusion layer as in the invention of claim 1, a silicon nitride film is formed on the entire surface of the substrate, and at least one end of the gate electrode and the high-concentration drain are formed. The silicon nitride film between the diffusion layer and the diffusion layer is selectively removed to form an opening, and selective oxidation is performed using the silicon nitride film as a mask, thereby forming one end of the gate electrode and the high-concentration drain diffusion layer. A thermal oxide film having a thickness larger than that of the gate oxide film can be formed on the semiconductor substrate between and, and it can be used as a high breakdown voltage transistor.

Further, in the third aspect of the present invention, as in the second aspect of the present invention, an impurity of opposite conductivity type is injected from an opening portion formed by selectively removing the silicon nitride film to compensate for a high concentration drain diffusion layer. By forming a diffusion layer and performing selective oxidation using the silicon nitride film as a mask, a film thickness larger than that of the gate oxide film is formed on the semiconductor substrate between one end of the gate electrode and the high-concentration drain diffusion layer. A thermal oxide film can be formed, which can be used as a high breakdown voltage transistor, and by forming the compensation diffusion layer,
The concentration of the drain diffusion layer can be maintained.

[0015]

An embodiment of the present invention will be described in detail below with reference to the drawings. Reference numeral 1 shown in FIG. 1 denotes a semiconductor substrate of one conductivity type, for example, an N-type silicon substrate.
OS) is formed, and about 170Å to 240Å is formed on the N-type silicon substrate 1 excluding the selective oxide film 2 in the next step.
A gate oxide film 3 is formed, and a gate electrode 4 having a thickness of about 2500 Å is formed on the gate oxide film 3 as shown in FIG. 2, and a low concentration drain is contacted with one end of the gate electrode 4 by ion implantation with boron ions. The diffusion layer 5 is formed.

Subsequently, as shown in FIG. 3, a lyoxide film 6 is formed on the N-type silicon substrate 1. And BF2
The high-concentration drain is separated from the gate electrode 4 by being included in the high-concentration source diffusion layer 7 and the low-concentration drain diffusion layer 6 so as to come into contact with the other end of the gate electrode 4 by ion implantation with ions. The diffusion layer 8 is formed. Next, as shown in FIG. 4, a silicon nitride film 9 is formed on the entire surface of the substrate 1, and at least the silicon nitride film 9 between one end of the gate electrode 4 and the high-concentration drain diffusion layer 8 is selected. By selectively removing it to form an opening, and selectively oxidizing the silicon nitride film 9 as a mask, as shown in FIG. 5, at least on the N-type silicon substrate 1 between the selective oxide film 2 and the gate electrode 4. A thermal oxide film 10 (SiO2 film) having a thickness larger than that of the gate oxide film 3 and having a thickness of about 3000Å.
To form. Since the thermal oxide film 10 has a high withstand voltage, the gate oxide film 3 is not destroyed even when a strong electric field is applied.

In order to compensate the concentration of the high concentration drain diffusion layer 8 before forming the thermal oxide film 10, for example, an implantation amount of 5E13 / cm 2 (5E13 is 5 times 10 to 13).
It is the intention of riding. ) The following boron ions may be implanted. Then, after the silicon nitride film 9 is selectively removed (see FIG. 6), the substrate 1 is subjected to CVD as shown in FIG.
Interlayer insulating film 11 made of a BPSG film formed by the method
To form a contact hole in the interlayer insulating film 11,
A source electrode 12 and a drain electrode 13 made of aluminum are formed in the source diffusion layer 7 and the drain diffusion layer 8 as shown in FIG. 8 through the contact holes.

A region indicated by a dotted line in FIG. 8 is a depletion layer that spreads when a negative high voltage is applied to the drain electrode 13, and a line of electric force (indicated by an arrow in the figure) from the end of the depletion layer to the gate. The thermal oxide film 10 in which the lines of electric force are thick when going to the electrode 4
Pass through. Here, since the thermal oxide film 10 generally has a higher dielectric strength than the CVD film of the BPSG film, it can sufficiently withstand the destruction even when a strong electric field is applied. As a result, unlike the conventional example, there is no risk of the gate oxide film being destroyed, and a high drain breakdown voltage can be realized.

Further, since the thermal oxide film 10 is formed so as not to overlap the end of the gate electrode 4, the threshold voltage does not change and the current driving capability is maintained. Furthermore, the manufacturing method of the present invention is similarly applied to a P-type semiconductor substrate.

[0020]

As described above, according to the method for manufacturing a high breakdown voltage transistor of the present invention, thermal oxidation having a film thickness larger than that of the gate electrode on the semiconductor substrate between the end of the gate electrode and the high concentration drain diffusion layer. Since the step of forming the film is provided, when the line of electric force goes from the edge of the depletion layer to the gate electrode, the layer through which the line of electric force passes is a thick thermal oxide film.
Since the withstand voltage is higher than that of the interlayer insulating film made of the BPSG film formed by the method, there is no fear of breaking the gate oxide film as in the conventional case, and a high drain withstand voltage can be realized.

Further, since the thermal oxide film is formed so as not to overlap the gate electrode, the threshold voltage does not change, and the current driving capability can be maintained. Further, for example, in an LSI of 0.5 μm rule, the distance L, which was about 9 μm in the past, is about 4.5 μm according to the present invention. Therefore, the pattern size can be reduced by that amount,
Moreover, since the resistance of that portion is lowered, there is an effect that the on-resistance of the transistor can be reduced. Further, since the gate oxide film of the high breakdown voltage transistor and the gate oxide film of the normal transistor can be made to have the same film thickness, the threshold voltage can be made to be the same, which eliminates the need for the threshold voltage adjusting mask as in the conventional case.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a high voltage MOS transistor according to the present invention.

FIG. 2 is a cross-sectional view for explaining the method of manufacturing a high breakdown voltage MOS transistor of the present invention.

FIG. 3 is a cross-sectional view for explaining the method of manufacturing the high breakdown voltage MOS transistor of the present invention.

FIG. 4 is a cross-sectional view for explaining the method of manufacturing the high breakdown voltage MOS transistor of the present invention.

FIG. 5 is a cross-sectional view for explaining the method of manufacturing a high voltage MOS transistor according to the present invention.

FIG. 6 is a cross-sectional view for explaining the method of manufacturing the high breakdown voltage MOS transistor of the present invention.

FIG. 7 is a cross-sectional view for explaining the method of manufacturing the high breakdown voltage MOS transistor of the present invention.

FIG. 8 is a cross-sectional view for explaining the method of manufacturing a high breakdown voltage MOS transistor of the present invention.

FIG. 9 is a cross-sectional view for explaining the conventional method for manufacturing a high breakdown voltage MOS transistor.

Claims (3)

[Claims] 1. A step of forming a selective oxide film on a semiconductor substrate of one conductivity type, a step of forming a gate oxide film on the semiconductor substrate excluding the selective oxide film, and a gate electrode via the gate oxide film. And a step of forming a low-concentration reverse conductivity type drain diffusion layer in contact with one end of the gate electrode, and a high-concentration reverse conductivity type in contact with the other end of the gate electrode. Forming a source diffusion layer of the same, and forming a high-concentration reverse-conductivity-type drain diffusion layer in the low-concentration drain diffusion layer away from one end of the gate electrode; A step of forming a thermal oxide film having a film thickness thicker than that of the gate oxide film on the semiconductor substrate between the edge of the semiconductor device and the high-concentration drain diffusion layer. 2. A step of forming a selective oxide film on a semiconductor substrate of one conductivity type, a step of forming a gate oxide film on the semiconductor substrate excluding the selective oxide film, and a gate electrode via the gate oxide film. And a step of forming a low-concentration reverse conductivity type drain diffusion layer in contact with one end of the gate electrode, and a high-concentration reverse conductivity type in contact with the other end of the gate electrode. Forming a source diffusion layer and forming a high-concentration drain diffusion layer of opposite conductivity type in the low-concentration drain diffusion layer at a distance from one end of the gate electrode, and a silicon nitride film over the entire surface. And a step of selectively removing the silicon nitride film between at least one end of the gate electrode and the high-concentration drain diffusion layer to form an opening, and using the silicon nitride film as a mask. Election Forming a thermal oxide film having a thickness greater than that of the gate oxide film on the semiconductor substrate between one end of the gate electrode and the high-concentration drain diffusion layer by performing selective oxidation. Features high withstand voltage M
Manufacturing method of OS transistor. 3. A step of selectively removing the silicon nitride film to form an opening, and then implanting an impurity of opposite conductivity type from the opening to form a compensation diffusion layer for a high concentration drain diffusion layer. 3. The method for manufacturing a high breakdown voltage MOS transistor according to claim 2, further comprising: