JPH08205103A - Atm line signal generating method and atm line signal processor utilizing same - Google Patents

Abstract

PURPOSE: To accommodate a digital video signal on an ATM line with efficiency. CONSTITUTION: When the digital video signal (270Mbps) of a 525/60 system D1 type is converted into the data format of an ATM line signal and transmitted through two lines, the number of cells of signal components (signals in a horizontal and a vertical blanking period) in a data area other than an active area is 2,860. The number of cells assigned to each line in the AAL5 layer is 11,778. The number of cells assigned to a video signal area is 8,909 in consideration of various control signals. A video signal component in each frame on one ATM line has 9,740 cells, so the cell ratio of the both is 8,909/9,740=0.915. In this case, when a video signal is compressed to >=91.5% for each ATM line, the video signal can be accommodated in the remaining ALL5 layer. The video signal is highly correlated, so data compression to this extent does not spoil the picture quality.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM line signal generation method suitable for transmitting a digital video signal using an ATM line and an A method using the same.
The present invention relates to a TM line signal processing device.

[0002]

2. Description of the Related Art ATM (Asynchronous Transfer Mode;
In a data transmission system that uses a communication line in the asynchronous transfer mode), all information is transmitted in cells, but the required service quality (error rate, etc.) is different in the part related to cell transmission, and cell conversion is performed. In doing so, there is a layer for the purpose of absorbing this difference in service quality. This layer is the ATM adaptation layer (A
AL; ATM Adaptation Layer).

5 for AAL layer protocol types
There are two types, of which type 5 is known as the most simplified type. AAL type 5 (AA
Among the protocol types, the L5 layer) is the type with the smallest number of control signals added to the user information, and its layer structure is shown in FIG.

CPC in the AAL5 layer structure of FIG.
The S sublayer is a convergence / data transfer layer.
Of the sub-layer CS (Convergence Sublayer), a CS common part (Common) that performs a common function that does not depend on services
Part CS). As shown in the figure, the protocol data unit (Protocol DataU) of the CPCS sublayer.
nit), an 8-byte trailer is added to the CPCS payload, which is user information, and then converted into a cell payload.

One cell has 48 bytes when it is formed into a payload, and each cell payload has 5 bytes of ATM.
A header is attached to make up one cell of 53 bytes. A header is attached at a rate of one cell for each of the 26 ATM cells to form a physical layer which is a data transmission format. The bit rate of this physical layer is 155.52 Mbps.

[0006]

By the way, utilizing such an ATM line, a digital video signal, for example, a D1 type digital video signal composed of so-called component signals or a D2 type digital video composed of a composite signal is used. There are some problems to be solved when transmitting signals and the like.

As is well known, the bit rate of the ATM line is 155.52 Mbps. However, since various headers and trailers different from each other are added as ATM line control signals by various ALL layers, the actual transmission capacity is It is less than 155.52 Mbps.

Even in the ALL5 layer described above in which the data amount of the control signal to be added is the smallest, the substantial bit rate is reduced to the following numerical values.

As described above, in the physical layer, a header is added at a rate of 1 cell for every 26 cells. In addition, the maximum number of bytes in the first stage of the CPCS sublayer is 2 16 (= 65536) for the payload for signal transmission, and the trailer amount and CPCS as a whole are multiples of the cell (48 bytes). When the PAD is added, it becomes 65568 bytes, but as is well known, the substantial number of bytes used for transmission as a payload is 65520 bytes. Further, one ATM cell has a structure of 53 bytes, of which 5 bytes are an ATM header. Considering these facts, the effective bit rate per CPCS sublayer is 155.52Mbps x (26/27) x (65520/65568) x (48/53) = 135.53Mbps The effective bit rate of the cell payload is 155.52 Mbps to 135.53 M even without including various control signals for the signal
It will be reduced to bps.

On the other hand, of the digital video signals, for example, a D1 type digital video signal has a sampling frequency of 13.5 MHz, one pixel has a 10-bit configuration, and in addition to the luminance signal Y, a color difference signal C (Cr, Cb). Therefore, the bit rate per frame is 13.5 Mbps x 10 bits x 2 times = 270 bit rate.

In order to transmit a digital video signal of such a bit rate using an ATM line, data such as an address is added to this data, or identification data when separating into two lines. Since they must be added and transmitted, an ATM line having a total bit rate of 270 Mbps or more is required. Therefore, even if two ATM lines are used, the above-mentioned D1 type digital video signal cannot be transmitted.

A digital video signal can be transmitted by using three ATM lines, but when three ATM lines are used, the video signal is distributed over the three ATM lines, so that a luminance signal component and a color difference signal component are provided on each line. Will be divided into and mixed. In order to properly restore the mixed Y / C signals at the receiving source as necessary, an extra new circuit for processing them is required, and 3
Increasing the number of lines used, such as lines, involves the problem that the number of bits of the identification code for distinguishing each line increases.

Further, when a video signal is bundled on a higher level line (for example, 620 Mbps, 1.2 Gbps) on the hierarchy of the transmission line, an unused line occurs when the ATM3 line is used, and the line is efficiently used. I can't plan.

The bit rate of the D2 type digital video signal is 143.2 Mbp in the NTSC system.
s, the PAL system has 177 Mbps, and thus includes the same problem as described above. Bit rates of digital video signals other than these are 135.53 Mbps
If it exceeds, the problematic points are the same as above.

Therefore, the present invention solves the above-mentioned conventional problems, and an ATM line signal generating method and an ATM line signal using the same which can transmit a digital video signal without increasing the lines used. A processing device is proposed.

[0016]

In order to solve the above-mentioned problems, in the ATM line signal generating method according to the present invention described in claim 1, a digital video signal is sent to an ATM line A
When transmitting using the TM adaptation layer protocol, the signal components other than the video signal component of the digital video signal are transmitted as full bits,
Remaining CPCS occupied by this full bit transmission
The video signal is compressed so that the video signal component can be accommodated within the number of transmission cells that can be assigned to the payload, and the compressed video signal component and the signal components other than the video signal are data of the ATM adaptation layer. It is characterized in that the format is converted into an ATM line signal.

An ATM according to the present invention described in claim 5.
In the line signal processing device, the digital video signal is transferred to the ATM.
When transmitting using the line, the compression means for compressing the video signal component of the digital video signal to a predetermined ratio and the bit length of the signal component other than the video signal component are shortened so as to match the ATM line signal. And a bit conversion means for performing bit conversion for converting the signal components into an ATM adaptation layer data format.
It is characterized in that it is composed of an ATM line signal conversion means for converting to a line signal.

[0018]

For example, when converting a 525/60 series, D1 type digital video signal (270 Mbps) into an ATM line signal data format for transmission, as shown in FIG. The number of cells in (the data area included in the period corresponding to the horizontal and vertical blanking signals) is 2860 cells.
Since the number of cells that can be assigned per line in the AAL5 layer is 11778 cells, the number of cells that can be assigned to the video signal component that is the active area includes the trailer component generated during CPCS configuration and the signal component other than the active area. It becomes 8909 cells excluding.

On the other hand, in the case of transmission over the ATM1 line, the video signal component corresponding to the active area per frame is 9740 cells, and the cell ratio of both is 8909/9740 = 0.915. In other words, 9 video signals per ATM line
If compressed to 1.5% or more, the ALL5 layer can accommodate this video signal. Since the video signals have a strong correlation, the image quality will not be impaired by such data compression.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An ATM line signal generating method according to the present invention and an example of an ATM line signal processing apparatus using the same will now be described in detail with reference to the drawings. As the applied digital video signal, an NTSC 4: 2: 2 digital video signal (D1 type in 525/60 system) will be described first.

FIG. 2 shows a frame structure relating to a D1 type digital video signal (hereinafter referred to as D1 signal) in the 525/60 system. The horizontal direction is the horizontal scanning direction (the number of pixels), and the vertical direction is the vertical scanning direction (line). Number). One frame is composed of an active area, which is a portion of video information, and a data area included in the horizontal blanking area H · BLK and the vertical blanking area V · BLK. The first half is an odd field and the second half is an even field.

In the present invention, basically, in order to enable transmission of a digital video signal for one frame through the ATM2 line, the D1 signal information amount (data amount) for one frame
For each D1 signal after dividing
Each of them compresses data so that they can be transmitted by ATM1 line.

As a method of separating the data amount of the D1 signal into 1/2, the video signal itself before separation is directly set to 1
It is also possible to divide into / 2, or it is possible to separate into a luminance signal component Y and a color difference signal component C (Cr and Cb). This example is the former example.

A data signal (digital audio signal or other data signal) may be inserted in a signal other than the video signal. The data signals have low correlation. Therefore, it is difficult to compress these data signals unless the nature of the signals is understood, and it is better to avoid them as much as possible. On the other hand, since the video signal has a strong correlation and its nature is known,
This can be compressed and restored to the original video signal without any deterioration of the signal.

Therefore, in the present invention, the signal components other than the video signal are transmitted as full bits, and only the video signal is compressed.

Therefore, in the present invention, the data amount of the D1 signal is halved and the number of pixels per ATM1 line is halved.
To The frame signal per ATM line when it is reduced to 1/2 has a frame configuration as shown in FIG. 1A.

The data of the horizontal blanking area HBLK and the vertical blanking area (19 × 2 lines) VBLK is transmitted in full bits with the 10-bit structure as it is.
In the ATM line, all signals are converted into cells and transmitted, and each cell is configured in units of bytes (8 bits). Therefore, signals other than video signals are converted from 10 bits to 8 bits. .

This conversion process is performed using a memory. For example, as shown in FIG. 3, a memory having 10 bits in the horizontal direction and 8 bits in the vertical direction is prepared, and the 10-bit input is sequentially stored in the horizontal direction in bit units. After the input data is stored in all areas, This time, the data is read from the vertical direction. Then, the output data has an 8-bit structure. The (10-8) conversion can be performed by such a simple process.

Next, the compression processing of the video signal component will be described. As is well known, since one pixel of the D1 signal is digitized with 10 bits, the frame configuration (10-byte unit) of FIG. 1A is converted into an 8-bit unit cell configuration as shown in FIG. 1B.

One cell is made up of 48 bytes, and about 3 bytes are taken as a control / address signal for reconstructing a video signal frame, and transmission cells = 4.
If the number of pixels in FIG. 1A is converted into cells with 5 bytes, the number of cells per line in the vertical blanking period is {(138 + 720) bytes × 10 bits} / (8 bits × 45 bytes) = 23.8
= 24 (cells). The number of cells per line in the horizontal blanking period is (138 bytes x 10 bits) / (8 bits x 45 bytes) = 3.8 = 4 (cells), so the data area including the horizontal and vertical blanking periods The number of cells per frame is 24 cells × 19 lines × 2 + 4 cells × (244 + 243) lines = 2860 cells / frame. Similarly, the number of cells per line in the video signal section is (720 bytes x 10 bits) / (8 bits x 45 bytes) = 20 (cells), so the number of cells per frame of the video signal is , 20 cells x (244 + 243) lines = 9740 cells / frame.

On the other hand, when the number of cells that can be assigned to the active area per ATM line is calculated in the AAL5 layer, it is 155.52 Mbps x (2 / 59.94) Hz x (1/8 bit) x (1/53 byte) = 12238.6 It becomes a cell. Since the ATM line signal is a transmission unit with a header of 1 cell for every 26 cells, it is 12238.9 / 27 = 453.28 = 453 transmission units. The actual number of ATM cells included in the 453 transmission unit is 453 × 26 = 11778 cells.

Although the CPCS sublayer includes 1366 cells including the control signal, the number of cells assigned as user information that can be transmitted per one stage of the CPCS sublayer is about 1532 cells because it is 26 cells as described above. Therefore, when the number of CPCS sublayers (integer) for transmitting one frame signal is calculated, it is 11778/1352 = 8.71 = 9.

Since a trailer of 1 cell is added to each CPCS sublayer, the video signal is actually calculated from the number of trailers (total 9 cells) and the total number of cells in the blanking period per frame (2860 cells) described above. The number of cells per frame that can be allocated as (active area) is 11778 cells-9 cells-2380 cells = 8909 cells / frame.

On the other hand, since the total number of video signal cells per frame to be allocated per ATM line is 9740 cells as described above, as a practical problem, 9740-8909 = 831 cells are insufficient. Therefore, the video signal is compressed so that it can be accommodated in 8909 cells. The compression rate is 8909/9740 = 0.915 × 100 = 91.5%. In this way, 9 ATM video signals per ATM line
When compressed to 1.5%, all data of the D1 signal can be transmitted using the ATM2 line.

FIG. 4 shows the case of applying to the D1 signal of the 625/50 system. The frame structure of the D1 signal per ATM1 line (actual 1/2 data amount) is shown in FIG. 4A. If this is made into cells in the same manner as in FIG. 1B, it becomes as shown in FIG. 4B. Here, the number of cells per line in the vertical blanking period is {(144 + 720) bytes × 10 bits} / (8 bits × 45 bytes) = 24 (cells). Since the number of cells per line in the horizontal blanking period is (144 bytes x 10 bits) / (8 bits x 45 bytes) = 4 (cells), the number of cells per frame in all horizontal and vertical blanking periods The number is 24 cells x (24 + 25) lines + 4 cells x (288 + 288) lines = 3480 cells / frame. Similarly, the number of cells per line in the video signal section is (720 bytes x 10 bits) / (8 bits x 45 bytes) = 20 (cells), so the number of cells per frame of the video signal is , 20 cells x (288 + 288) lines = 11520 cells / frame.

On the other hand, when the number of cells that can be assigned to the active area per ATM line is calculated in the AAL5 layer, it is 155.52 Mbps × 25 Hz × (1/8 bit) × (1/53 byte) = 14671.7 cells. Since the ATM line signal is a transmission unit with a header of 1 cell for every 26 cells, 14671.7 / 27 = 543.4 = 543 transmission units. The actual number of ATM cells included in the 543 transmission unit is 543 × 26 = 14118 cells. Since the CPCS sublayer has 1532 cells as described in the D1 signal processing, the number of constituent stages of the CPCS sublayer for transmitting one frame signal is calculated as 14118/1352 = 10.44 = 11.

Since a trailer of 1 cell is added to each CPCS sublayer, the video signal is actually calculated from the number of trailers (11 cells in total) and the total number of cells in the blanking period per frame (3480 cells) described above. The number of cells per frame that can be allocated as follows is 14118 cells-11 cells-3480 cells = 10627 cells / frame.

However, since the total number of video signal cells per frame to be allocated per ATM line is 11520 cells as described above, as a practical problem, 11520-10627 = 893 cells are insufficient. Therefore, the video signal is compressed so that it can be accommodated in 10627 cells. The compression rate is 10627/11520 = 0.922 × 100 = 92.2%. In this way, 9 ATM video signals per ATM line
625 using ATM2 line when compressed to 2.2%
All data of the D1 signal of the / 50 system can be transmitted.

In the above description, the video signal is compressed so that the D1 signal can be transmitted using the ATM2 line.
It is also possible to accommodate the D1 signal in the ATM1 line. For example, the number of cells that can be transmitted in one frame for the 525/60 system D1 signal is 8909-2380 = 6049 cells / frame because the number of cells in the blanking signal period is 2860 cells. Since 9740 x 2 = 19480 cells, the compression rate is 6049/19480 = 0.311 x 100 = 31.1%. That is, the 525/60 system D1 signal is a video signal of 31.
By compressing by 1% or more, it becomes possible to transmit on ATM1 line.

In the 625/50 system D1 signal, the number of cells for blanking is 3480, and the maximum number of transmission cells is 10.
Since there are 627 cells, the number of cells that can be used as a video signal is 10627−3480 = 7147 cells / frame, and since the number of video signal cells is 11520, the compression rate is 7147 / (10520 × 2) = 0.310. × 100 = 31.0%, and the 625/50 system D1 signal is 3 video signals.
By compressing 1.0% or more, it can be transmitted by ATM1 line.

When the D2 signal which is the composite digital video signal is transmitted by using the ATM1 line, it becomes as shown in FIG. Fig. 5 shows the case of applying to the D2 signal of 525/60 system, and the number of cells in the blanking period is (26 cells × 19 lines × 2) + 4 × (244 + 243) lines = 2936 cells / frame Active area video The number of cells in the signal period is 22 cells x (244 + 243) lines = 10714 cells / frame.

Since the number of cells per ATM line is 11778 as described above, the number of cells that can be assigned to the active area per ATM line is 11778-9, assuming that the CPCS sublayer is used in 9 stages for transmission. -2936 = 8883 cells / frame, so 8883/10717 = 0.824 x 100 = 82.4%.

Therefore, if the video signal is compressed to 82.4% or more, the D2 signal of the 525/60 system 4: 2: 2 system can be transmitted using the ATM1 line.

In the case of 625/50 system D2 signal, FIG.
As shown in, the number of cells occupied by the data area is 5024.
The number of cells occupied by the active area is 15
Since it is 552 cells, the CPCS sublayer is set to 11
The number of cells that can be assigned to the active area per ATM line for transmission by using multiple stages is 14118-11-5024 = 9083 cells / frame, so 9083/15552 = 0.584 × 100 = 58.4%.

Therefore, if the video signal is compressed to 58.4% or more, the D2 signal of the 625/50 system 4: 2: 2 system can be transmitted through the ATM1 line.

Then, an AT for realizing the above-mentioned signal processing
An example of the M line signal processing device is shown in FIG. This figure shows a case where the present invention is applied to the D1 signal of the 525/60 system shown in FIG.

The terminal 12 is supplied with a digitized 10-bit D1 signal (4: 2: 2 signal), which is halved by the separation circuit 14 to receive D1 of one frame.
The data is separated so that the data amount of the signal becomes 1/2. Each of the separated D1 signals D1a and D1b is a pair of ATs.
It is supplied to the M line signal generation means 20 and 40. Since these generating means 20 and 40 have the same configuration, only one of them will be described.

Explaining the processing system of the D1 signal D1a, it is first supplied to the signal separating means 22 and separated into a video signal (luminance signal component Y and color difference signal component C) and a signal in the blanking period. As is well known, in the D1 signal, a TRS signal (Timing R
eference Signal) is inserted, and x is inserted in the last byte.
The signal yz is inserted.

In the embodiment, the active area (Y and C) and other areas (horizontal blanking and vertical blanking areas) are separated by judging the xyz signal.

The separated video signal is data compression means 2
4 and the predetermined data compression of 91.5% or more in this case is performed, and then the data is output in units of 8 bits which is a unit of the ATM cell. Therefore, in compression, it is output as pseudo 8-bit data.

Signals in the horizontal and vertical blanking periods, which are signal components other than video signals, are converted from 10 bits to 8 bits in the bit conversion means 26. A specific example of this bit conversion processing has already been described with reference to FIG.

The 8-bit video signal and the signal in the blanking period are supplied to the buffer memory 28, and a control signal necessary for reframe of a predetermined video signal is added to the buffer memory 28. By reading, it is made into cells and output. For the data shortage when converting to 48 bytes, a corresponding control signal is added and "0" data is inserted.

A plurality of cell signals read out in units of 48 bytes are supplied to the CPCS conversion means 30 configured as an ATM layer section, where a trailer is added and an ATM cell conversion process (AAL5 layer) is performed. 53 bytes), and processing such as addition of a transmission header is performed at a rate of one for every 26 ATM cells. The output is the ATM line signal ATMa.

In the other ATM line signal generating means 40, the remaining D1 signal D1b which has been divided into halves is subjected to the same conversion processing as described above to form an ATM line signal ATMb. Line signal AT
Ma and ATMb are supplied to the ATM line 50. All of these series of processes are executed under the intervention of a system controller (not shown).

FIG. 8 shows an ATM input from the ATM line 50.
A specific example of the video signal converter 55 for inversely converting the line signals ATMa and ATMb into D1 signals will be shown.

The ATM line signal ATMa is supplied to the CPCS inverse conversion means 62 constituting the first video signal conversion means 60 and separated into CPCS payload units, and then the cell separation means 64 converts it into a control signal contained in the cell signal. Based on this, the cell signal in 48-byte units is separated into the video signal component and the other signal component (BLK). At this time, the order of the cells may be reversed, so that the internal memory is used to rearrange the cells in the normal order and output.

Among them, the cell signal relating to the video signal is converted into a byte-unit data signal in the data converting means 66, and then (8-10) in the converting means 68 (8
-10) The converted data is expanded.

The cell signal relating to the signal in the blanking period is converted into cell data by the cell data conversion means 70, and then inversely converted into 10-bit data by the bit conversion means 72. This conversion process is the reverse of FIG. 3, and is a process for reading 8-bit data input in the vertical direction from the horizontal direction and converting it into 10-bit data (full bit data).

In each case, the video signal restored to 10 bits and the signal in the blanking period are further supplied to the buffer memory 74 and output in the state of being rearranged to the original frame signal so that the frame structure can be formed. The output frame signal is the D1 signal D1a.

The second video signal converting means 80 also performs the same processing to restore the remaining D1 signal D1b, and these D1 signals D1a and D1b are multiplexed by the multiplexing circuit 76 to restore the original D1 signal. It All of these series of processes are executed under the intervention of a system controller (not shown).

With respect to the D1 signal and the D2 signal of the 625/50 system, it is easy to generate an ATM line signal by the signal processing system as shown in FIG. 7 or 8 and to reproduce the original digital video signal from the ATM line signal. Can understand.

[0062]

As described above, according to the ATM line signal generating method of the present invention, the video signal is compressed and the ATM line signal is generated.
It can be accommodated in two lines or one ATM line.

According to this, only the video signal is compressed, and other signals (horizontal and vertical blanking period signals) are simply subjected to bit conversion processing to frame the ATM2 line or ATM1 line. Can accommodate signals. The video signal has a strong correlation, and even if it is subjected to the compression process, the visually noticeable deterioration of the image quality does not occur, so that it has a feature that it can be digitally transmitted without substantially impairing the quality of the digital video signal.

Further, since the digital video signal can be accommodated in the ATM2 line, the ATM line can be used efficiently, and the video signal can be bundled even in the case of bundling the video signal to the upper line of the transmission hierarchy. It has a feature that ATM lines for transmission can be multiplexed without waste.

Therefore, the present invention is extremely suitable when applied to a transmission system for transmitting a so-called D1 type or D2 type digital video signal using an ATM line.

[Brief description of drawings]

FIG. 1 is an AT of a 525/60 system D1 signal according to the present invention.
It is a figure which shows the example of a frame structure per M1 line.

FIG. 2 is a diagram showing a frame configuration example of a 525/60 system D1 signal.

FIG. 3 is a diagram illustrating an example of bit conversion processing.

FIG. 4 is an AT of 625/50 system D1 signal according to the present invention.
It is a figure which shows the example of a frame structure per M1 line.

FIG. 5: AT of 525/60 system D2 signal according to the present invention
It is a figure which shows the example of a frame structure per M line.

FIG. 6 is an AT of 625/60 system D2 signal according to the present invention.
It is a figure which shows the example of a frame structure per M line.

FIG. 7 is a system diagram showing an example of an ATM line signal processing device.

FIG. 8 is a system diagram showing an example of an ATM line signal inverse processing device.

9 is a diagram showing a configuration example of ATM adaptation layer type 5. FIG.

[Explanation of symbols]

 20, 40 ATM line signal generation means 24 Video signal compression means 26 Bit conversion means 30 CPCS conversion processing means 60, 80 Video signal conversion means 62 CPCS inverse conversion means 64 Cell separation means 68 (8-10) conversion means 72 bit conversion means

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Claims (5)

[Claims] 1. A digital video signal is transmitted through an ATM line A.
When transmitting using the TM adaptation layer protocol, the signal components other than the video signal components of the digital video signal are transmitted as full bits, and are allocated to the remaining CPCS payload occupied by this full bit transmission. The video signal is compressed so that the video signal component can be accommodated within the number of transmission cells, and the compressed video signal component and the signal component other than the video signal are converted into the ATM adaptation layer data format. A method for generating an ATM line signal, which is characterized in that the ATM line signal is generated. 2. The ATM line signal generating method according to claim 1, wherein the digital video signal is a component signal or a composite signal. 3. When the component signal is used as the digital video signal, the luminance signal component and the color difference signal component are separated and then compression processing is performed on each of them. 1. The ATM line signal generation method described in 1. 4. The ATM line signal generation method according to claim 1, wherein a type 5 adaptation layer to which the smallest number of control signals are added is used as the ATM adaptation layer. 5. When transmitting a digital video signal using an ATM line, a compression means for compressing a video signal component of the digital video signal to a predetermined ratio, and a signal component other than the video signal component being an ATM line signal. And bit line converting means for performing bit conversion for shortening the bit length so as to conform to the above, and ATM line signal converting means for converting these signal components into an ATM adaptation layer data format to form an ATM line signal. An ATM line signal processing device characterized in that