JPH08221703A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE: To obtain such a digital signal reproducing device that the adjustment of a circuit is easy and the stable operation is secured. CONSTITUTION: The output of an AGC circuit 5 is supplied to both of an A/D converter 6 and a QFB circuit 7. In the QFB circuit 7, a rectangular wave is produced by a signal from the circuit 5 and supplied to a PLL circuit 8, wherein a clock for the circuit 6 is produced from this rectangular wave. Reference voltages of the circuit 7 and circuit 6 are supplied from a reference voltage source 11 which is incorporated in an IC including the circuit 7. Since a feedback gain of the circuit 7 is controlled by the supplied reference voltage, the circuit 7 is operatable without adjustment. The reference voltage of the circuit 6 is also supplied from the voltage source 11, so the adjustment is unrequired. Consequently, the adjustment of the whole device is completed by only supplying the signal to the circuit 5 and adjusting it while monitoring the output of the circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing a digital video signal, a digital audio signal, etc. recorded on a recording medium, and more particularly, a partial response level 4
The present invention relates to a digital signal reproducing device for reproducing a digital signal recorded on a magnetic tape by an encoding method utilizing the above.

[0002]

2. Description of the Related Art At present, a digital VCR (video cassette recorder) for recording digital video signals, digital audio signals, etc. on a magnetic tape has been proposed. At this time, the digital signal is appropriately encoded, modulated, and recorded. When reproducing a signal recorded in this way, a method called partial response is used as one means for reducing waveform distortion. This is to perform efficient data transmission by allowing inter-symbol interference, that is, waveforms of data at different times, to interfere with the waveform on the receiving side when digitally transmitting data.

This partial response is classified into levels 1 to 5 according to how intersymbol interference is applied.
The level 4 system is mainly used for recording on magnetic tapes and magnetic disks. This is called partial response level 4 (PR4). In this PR4 system, data is ternary detected as (-1, 0, +1) during reproduction.

FIG. 3 shows an example of the structure of a magnetic tape reproducing apparatus using the PR4 system. The signal recorded on the magnetic tape 100 is reproduced by the head 101 and supplied to the integral equalizer 103 via the amplifier 102. Generally, the characteristics of signals are differentiated when they are recorded on a magnetic tape. Therefore, since the reproduced signal also has a differential characteristic and is cut off in the low frequency range, the differential characteristic is compensated by the integral equalizer 103. The reproduced signal whose differential characteristic is compensated is supplied to the AGC circuit 104 and controlled so that the amplitude becomes constant. The output of this AGC circuit 104 is A /
The D converter 105 and the quantized feedback equalizer (hereinafter, Q
(Referred to as FB circuit) 106.

The reproduced signal supplied from the AGC circuit 104 to the QFB circuit 106 is low-frequency-equalized into a rectangular wave.
Details of the operation of the QFB circuit 106 will be described later. The signal made into a rectangular wave by this QFB circuit 106 is P
It is supplied to the LL circuit 107 and the clock is extracted. This clock is supplied to the A / D converter 105, and A / D conversion is performed based on this clock.

On the other hand, the reproduction signal supplied from the AGC circuit 104 to the A / D converter 105 is A / D converted and quantized based on the clock supplied from the PLL circuit 107 described above. This quantized reproduction signal is 1-D
² is supplied to the data detection circuit 109 via the circuit 108,
Three values are detected such as (-1, 0, +1). Three
This reproduced signal whose value has been detected is sent to a subsequent stage (not shown) and subjected to decoding processing and the like.

In the A / D converter 105, the reference voltage source 110 is connected to the A / D converter reference voltage regulator 11
A reference voltage is supplied via 1, which causes A /
The maximum output level of the D converter 105 is controlled.
For example, if the A / D converter 105 has an 8-bit A / D
In the case of D conversion, if the reference voltage is 1 [V], this A
When the input signal of 1 [V] is supplied to the / D converter 105, the signal of the level (255) is output.

FIG. 4 shows an example of the configuration of the QFB circuit 106 described above. The QFB circuit 106 removes the influence of low-frequency cutoff so that an accurate clock is extracted from the signal whose differential characteristic is compensated by the integral equalizer 103 described above,
This is a circuit for making a rectangular wave. Here, this QFB
Waveform distortion is generated from the signal supplied to the circuit 106, and this is extracted and added to the original signal to restore the waveform.

The signal whose differential characteristic is compensated is input terminal 20.
0 is supplied to the high pass filter 201. The signal supplied to the high-pass filter 201 is cut in the low frequency range and supplied to the adder 202.
An example of the waveform of the signal at point A in FIG. 4 at this time is shown in FIG. 5A. In this way, the signal is high pass filter 2
Waveform distortion is generated by passing through 01.

The output of the adder 202 is the slicer 20.
3 is supplied. A reference voltage is supplied to the slicer 203 (not shown), and the amplitude of the output signal is limited according to the reference voltage and binarized. The output of this slicer 203 is supplied to the output terminal 204, and
It is also supplied to the low-pass filter 205.

The high frequency band of this signal supplied to the low pass filter 205 is cut and the signal is supplied to the adder 202.
The waveform at point B in FIG. 4 at this time is shown in FIG. 5B. In this way, the signal whose waveform distortion has been generated by the high-pass filter 201 is passed through the low-pass filter 205, whereby the waveform distortion is extracted.

The output from the high-pass filter 201 is also supplied to the adder 202, as described above. The output from the low-pass filter 205 and the output from the high-pass filter 201 are added by the adder 202. This restores the waveform. This restored signal is output to the output terminal 20 via the slicer 203.
4 is supplied and output.

As described above, in the QFB circuit 106, the adder 202, the slicer 203, and the low-pass filter 205 form a positive feedback circuit. In this positive feedback circuit, the DC component is positively fed back 100%. Therefore, if the amplitude b (FIG. 5A) of the feedback signal at the point B does not satisfy the relationship shown in the equation (1) with respect to the amplitude a (FIG. 5A) of the input signal at the point A in FIG. , Will oscillate. b <a / 2 (1)

In order to satisfy this relationship, this QFB
In the circuit 106, the slicer 203 controls the amplitude b. As described above, this amplitude control is performed based on the reference voltage supplied to the slicer 203. Therefore, this reference voltage needs to be strictly adjusted.

Normally, the circuit as shown in FIG. 3 is composed of several ICs or LSIs. In this example, the integration equalizer 103 and the AGC circuit 104 are ICs.
300, A / D converter 105, 1-D ² circuit 10
8, the data detection circuit 109, and the reference voltage source 110 are the IC 301, and the QFB circuit 106 is the IC 302.
And each is configured.

[0016]

As described above, the QF
Since the feedback gain of the B circuit 106 needs to be controlled, the level adjustment of the slicer 203 is necessary. A
Although the reference voltage source 110 is built in the / D converter 105, it usually has a variation of 10 to 20%. However, the dispersion of the digital signal reproducing apparatus as a whole must be suppressed to several percent. Therefore, it is also necessary to adjust the level of the A / D converter 105. Further, since it is also necessary to adjust the level of the input signal supplied to the A / D converter 105 and the QFB circuit 106, the AGC circuit 104
It is also necessary to adjust the output level of.

Here, a method of adjusting these circuits will be described. As described above, this adjustment is performed by the QFB circuit 1
06, A / D converter 105, and AGC circuit 10
It is required for each of the three circuits of No. 4. In order to determine the output level of AGC circuit 104, the input / output characteristics of A / D converter 105 and QFB circuit 106 must be determined. Further, in order to determine the input / output characteristics of the A / D converter 105, the A / D converter 105 itself needs to operate with a correct clock, and for that reason, a square wave is normally output from the QFB circuit 106. Must have been Furthermore, the QFB circuit 1
In order for the rectangular wave to be normally output from 06, the level of the input signal supplied must also be controlled. For that purpose, the output level of the AGC circuit 104 is adjusted as described above. There is a need.

In this example, these three circuits are:
IC300, IC301, and IC302 are included in separate ICs. Based on this, a specific example of adjustment will be described. First, the QFB circuit 106
Is adjusted. IC 302 including the QFB circuit 106
The reference signal for adjustment is input to the input terminal of. Then, the output waveform of the QFB circuit 106 is monitored, and the feedback gain of the QFB circuit 106, that is, the output level of the slicer 203 is adjusted so that the output waveform becomes a rectangular wave.

Next, the A / D converter 105 is adjusted. A reference signal for adjustment is input to the input terminal of the IC 301 including the A / D converter 105. Then, the output level of the A / D converter 105 is monitored, and the voltage value of the reference voltage source 110 is adjusted by the A / D converter reference voltage adjuster 111 so that this output level becomes a predetermined value.

Finally, the AGC circuit 104 is adjusted.
A reference signal for adjustment is input to the input terminal of the IC 300 including the AGC circuit 104. And AGC
The output waveform of the circuit 104 is monitored, and the Pea of this waveform is monitored.
AG so that the value of k to Peak becomes a predetermined value.
The output amplitude of the C circuit 104 is adjusted.

As described above, since these three circuits are related to each other, it is necessary to input the reference signal to each of them independently and adjust them separately, which is very troublesome to adjust. .

Therefore, an object of the present invention is to provide a digital signal reproducing apparatus in which circuit adjustment is simple and stable operation is guaranteed.

[0023]

In order to solve the above-mentioned problems, the present invention is configured in a first integrated circuit, which comprises an AG
An AGC circuit with adjustable C gain, an A / D converter configured in a second integrated circuit, a quantization feedback equalizer configured in a third integrated circuit, and a third integrated circuit And a reference voltage source, and the reference voltage source supplies a reference voltage to the A / D converter and the quantization feedback equalizer.

In order to solve the above-mentioned problems, the present invention has a quantization feedback equalizer having a high-pass filter, an adder, an amplitude limiter and a low-pass filter, and the amplitude limiter is a reference voltage source. The digital signal reproducing device is characterized in that it is controlled by a supplied reference voltage.

[0025]

According to the present invention, since the reference voltage of the A / D converter and the quantization feedback equalizer is supplied from the reference voltage source configured in the third integrated circuit, the A / D converter and the quantization feedback are provided. There is no need to adjust the reference voltage of the equalizer.

Further, according to the present invention, since the amplitude limiter of the quantization feedback equalizer is controlled by the reference voltage supplied from the reference voltage source, the feedback amount of the quantization feedback equalizer is set to the reference voltage. It can be decided by setting.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the configuration of a digital signal reproducing apparatus using the PR4 system according to this embodiment. In this embodiment, an IC including a QFB circuit
Is provided with a reference voltage source, and the QFB circuit and the A / D converter are controlled by the reference voltage supplied from the reference voltage source.

The head 2 is for reproducing the signal recorded on the magnetic tape 1, and the output of the head 2 is supplied to the reproducing amplifier 3. The output of the reproduction amplifier 3 is supplied to the integral equalizer 4, and the output of the integral equalizer 4 is AGC.
It is supplied to the circuit 5. The output of the AGC circuit 5 is supplied to both the signal input terminal of the A / D converter 6 and the QFB circuit 7. The output of the QFB circuit 7 is supplied to the PLL circuit 8, and the output of the PLL circuit 8 is supplied to the clock input terminal of the A / D converter 6. Output of A / D converter 6 is 1
It is supplied to the -D ² circuit 9, the output of the 1-D ² circuit 9 is supplied to the data detection circuit 10, and the output of the data detection circuit 10 is output to a decoding circuit (not shown) in the subsequent stage.
Further, the output of the reference voltage source 11 is supplied to the A / D converter 6 and the QFB circuit 7.

In this example, the integral equalizer 4 and the AGC circuit 5 are provided in the IC 30, the A / D converter 6,
1-D ² circuit 9 and data detection circuit 10 are IC 31
In addition, the QFB circuit 7 and the reference voltage source 11 are
2 is included in each.

The signal recorded on the magnetic tape 1 is reproduced by the head 2 and is passed through the amplifier 3 to the integral equalizer 4
Is supplied to. The reproduction signal, whose characteristics are differentiated and cut off in the low range when recorded on the magnetic tape, is compensated for the differential characteristics by the integral equalizer 4 and supplied to the AGC circuit 5. The reproduction signal supplied to the AGC circuit 5 is controlled so that the amplitude becomes constant, and is supplied to both the A / D converter 6 and the QFB circuit (quantization feedback equalizer) 7.

The reproduction signal supplied from the AGC circuit 5 to the QFB circuit 7 is low-frequency equalized into a rectangular wave. This QF
The rectangular wave signal in the B circuit 7 is supplied to the PLL circuit 8 and the clock is extracted. This clock is A / D
The clock is supplied to the converter 6, and a clock for A / D conversion is generated based on this.

On the other hand, the reproduction signal supplied from the AGC circuit 5 to the A / D converter 6 is A / D converted and quantized based on the clock supplied from the PLL circuit 8 described above. In this case, in the PR4 system, the low-frequency characteristic is not so important, so in this example, waveform shaping by the QFB circuit or the like is not performed. The quantized reproduction signal is supplied to the data detection circuit 10 via the 1-D ² circuit 9 and is ternary detected such as (-1, 0, +1). This reproduction signal, which has been detected in three values, is sent to a subsequent stage (not shown) and subjected to decoding processing and the like.

As described above, in this embodiment, the reference voltage source 1 is added to the IC 32 including the QFB circuit 7.
1 is provided. A reference voltage is supplied from the reference voltage source 11 to the QFB circuit 7, and the feedback level in the QFB circuit 7 is controlled. In addition, this reference voltage source 11
From the above, the reference voltage is also supplied to the A / D converter 6, and thereby the output level of the A / D converter 6 is controlled.

FIG. 2 shows the QFB circuit 7 in this embodiment.
An example of the configuration will be shown. This is because the reference voltage source 11 has the same I
The operation and configuration are exactly the same as those of the conventional QFB circuit 106 described above, except that it is provided in C32.

That is, the input terminal 20 to which the reproduced signal is input is connected to the high pass filter 21, and the output of the high pass filter 21 is supplied to one input terminal of the adder 22. The output of the low-pass filter 24 is supplied to the other input terminal of the adder 22. The output of the adder 22 is supplied to the slicer 23, the output of the slicer 23 is supplied to the output end 25, and the low-pass filter 2
4 is also supplied. Further, the reference voltage output of the reference voltage source 11 is supplied to the reference voltage input terminal of the slicer 23.

The signal whose differential characteristic is compensated is input terminal 20.
Are supplied to the high pass filter 21. The signal supplied to the high pass filter 21 is subjected to waveform distortion and supplied to the adder 22. The output of the adder 22 is supplied to the slicer 23. A reference voltage is supplied from the reference voltage source 11 to the slicer 23, and the amplitude of the output signal is limited to a predetermined value according to the reference voltage and binarized.

The output of this slicer 23 is output to the output terminal 24.
And is also supplied to the low-pass filter 25. This signal supplied to the low pass filter 25 is
The waveform distortion is extracted and supplied to the adder 22. An output generated by the high-pass filter 21 to cause waveform distortion is also supplied to the adder 22. The output from the low-pass filter 25 and the output from the high-pass filter 21 are added by the adder 22 to restore the waveform,
It is supplied to the output terminal 24 through the slicer 23 and output.

Next, a method of adjusting the digital signal reproducing circuit having such a configuration will be described. QFB circuit 7
The relationship between the waveforms at the points A and B needs to satisfy the relationship of Expression (1) as described above. However, if the level of the signal input to the circuit is a certain value or more, the clock can be output. That is, there is no problem as long as the value of a in the formula (1) is large.

Therefore, the QFB circuit 7 is designed so that the amplitude of the output from the slicer 23 corresponds to the reference voltage supplied from the reference voltage source 11, for example, in a proportional relationship. A signal is supplied to the QFB circuit 7 from the AGC circuit 5. As will be described later, a reference signal is supplied to the AGC circuit 5 during adjustment, and a signal having a certain level or higher is output. Therefore, the reference voltage source 11 is set in advance so that the reference voltage that allows the QFB circuit 7 to operate sufficiently with respect to this expected input level is output. By doing so, the QFB circuit 7 can be operated without any special adjustment.

As described above, since the QFB circuit 7 can be operated without adjustment, the A / D converter 6 can be operated from the beginning accordingly. Therefore, the actual adjustment method is as follows. First, by supplying the reference signal to the input terminal of the IC 30 including the AGC circuit 5, the reference signal is supplied to the AGC circuit 5 as described above. The amplitude of this input reference signal is controlled by the AGC circuit 5, and the A / D
A via the input terminal of the IC 31 including the converter 6
It is supplied to the / D converter 6.

The output of the A / D converter 6 is monitored,
The output amplitude of the AGC circuit 5 is adjusted so that this output has a predetermined value. For example, this A / D converter 6 has 8
A / D conversion is performed by bits, and when an input voltage corresponding to a certain reference voltage, for example, 1 [V] is supplied to the A / D converter 6, the A / D converter 6 outputs the maximum output value ( 255), the AGC circuit 5 is adjusted so that the maximum output amplitude of the AGC circuit 5 becomes 1 [V].

In this way, if the reference voltage supplied to the A / D converter 6 is constant, a predetermined output can be obtained. In this example, this reference voltage is
It is fixed because it is supplied from the reference voltage source 11 incorporated in the IC 32 including the QFB circuit 7. Therefore, it is not necessary to even adjust the reference voltage, and a series of adjustments are completed only by adjusting the output amplitude of the AGC circuit 5.

The present invention is not limited to the above-mentioned configuration, and for example, the reference voltage source is the QFB circuit 7
Other configurations can also be implemented as long as the stable reference voltage is collectively supplied to the A / D converter 6. For example, a configuration may be adopted in which a regulator IC or the like is provided externally and is supplied from now on.

The present invention is not limited to use only in a digital signal reproducing device for reproducing digital data recorded on a magnetic tape. That is, a configuration in which a rectangular wave is generated by the QFB circuit from a signal whose amplitude is limited by the AGC circuit, thereby generating a clock for A / D converting the signal supplied from the AGC circuit by the A / D converter. Any device having can be used.

[0045]

As described above, according to the present invention, the QFB circuit is designed so that the amplitude of the output from the slicer in its configuration corresponds to the reference voltage supplied from the reference voltage source. Therefore, by setting this reference voltage to a predetermined value in advance, the QFB circuit circuit can be operated without adjustment. Therefore, from the beginning
It is possible to operate the / D converter. Also, A /
The reference voltage supplied to the D converter is supplied from the reference voltage source built in the IC including the QFB circuit. Therefore, it is not necessary for the A / D converter to independently adjust the reference voltage.

Therefore, there is an effect that the number of adjustment points, which conventionally required three points, is reduced to one, and the number of man-hours required for the adjustment is reduced.

Also, regarding the adjustment of one place, A /
Since the adjustment can be performed while monitoring the digitized data by the D converter, the adjustment can be performed quickly, accurately and easily.

Further, there is an effect that the manufacturing cost can be suppressed by the above two effects.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a digital data reproducing device according to the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a QFB circuit according to the present invention.

FIG. 3 is a block diagram showing an example of a configuration of a digital data reproducing device according to a conventional technique.

FIG. 4 is a block diagram showing an example of a configuration of a QFB circuit according to a conventional technique.

FIG. 5 is a schematic diagram for explaining a signal waveform in the operation of the QFB circuit.

[Explanation of symbols]

 5 AGC circuit 6 A / D converter 7 QFB circuit 11 Reference voltage source 21 High-pass filter 23 Slicer 24 Low-pass filter

Claims (2)

[Claims] 1. A digital signal reproducing apparatus for reproducing a digital signal recorded on a magnetic tape, comprising an AGC circuit which is configured in a first integrated circuit and has an adjustable AGC gain, and a second integrated circuit. The A / D converter, a quantization feedback equalizer configured in a third integrated circuit, and a reference voltage source configured in the third integrated circuit, wherein the reference voltage source is the A digital signal reproducing device characterized in that a reference voltage is supplied to an A / D converter and the quantization feedback equalizer. 2. The digital signal reproducing apparatus according to claim 1, wherein the quantization feedback equalizer has a high-pass filter, an adder, an amplitude limiter, and a low-pass filter, and the amplitude limiter has the reference voltage. A digital signal reproducing device characterized in that it is controlled by the reference voltage supplied from a source.