JPH08236774A - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce the leak current at the time of OFF without lowering the ON current. [Structure] Substrate 1 of source region 7 and drain region 7
Since the high resistance layer 6 formed on the side has an insulating function, the leakage current with respect to the source-drain voltage becomes low.
The high resistance layer 6 for reducing the leak current is preferably formed not only on the substrate 1 side of the source region 7 and the drain region 7 but also on the substrate 1 side of the channel region 2a. With this, the leak current with respect to the source-drain voltage can be further reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor using a polycrystalline silicon thin film and a manufacturing method thereof, and more particularly to a thin film transistor preferably used as a switching element of a liquid crystal display device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, a thin film transistor (hereinafter referred to as TFT) using a semiconductor layer made of a polycrystalline silicon thin film
Are used in a pixel switching element for switching pixels of a liquid crystal display device (hereinafter referred to as an LCD) and a peripheral drive circuit. However, in this polycrystalline silicon TFT, since many trap levels are localized at the crystal grain boundaries of the polycrystalline silicon thin film, a large amount of leak current flows through the trap levels at the time of off. There was a drawback. Especially, when a polycrystalline silicon TFT is used as a pixel switching element of a TFT-LCD, the above-mentioned drawback is serious.

Therefore, in order to overcome this drawback, conventionally, an offset gate structure or an LDD (Lightly) structure is used.
A method of relaxing the electric field concentration at the drain end by adopting a doped drain structure or the like has been proposed (Japanese Patent Publication No. 3-38755 and Japanese Patent Laid-Open No. 5-136418).
issue).

By the way, the leak current when the polycrystalline silicon TFT is off is roughly classified into the following two. The Vg-Id curve of the TFT shown in FIG.
As can be understood from the Vds-Id curve of the TFT shown in (b), when the gate voltage Vg and the drain voltage are low, the ohmic leakage current with respect to the source-drain voltage Vds and the gate voltage Vg and the drain voltage are high. In the case of voltage, it is a non-linear leak current with respect to the source-drain voltage Vds.

The above-mentioned non-linear leakage current can be reduced by providing an offset region between the channel region and the drain region. However, the above ohmic leak current cannot be reduced even if the offset region is provided.
Further, since the ohmic leakage current of 1 increases as the film thickness of the intrinsic semiconductor layer increases, a method of reducing the ohmic leakage current of 1) by thinning the intrinsic semiconductor layer can be considered.

For the above reasons, a TFT is formed by combining a method of thinning an intrinsic semiconductor layer conventionally used as a channel region to about 20 nm to 30 nm and a method of forming an offset region having an offset length of 1 μm or more. Is being done.

[0007]

However, when the polycrystalline silicon thin film is formed at a low temperature, if the intrinsic semiconductor layer used as the channel region is thinly formed, the quality of the polycrystalline silicon film deteriorates. Therefore, although the ohmic leakage current with respect to the source-drain voltage can be reduced by thinning the intrinsic semiconductor layer, the gate voltage and the drain voltage at which the nonlinear leakage current appears are reduced. In order to prevent this, it is necessary to lengthen the offset length, and as a result, there is a problem that the on-current becomes low.

The present invention has been made to solve the problems of the prior art, and provides a thin film transistor capable of reducing the leak current at the time of turning off without lowering the on current and a method of manufacturing the same. With the goal.

[0009]

A thin film transistor of the present invention is a thin film transistor in which a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film and a gate electrode are formed in this order from the substrate side on the substrate. Has a source region and a drain region with a channel region sandwiched therebetween, and a high resistance layer is formed on the substrate side of the source region and the drain region of the semiconductor layer, whereby the above object is achieved.

In the thin film transistor of the present invention, the channel region may be thicker than the source region and the drain region.

The thin film transistor of the present invention is provided on a substrate,
In a thin film transistor in which a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed in this order from the substrate side, the semiconductor layer has a source region and a drain region with a channel region interposed therebetween, and the semiconductor layer A high resistance layer is formed on the entire area of the substrate side, whereby the above object is achieved.

In the thin film transistor of the present invention, the high resistance layer may be composed of a polycrystalline silicon thin film mixed with nitrogen or carbon.

The method of manufacturing a thin film transistor according to the present invention comprises:
In a method of manufacturing a thin film transistor, a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed on a substrate in this order from the substrate side, and the semiconductor layer has a source region and a drain region with a channel region interposed therebetween. A step of forming a semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, and nitrogen or carbon is injected into the semiconductor layer using the gate electrode as a mask, and a high resistance layer is provided in a portion of the semiconductor layer near the substrate. Forming a source region and a drain region in the semiconductor layer portion above the high resistance layer by injecting impurities into the semiconductor layer using the gate electrode as a mask and performing an activation process. The above-mentioned object is achieved by including a process.

In the method of manufacturing a thin film transistor according to the present invention, when nitrogen or carbon is injected into the semiconductor layer, nitrogen or carbon is introduced into the portion where the high resistance layer is formed by 10 ²¹ atto.
ms / cm ³ or more, and nitrogen or carbon is added to the formation region of the source region and the drain region at 10 ²¹ atoms.
It is advisable to carry out so as to mix less than / cm ³ .

The method of manufacturing a thin film transistor of the present invention comprises:
In a method of manufacturing a thin film transistor, a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed on a substrate in this order from the substrate side, and the semiconductor layer has a source region and a drain region with a channel region interposed therebetween. Forming a high resistance layer by forming a polycrystalline silicon thin film mixed with nitrogen or carbon on a substrate or by implanting nitrogen or carbon after forming the polycrystalline silicon thin film; and the high resistance layer. A step of forming the semiconductor layer, the gate insulating film, and the gate electrode in this order on the above,
A step of implanting an impurity into the semiconductor layer using the gate electrode as a mask and activating the impurity to form a source region and a drain region, whereby the above object is achieved.

In the method of manufacturing a thin film transistor according to the present invention, when an impurity is injected into the semiconductor layer to form the source region and the drain region, an insulating film formed on the surface of the gate electrode in addition to the gate electrode. May also be used as a mask.

[0017]

In the present invention, since the high resistance layer formed on the substrate side of the source region and the drain region has an insulating function, the leak current with respect to the source-drain voltage becomes low. The high resistance layer that reduces the leak current is
It is preferable to form not only the source region and the drain region on the substrate side but also the channel region on the substrate side. With this, the leak current with respect to the source-drain voltage can be further reduced. However, like the former,
When the high resistance layer is formed on the substrate side of the source region and the drain region, the channel region is thicker than the source region and the drain region and is in a state of protruding toward the substrate, and therefore flows on the back gate side of the channel region. This also reduces the leakage current for the source-drain voltage because the current is reduced.

As such a high resistance layer, a polycrystalline silicon thin film mixed with nitrogen or carbon can be used.

When the high resistance layer is formed on the substrate side of the source region and the drain region, nitrogen or carbon is injected into the semiconductor layer using the gate electrode as a mask, so that the high resistance layer is self-aligned to the portion of the semiconductor layer near the substrate. Forming a resistive layer,
A source region and a drain region can be formed on the high resistance layer. At this time, implantation is performed so that nitrogen or carbon is mixed in the high resistance layer at 10 ²¹ atoms / cm ³ or more, and nitrogen or carbon is mixed in the source region and the drain region at less than 10 ²¹ atoms / cm ^3. Is desirable. If nitrogen or carbon mixed in the high resistance layer is less than 10 ²¹ atoms / cm ³ , desired high resistance cannot be obtained. On the other hand, when nitrogen or carbon is mixed in the source region and the drain region at 10 ²¹ atoms / cm ³ or more, the transistor does not operate.

When the high resistance layer is formed not only on the substrate side of the source region and the drain region but also on the substrate side of the channel region, after the high resistance layer is formed on the substrate, the channel region and the source are formed. A semiconductor layer that forms the region and the drain region may be formed. In this case, the high resistance layer is formed by forming a polycrystalline silicon thin film (or non-single-crystal silicon) mixed with nitrogen or carbon, or forming a polycrystalline silicon thin film (or non-single-crystal silicon). This can be done later by injecting nitrogen or carbon.

When implanting impurities into the semiconductor layer to form the source region and the drain region, an insulating film formed on the surface of the gate electrode in addition to the gate electrode (for example, used in the following examples) If an anodic oxide film) is also used as a mask, it is possible to form an offset region having a thickness such that the insulating film projects from the gate electrode along the substrate surface. This offset region contributes to the reduction of non-linear leakage current.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 2 (j) shows the TF of this embodiment.
A sectional view of T is shown. In this TFT, a semiconductor layer 2 made of polycrystalline silicon is formed on an insulating substrate 1.
This semiconductor layer 2 is a channel region 2 which is an intrinsic semiconductor layer.
a, a source region 7 and a drain region 7 which are implanted with impurities to form an n ⁺ layer or a p ⁺ layer.
A high resistance layer 6 made of polycrystalline silicon mixed with nitrogen or carbon is formed under the source region 7 and the drain region 7. Channel region 2 of the semiconductor layer 2
A gate insulating film 3 and a gate electrode 4 are formed in this order on a. An anodized film 5 is formed on the surface of the gate electrode 4.

An interlayer insulating film 8 is formed on the substrate in this state so as to cover the anodic oxide film 5 and the like, and on each of the source region 7 and the drain region 7 in the interlayer insulating film 8, the interlayer insulating film 8 is formed. , Source region 7 and drain region 7
Contact holes are formed. A source electrode 9 and a drain electrode 9 are formed on the interlayer insulating film 8 while partially filling the contact holes, and a protective film 10 is further formed thereon.

Next, a method of manufacturing this TFT will be described.

First, as shown in FIG. 1 (a), low pressure CVD (Chemi) is performed on a transparent insulating substrate 1 made of glass or the like.
An amorphous silicon film is formed using a cal vapor deposition device or a plasma CVD device.

Next, this amorphous silicon film is replaced with S
A polycrystalline silicon film is formed by PC (Solid Phase Crystaization) or excimer laser annealing or a combination of SPC and an excimer laser, and processed into a predetermined shape to obtain the semiconductor layer 2. The thickness of the polycrystalline silicon film is preferably about 20 nm to 100 nm in order to obtain good film quality. In the portion of the semiconductor layer 2, the above-mentioned channel region 2, source region 7, drain region 7 and high resistance layer 6 are formed.

Next, as shown in FIG. 1B, a 100 nm-thickness SiO ₂ film is formed to cover the semiconductor layer 2 using, for example, a plasma TEOS device. This SiO ₂ film is to be the gate insulating film 3 by the etching process described later.

Next, an Al film containing Ti is formed on the SiO ₂ film with a film thickness of 3 using a sputtering apparatus, for example.
The gate electrode 4 is formed by forming a film with a thickness of 00 nm and processing it into a predetermined shape.
To form.

Next, as shown in FIG. 1 (c), 3% ammonium tartrate and ethylene glycol were added to the former: the latter =
The gate electrode 4 was prepared by using the mixed solution of 1: 9.
Is anodized to form 0.2 on the surface of the gate electrode 4.
An anodic oxide film 5 having a thickness of less than μm is formed. This anodized film 5
Is the offset length.

Next, as shown in FIG. 1D, the SiO ₂ film is etched into a predetermined shape using the gate electrode 4 and the anodic oxide film 5 as a mask, thereby obtaining the gate insulating film 3.

Next, as shown in FIG. 1E, nitrogen or carbon is implanted into the semiconductor layer 2 by a mass separation type ion implantation apparatus or an ion shower doping apparatus using the gate electrode 4 and the anodic oxide film 5 as a mask. . Thereby, the high resistance layer 6 is formed. In this implantation, nitrogen or carbon is mixed into the high resistance layer 6 at 10 ²¹ atoms / cm ³ or more, and a portion above the high resistance layer 6, that is, a source region 7 and a drain region 7 are formed by a later step. Nitrogen or carbon is 10 ²¹ atom in the semiconductor layer 2 part.
It is desirable to carry out so that less than s / cm ^{3 is} mixed.

Next, as shown in FIG. 1F, the semiconductor layer 2 above the high resistance layer 6 is formed by a mass separation type ion implantation apparatus or an ion shower doping apparatus using the gate electrode 4 and the anodic oxide film 5 as a mask. Phosphorus or boron is implanted into the portion, for example, 10 ²⁰ atoms / cm ³ or more.

Next, thermal annealing or laser annealing is performed to activate the impurity ions. As a result, the source region 7 and the drain region 7 which are n ⁺ layers or p ⁺ layers are formed (see FIG. 2G). Therefore, the semiconductor layer 2 portion below the anodic oxide film 5 becomes an offset region.

Next, as shown in FIG. 2H, a SiO ₂ film having a thickness of 400 nm is formed by using, for example, a plasma TEOS device.
An interlayer insulating film 8 made of is formed.

Next, as shown in FIG. 2I, two contact holes are formed in the interlayer insulating film 8 so as to reach the source region 7 and the drain region 7, and then Ti is formed by using, for example, a sputtering device. An Al film containing Al is formed to a film thickness of 350 nm, and the contact hole is partially filled to form the source electrode 9 and the drain electrode 9.

Finally, as shown in FIG. 2 (j), the TFT
A silicon nitride film is formed on the upper part of the substrate using a plasma CVD apparatus to form a protective film 10.

(Embodiment 2) FIG. 4 (i) shows the TF of this embodiment.
A sectional view of T is shown.

In this TFT, a high resistance layer 12 made of polycrystalline silicon mixed with nitrogen or carbon and a semiconductor layer 13 made of polycrystalline silicon are formed in this order on an insulating substrate 11. The semiconductor layer 13 is a channel region 13a which is an intrinsic semiconductor layer, and n ⁺
It is divided into a source region 17 and a drain region 17 which are layers or p ⁺ layers.

A gate insulating film 14 and a gate electrode 15 are formed in this order on the channel region 13a of the semiconductor layer 13, and the anodic oxide film 1 is formed on the surface of the gate electrode 15.
6 is formed.

An interlayer insulating film 18 is formed on the substrate in this state so as to cover the anodic oxide film 16 and the like, and contact holes reaching the source region 17 and the drain region 17 are formed in the interlayer insulating film 18. There is. A source electrode 19 and a drain electrode 19 are formed on the interlayer insulating film 18 in a state where the contact holes are partially filled, and a protective film 20 is further formed thereon.

Next, a method of manufacturing this TFT will be described.

First, as shown in FIG. 3A, an amorphous silicon film is formed on a transparent insulating substrate 11 made of glass or the like by using a low pressure CVD apparatus or a plasma CVD apparatus. Nitrogen or carbon is implanted into this amorphous silicon film by a mass separation type ion implantation apparatus or an ion shower doping apparatus to form a high resistance layer 12. This implantation is performed on the high resistance layer 12 by adding nitrogen or carbon 10
^It is desirable to carry out so as to mix at least ²¹ atoms / cm ³ .

Next, as shown in FIG. 3B, an amorphous silicon film is formed on the high resistance layer 12 by using a low pressure CVD apparatus or a plasma CVD apparatus. This amorphous silicon film is made into a polycrystalline silicon film by SPC or excimer laser annealing or a combination of SPC and excimer laser, and processed into a predetermined shape to obtain the semiconductor layer 13. The thickness of the polycrystalline silicon film is preferably about 20 nm to 100 nm in order to obtain good film quality.

Next, as shown in FIG. 3C, a 100 nm thick SiO ₂ film is formed on the substrate in this state so as to cover the semiconductor layer 13 using, for example, a plasma TEOS device.
A gate insulating film 14 made of is formed.

Next, an Al film containing Ti is formed to a film thickness of 300 nm on the gate insulating film 14 by using, for example, a sputtering device, and processed into a predetermined shape to form the gate electrode 15.

Next, as shown in FIG. 3D, 3% ammonium tartrate and ethylene glycol were added to the former: the latter =
Using the solution mixed in the ratio of 1: 9, the gate electrode 1
5 is anodized to form an anodized film 16 of 0.2 μm or less on the surface of the gate electrode 15. The thickness of this anodic oxide film 16 becomes the offset length.

Next, as shown in FIG. 3E, the gate insulating film 14 is etched into a predetermined shape by using the gate electrode 15 and the anodic oxide film 16 as a mask.

Next, as shown in FIG. 3F, with the gate electrode 15 and the anodic oxide film 16 as a mask, phosphorus or boron, for example, phosphorus is added to the semiconductor layer 13 by a mass separation type ion implantation apparatus or an ion shower doping apparatus. 10
Inject at least ²⁰ atoms / cm ³ . Then, thermal annealing or laser annealing is performed to activate the impurity ions. As a result, the source region 17 and the drain region 17 which are n ⁺ layers or p ⁺ layers are formed. At this time, the semiconductor layer below the anodic oxide film 16 becomes an offset region (not shown).

Next, as shown in FIG. 4G, a SiO ₂ film having a thickness of 400 nm is formed by using, for example, a plasma TEOS device.
An interlayer insulating film 18 made of is formed.

Next, as shown in FIG. 4 (h), two contact holes are formed in the interlayer insulating film 18 so as to reach the source region 17 and the drain region 17, and then Ti is deposited by using, for example, a sputtering apparatus. An Al film containing Al is formed to a film thickness of 350 nm, and the contact hole is partially filled to form the source electrode 19 and the drain electrode 19.

Finally, as shown in FIG. 4 (i), the TFT
A silicon nitride film is formed on the upper portion using a plasma CVD device to form a protective film 20.

(Embodiment 3) FIG. 6I shows the TF of this embodiment.
A sectional view of T is shown.

In this TFT, a high resistance layer 22 made of polycrystalline silicon mixed with nitrogen or carbon and a semiconductor layer 23 made of polycrystalline silicon are formed in this order on an insulating substrate 21. The semiconductor layer 23 is a channel region 23a which is an intrinsic semiconductor layer, and n ⁺
It is divided into a source region 27 and a drain region 27 which are layers or p ⁺ layers.

A gate insulating film 24 and a gate electrode 25 are formed in this order on the channel region 23a of the semiconductor layer 23, and the anodic oxide film 2 is formed on the surface of the gate electrode 25.
6 is formed.

An interlayer insulating film 28 is formed on the substrate in this state so as to cover the anodic oxide film 26 and the like, and contact holes reaching the source region 27 and the drain region 27 are formed in the interlayer insulating film 28. There is. Interlayer insulation film 2
A source electrode 29 and a drain electrode 29 are formed on the electrode 8 in a state where the contact hole is partially filled, and a protective film 30 is further formed on the source electrode 29 and the drain electrode 29.

Next, a method of manufacturing this TFT will be described.

First, as shown in FIG. 5A, a high resistance layer made of non-single-crystal silicon containing nitrogen or carbon is formed on a transparent insulating substrate 21 made of glass or the like by using a plasma CVD apparatus or a sputtering apparatus. 22 is formed into a film. The high resistance layer 22 contains 10 ²¹ atoms / cm 2 of nitrogen.
^It is desirable that ³ or more are mixed.

Next, as shown in FIG. 5B, an amorphous silicon film is formed on the high resistance layer 22 by using a low pressure CVD apparatus or a plasma CVD apparatus. continue,
The amorphous silicon film is heat-treated by SPC or excimer laser annealing or a combination of SPC and excimer laser to form a polycrystalline silicon film, which is processed into a predetermined shape to obtain the semiconductor layer 23. The thickness of the semiconductor layer 23 is 20 nm in order to obtain good film quality.
Approximately 100 nm is desirable. The high resistance layer 22 made of non-single crystal silicon containing nitrogen or carbon as described above.
Becomes polycrystalline silicon by the above heat treatment. In order to function as a high resistance layer, the film quality of non-single crystal silicon containing nitrogen or carbon may be used as it is. In this embodiment, when the semiconductor layer 23 is formed and when the source region and the drain region which will be described later are formed. The heat treatment performed on the non-single-crystal silicon causes a structural change in the polycrystalline silicon.

Next, as shown in FIG. 5C, a SiO ₂ film having a thickness of 100 nm is formed by using, for example, a plasma TEOS device.
A gate insulating film 24 made of is formed so as to cover the semiconductor layer 23. An Al film containing Ti is formed thereon with a film thickness of 300 nm by using, for example, a sputtering device,
The gate electrode 25 is formed by processing into a predetermined shape.

Next, as shown in FIG. 5 (d), 3% ammonium tartrate and ethylene glycol were added to the former: the latter =
The gate electrode 2 using the solution mixed in the ratio of 1: 9
5 is anodized to form an anodized film 26 of 0.2 μm or less on the surface of the gate electrode 25. The thickness of this anodic oxide film 26 becomes the offset length.

Next, as shown in FIG. 5E, the gate insulating film 24 is etched into a predetermined shape by using the gate electrode 25 and the anodic oxide film 26 as a mask.

Next, as shown in FIG. 5F, with the gate electrode 25 and the anodic oxide film 26 as a mask, the semiconductor layer 23 is doped with phosphorus or boron, for example, by a mass separation type ion implantation apparatus or an ion shower doping apparatus. 10
Inject at least ²⁰ atoms / cm ³ . After that, thermal annealing or laser annealing is performed to activate the impurity ions and to form the source region 27 which is the n ⁺ layer or the p ⁺ layer.
And the drain region 27 is formed. At this time, the semiconductor layer below the anodic oxide film 26 has an offset region (not shown).
become.

Next, as shown in FIG. 6G, for example, a plasma TEOS apparatus is used to form a SiO ₂ film having a thickness of 400 nm.
An interlayer insulating film 28 made of is formed.

Next, as shown in FIG. 6H, two contact holes are formed in the interlayer insulating film 28 so as to reach the source region 27 and the drain region 27, and then Ti is formed by using, for example, a sputtering device. An Al film containing Al is formed to a film thickness of 350 nm, and the contact hole is partially filled to form a source electrode 29 and a drain electrode 29.

Finally, as shown in FIG. 6 (i), the TFT
A silicon nitride film is formed on the upper portion using a plasma CVD apparatus to form a protective film 30.

[0067]

As is apparent from the above description, according to the present invention, the polycrystalline silicon T capable of reducing the leak current at the time of off with almost no decrease in the on-current.
The FT can be manufactured by a simple manufacturing process.
In a TFT-LCD, a TFT having a sufficiently high on-current as a driver element of a peripheral drive circuit and a sufficiently low off-current as a pixel switching element can be realized, so that the driver element and the pixel switching element can be formed by the same process and the same structure. A manufacturing process with excellent productivity that can be manufactured becomes possible.

[Brief description of drawings]

1A to 1F are cross-sectional views showing a manufacturing process of a TFT according to a first embodiment.

2 (g) to (j) are cross-sectional views showing the manufacturing process of the TFT of Example 1. FIG.

3A to 3F are cross-sectional views showing the manufacturing process of the TFT of the second embodiment.

4 (g) to (i) are cross-sectional views showing a manufacturing process of the TFT of Example 2. FIG.

5A to 5F are cross-sectional views showing a manufacturing process of a TFT of Example 3.

6 (g) to (i) are cross-sectional views showing manufacturing steps of the TFT of Example 3. FIG.

7A is a Vg-Id curve of a TFT, FIG.
(B) is a Vds-Id curve of the TFT.

[Explanation of symbols]

 1, 11, 21 Insulating substrate 2, 13, 23 Semiconductor layer made of polycrystalline silicon 3, 14, 24 Gate insulating film 4, 15, 25 Gate electrode 5, 16, 26 Anodized film 6, 12, 22 High resistance Layers 7, 17, 27 Source region and drain region 8, 18, 28 Interlayer insulating film 9, 19, 29 Source electrode and drain electrode 10, 20, 30 Protective film

Claims (8)

[Claims] 1. A thin film transistor in which a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed on a substrate in this order from the substrate side, wherein the semiconductor layer sandwiches a channel region between a source region and a drain. A thin film transistor having a region, in which a high resistance layer is formed on the substrate side of the source region and the drain region of the semiconductor layer. 2. The thin film transistor according to claim 1, wherein the channel region is formed thicker than the source region and the drain region. 3. A thin film transistor in which a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed on a substrate in this order from the substrate side, the semiconductor layer sandwiching a channel region between a source region and a drain. A thin film transistor having a region and a high resistance layer formed over the entire region of the semiconductor layer on the substrate side. 4. The thin film transistor according to claim 1, wherein the high resistance layer is made of a polycrystalline silicon thin film mixed with nitrogen or carbon. 5. A semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed on a substrate in this order from the substrate side, and the semiconductor layer has a source region and a drain region with a channel region interposed therebetween. In the method of manufacturing a thin film transistor, a step of forming a semiconductor layer, a gate insulating film, and a gate electrode on a substrate in this order, and nitrogen or carbon is injected into the semiconductor layer using the gate electrode as a mask so that the semiconductor layer is closer to the substrate. A step of forming a high resistance layer in a portion, and by implanting an impurity into the semiconductor layer using the gate electrode as a mask and performing an activation process, a source region and a source region are formed in the semiconductor layer portion above the high resistance layer. A method of manufacturing a thin film transistor, comprising the step of forming a drain region. 6. When implanting nitrogen or carbon into the semiconductor layer, nitrogen or carbon is added to a portion where the high resistance layer is formed.
²¹ atoms / cm ³ or more is mixed, and nitrogen or carbon is added to the formation region of the source region and the drain region at 10 ²¹ a
The method of manufacturing a thin film transistor according to claim 5, wherein the method is performed so that the amount of less than toms / cm ^{3 is} mixed. 7. A semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed on a substrate in this order from the substrate side, and the semiconductor layer has a source region and a drain region with a channel region interposed therebetween. In a method of manufacturing a thin film transistor, a step of forming a high resistance layer by forming a polycrystalline silicon thin film mixed with nitrogen or carbon on a substrate, or by injecting nitrogen or carbon after forming the polycrystalline silicon thin film. Forming a semiconductor layer, a gate insulating film and a gate electrode in this order on the high resistance layer, and injecting an impurity into the semiconductor layer using the gate electrode as a mask and activating the impurity And a step of forming a source region and a drain region by the method. 8. The insulating film formed on the surface of the gate electrode in addition to the gate electrode is also used as a mask when implanting impurities into the semiconductor layer to form the source region and the drain region. 5. The method for manufacturing a thin film transistor according to any one of 5 to 7.