JPH08249880A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] / Providing a semiconductor memory device capable of preventing the / WE signal from being erroneously detected at a low level and preventing erroneous writing of data to a memory cell. . A power supply voltage conversion circuit 1 for converting an external power supply voltage Vext to an internal power supply voltage Vint lower than the external power supply voltage Vext is provided, and an output terminal of the power supply voltage conversion circuit 1 and an input buffer circuit for at least a write enable signal / WE. 11
The integrating circuit 21 was inserted between the internal power supply voltage applying terminal and the internal power supply voltage applying terminal. The power supply voltage conversion circuit 1a for the sense amplifier 31, the input buffer circuit 11 for at least the write enable signal / WE, and the power supply voltage conversion circuit 1b for the peripheral circuit 32 are provided, and the output terminal of the power supply voltage conversion circuit 1b. The integrating circuit 21 was inserted between the input buffer circuit 11 and the internal power supply voltage applying terminal of the input buffer circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a power supply voltage conversion circuit.

[0002]

2. Description of the Related Art Conventionally, for example, an external power supply voltage Vex of 5V
A power supply voltage conversion circuit (hereinafter, referred to as VDC) for converting t into an internal power supply voltage Vint of 3.3V, which is lower than that used inside the memory, is provided in a semiconductor memory device such as a DRAM (for example, referred to as VDC). Japanese Patent Laid-Open No. 3-2
See Japanese Patent No. 46961. ). An example of this VDC is shown in FIG.

In FIG. 5, the terminal of the external power supply voltage Vext is a p-channel MOSFET (hereinafter, MOSFET).
Is called FET. ) 41 source and drain, n-channel FET 43 drain and source, and n-channel FET 45 drain and source while being grounded, while p-channel FET 42 source and drain, n-channel FET 44 drain and source,
It is also grounded via the drain and source of the FET 45. The terminal of the external power supply voltage Vext is connected to the internal power supply voltage Vint output terminal via the drain and source of the p-channel FET 46. In addition, FET
41 and FET 42 are connected together to form an FET
42, the drains of the FETs 41 and 43 are connected to the gate of the FET 46, and the gate of the FET 44 is connected to the internal power supply voltage Vint output terminal.

In the VDC constructed as described above,
When a high level VDC enable signal is applied to the gate of the FET 45, the FET 45 turns on,
The VDC starts operating. For example, when a reference voltage Vref of 3.3V is applied to the gate of the FET 43,
VDC adjusts the conductance between the drain and the source of the FET 46 by the feedback circuit operation so that the constant reference voltage Vref and the voltage of the source of the FET 46, that is, the converted internal power supply voltage Vint become equal to each other.
It operates to keep the internal power supply voltage Vint constant.

Power supply circuits for the semiconductor memory devices of the conventional examples 1 and 2 using the above VDC are shown in FIGS. 7 and 8, respectively. In the power supply circuit of FIG. 7, the external power supply voltage Vext is VD
After being converted into the internal power supply voltage Vint by C1, it is distributed and supplied to the sense amplifier 31 in the semiconductor memory device and the peripheral circuit 32a including, for example, a row decoder, a column decoder, an input buffer circuit for an input signal, and the like. . Further, in the power supply circuit of FIG. 8, the external power supply voltage Vext
Is supplied to the sense amplifier 31 in the semiconductor memory device after being converted to the internal power supply voltage Vint by VDC1a, and is also supplied to the internal power supply voltage Vi by VDC1b.
After being converted to nt, it is supplied to the peripheral circuit 32a in the semiconductor memory device.

Further, FIG. 6 shows a block diagram of an input buffer circuit included in the peripheral circuit 32a. In FIG. 6, the terminal of the internal power supply voltage Vint is the source and drain of the p-channel FET 51, and the n-channel FET.
Is grounded through the drain and the source. Also, FE
The gates of T51 and FET52 are connected together and connected to the input terminal 60, while the drains of FET51 and FET52 are connected together and connected to the memory side terminal 70.

The input buffer circuit configured as described above is a known CMOS inverter circuit, and the input terminal 6
When the signal input to 0 is _{equal to} or higher than a predetermined high level detection threshold voltage V _IHmin , the FET 52 is turned on,
The FET 51 is turned off, and a low level signal is output from the memory side terminal 70. On the other hand, when the signal input to the input terminal 60 is _equal to or lower than the predetermined low level detection threshold voltage V _ILmax lower than the threshold voltage V _IHmin , the FE
While T51 is turned on, the FET 52 is turned off and a high level signal is output from the memory side terminal 70. For example, when the internal power supply voltage Vint becomes higher than a predetermined value, both the threshold voltages V _IHmin and V _ILmax become high.

[0008]

FIG. 9 shows a conventional DR.
7 is a timing chart of each signal showing a read-modify-write operation in AM. This read-modify-write operation is an operation in which data is read from the memory cell once, and the data is modified and written in one cycle. In FIG. 9, the RAS bar (upper line) (hereinafter referred to as / RAS in this specification).
Similarly, / is used for other symbols. ) Is a row address select signal (hereinafter referred to as / RAS signal). The bar indicates a signal activated at a low level. Further, / CAS is a column address select signal (hereinafter referred to as / CAS signal), / WE is a write enable signal (hereinafter referred to as / WE signal), and /.
OE is an output enable signal (hereinafter referred to as / OE signal).

As shown in FIG. 9, after the / RAS signal becomes low level and the row address is enabled,
When the CAS signal goes low and the column address is enabled, the sense amplifier 31 and the peripheral circuit 32a are
Is enabled, a very large power supply current flows to the sense amplifier 31 and the peripheral circuit 32a. At this time, the FE of FIG.
Since the control of VDC1 with respect to the conductance of T46 cannot catch up and the internal power supply voltage Vint drops temporarily, an undershoot occurs as indicated by 100. Next, VDC1 controls the internal power supply voltage Vint to match the reference voltage Vref by the above feedback circuit operation.
As shown in 1, overshoot occurs. For example, at time t1, the internal power supply voltage Vint becomes higher than a predetermined value, which causes the high level detection threshold voltage V _IHmin to become high. Therefore, at this time, the / WE signal, which should have been at the high level, may be detected by the input buffer circuit to be at the low level, as indicated by 200. At this time t1, since the data to be written has not been input, there is a problem that erroneous data may be written to the memory cell of the DRAM.

FIG. 10 is a timing chart of each signal showing the delayed write operation in the conventional DRAM. In write cycle, delay later than predetermined time / W
When the E signal falls, the output state is not in the high impedance state, but the data write operation is possible in this case as well. This operation is a delayed write operation, and also in this operation, an undershoot 100 and an overshoot 101 occur, and in particular, when the overshoot 101 occurs, the / WE signal becomes 2
As shown in 00, there is a problem that it becomes low level and erroneous data may be written in the memory cell of the DRAM.

The object of the present invention is to solve the above problems and, in particular, to prevent the / WE signal from being erroneously detected at a low level, and to prevent semiconductor memory data from being erroneously written to a memory cell. To provide a device.

[0012]

A first semiconductor memory device according to the present invention is a semiconductor memory device provided with a power supply voltage conversion circuit for converting an external power supply voltage into an internal power supply voltage lower than the external power supply voltage. An integration circuit is inserted between the output terminal of the power supply voltage conversion circuit and at least the internal power supply voltage application terminal of the input buffer circuit for the write enable signal.

A second semiconductor memory device according to the present invention includes a first power supply voltage conversion circuit which converts an external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to a sense amplifier. A second power supply voltage conversion circuit for converting the external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputting the internal power supply voltage to at least an input buffer circuit for a write enable signal and a peripheral circuit; An integration circuit is inserted between the output terminal of the second power supply voltage conversion circuit and the internal power supply voltage application terminal of the input buffer circuit.

Further, in the third semiconductor memory device according to the present invention, the first power supply voltage for converting the external power supply voltage into the internal power supply voltage lower than the external power supply voltage and outputting the internal power supply voltage to the sense amplifier and the peripheral circuit. The conversion circuit and the external power supply voltage
Converted to an internal power supply voltage lower than the external power supply voltage,
At least a second power supply voltage conversion circuit for outputting to the input buffer circuit for the write enable signal is provided.

Furthermore, in a fourth semiconductor memory device according to the present invention, the external power supply voltage is converted into an internal power supply voltage lower than the external power supply voltage and output to the sense amplifier.
Power supply voltage conversion circuit, a second power supply voltage conversion circuit that converts the external power supply voltage to an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to peripheral circuits, and the external power supply voltage to the external power supply. And a third power supply voltage conversion circuit for converting the internal power supply voltage lower than the voltage and outputting to the input buffer circuit for at least the write enable signal.

[0016]

In the first semiconductor memory device configured as described above, the power supply voltage conversion circuit converts the external power supply voltage into the internal power supply voltage lower than the external power supply voltage, and the integration circuit is operated. Via an input buffer circuit for at least the write enable signal. The integrator circuit absorbs fluctuations in the undershoot 100 and overshoot 101 of the internal power supply voltage Vint as shown in FIGS. 9 and 10, and apparently detects the high level detection threshold voltage V in the input buffer circuit. It is possible to improve the margin of _IHmin and prevent a malfunction such as "wrong writing of data" shown in the conventional example.

In the second semiconductor memory device, the first power supply voltage conversion circuit supplies the external power supply voltage to the external power supply voltage.
The second power supply voltage conversion circuit converts the external power supply voltage to an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to the sense amplifier. And outputs to the peripheral circuit and at least the input buffer circuit for the write enable signal and the peripheral circuit via the integrating circuit. Therefore, the internal power supply voltage is supplied to the sense amplifier that consumes a relatively large current consumption by the first power supply voltage conversion circuit different from the second power supply voltage conversion circuit for the input buffer circuit. . Thereby, the first
Compared to the semiconductor memory device of No. 1, the influence of the fluctuation of the internal power supply voltage on the input buffer circuit and the peripheral circuit due to the current consumption of the sense amplifier is eliminated. Further, the integrator circuit absorbs fluctuations of the internal power supply voltage to the input buffer circuit, such as undershoot and overshoot, similar to the first semiconductor memory device, and apparently the high level of the input buffer circuit. It is possible to improve the margin of the detection threshold voltage V _IHmin and prevent malfunction such as “wrong writing of data” shown in the conventional example.

Further, in the third semiconductor memory device, the first power supply voltage conversion circuit converts an external power supply voltage into an internal power supply voltage lower than the external power supply voltage to form a sense amplifier and peripheral circuits. Output to the second
The power supply voltage conversion circuit converts the external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to at least an input buffer circuit for a write enable signal. Therefore, the internal power supply voltage is supplied to the sense amplifier and the peripheral circuit which consume relatively large current consumption by the first power supply voltage conversion circuit different from the second power supply voltage conversion circuit for the input buffer circuit. are doing. As a result, the influence of the fluctuation of the internal power supply voltage on the input buffer circuit due to the current consumption of the sense amplifier and the peripheral circuit is eliminated. Therefore, compared to the conventional example, the undershoot and overshoot of the internal power supply voltage to the input buffer circuit can be reduced, and apparently the margin of the high level detection threshold voltage V _IHmin in the input buffer circuit is _small . Therefore, it is possible to prevent malfunctions such as “erroneous writing of data” shown in the conventional example.

Furthermore, in the fourth semiconductor memory device, the first power supply voltage conversion circuit converts the external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to the sense amplifier. . Further, the second power supply voltage conversion circuit converts the external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to a peripheral circuit. Further, the third power supply voltage conversion circuit converts the external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to at least an input buffer circuit for a write enable signal. Therefore, for the sense amplifier and the peripheral circuit that consume relatively large current consumption, first and second power supply voltages dedicated to the input buffer circuit and different from the third power supply voltage conversion circuit. The conversion circuit supplies the internal power supply voltage. As a result, the influence of the fluctuation of the internal power supply voltage on the input buffer circuit due to the current consumption of the sense amplifier and the peripheral circuit is eliminated. Therefore, compared to the conventional example, the undershoot and overshoot of the internal power supply voltage to the input buffer circuit can be reduced, and apparently the margin of the high level detection threshold voltage V _IHmin in the input buffer circuit is _small . Therefore, it is possible to prevent malfunctions such as “erroneous writing of data” shown in the conventional example.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1. FIG. 1 shows a first embodiment according to the present invention.
FIG. 3 is a block diagram showing a power supply circuit of the semiconductor memory device. In FIG. 1, the same components as those in FIGS. 7 and 8 are designated by the same reference numerals. The power supply circuit according to the first embodiment includes one VDC1, the output terminal of VDC1 and the internal power supply voltage Vint of each of the input buffer circuits 11 to 14.
It is characterized in that integrating circuits 21 to 24 each composed of a resistor R and a capacitor C are inserted between the applying terminal and the applying terminal.

As shown in FIG. 1, an external power supply voltage Vext of, for example, 5V is lower than the external power supply voltage Vext by a predetermined internal power supply of 3.3V by VDC1 having the circuit configuration shown in FIG. After being converted into the voltage Vint, it is distributed and supplied to the sense amplifier 31 and the peripheral circuit 32, and also distributed and supplied to the input buffer circuits 11 to 14 through the integrating circuits 21 to 24. Each of the integrating circuits 21 to 24 is composed of a resistor R connected in series between the input and output terminals of the circuit, and a capacitor C connected between the output terminal of the circuit and the ground.

The peripheral circuit 32 is, for example, a peripheral circuit for a DRAM and includes circuits such as a row decoder and a column decoder, but does not include an input buffer circuit for an input signal. Each of the input buffer circuits 11 to 14 has the CMOS circuit configuration shown in FIG.
Here, the input buffer circuit 11 is an input buffer circuit for the / WE signal, and has an input terminal 61 and a memory side terminal 71. In addition, the input buffer circuit 12 is /
It is an input buffer circuit for the OE signal and has an input terminal 62 and a memory side terminal 72. Further, the input buffer circuit 13 is an input buffer circuit for the / RAS signal, and has an input terminal 63 and a memory side terminal 73. Furthermore, the input buffer circuit 14 is an input buffer circuit for the / CAS signal, and has an input terminal 64 and a memory side terminal 74.

In this embodiment, the integrating circuits 21 to 24 are used.
Is an input buffer circuit 1 for at least the / WE signal
It is preferable to provide the internal power supply voltage Vint 1 in the preceding stage. Further, in FIG. 1, for example, an internal power supply voltage Vint application terminal of an input buffer circuit (not shown) for input signals such as address pins and I / O pins, and VDC.
An integrating circuit (not shown) may preferably be inserted between the output terminal 1 and the output terminal 1. The product of the resistance value of the resistor R and the capacitance value of the capacitor C is, as is well known, the integrating circuit 2
The time constant is 1 to 24, and is set such that the undershoot and overshoot at the internal power supply voltage Vint are small values.

In the power supply circuit of the first embodiment configured as described above, the integrating circuit 2 is provided in each of the input buffer circuits 11 to 14 before the internal power supply voltage Vint application terminal.
1 to 24 are provided, the undershoot 100 of the internal power supply voltage Vint as shown in FIGS. 9 and 10, for example.
It is possible to absorb the fluctuation of the overshoot 101 and the like, and apparently improve the margin of the high level detection threshold voltage V _IHmin of each of the input buffer circuits 11 to 14. It is possible to prevent a malfunction such as "."

Example 2. FIG. 2 shows a second embodiment according to the present invention.
FIG. 3 is a block diagram showing a power supply circuit of the semiconductor memory device. 2, the same components as those in FIGS. 1, 7 and 8 are designated by the same reference numerals. The power supply circuit according to the second embodiment includes two VDCs 1a and 1b, and a resistor R and a capacitor C are provided between the output terminal of VDC 1b and the internal power supply voltage Vint application terminals of the input buffer circuits 11 to 14, respectively. Integrating circuits 21 to 24 are inserted. Hereinafter, differences from the first embodiment will be described in detail.

As shown in FIG. 2, the external power supply voltage Vext
Is converted into internal power supply voltage Vint by VDC 1a having the circuit configuration shown in FIG. 5, and then supplied to sense amplifier 31. Further, external power supply voltage Vext is converted to internal power supply voltage Vint by VDC 1b having the circuit configuration shown in FIG. 5, and then supplied to peripheral circuit 32 and input buffer circuit via integrating circuits 21 to 24. 11 to 14 are distributed and supplied.

In this embodiment, the integrating circuits 21 to 24 are used.
Is an input buffer circuit 1 for at least the / WE signal
It is preferable to provide the internal power supply voltage Vint 1 in the preceding stage. Further, in FIG. 2, for example, an internal power supply voltage Vint application terminal of an input buffer circuit (not shown) for input signals such as address pins and I / O pins, and VDC.
An integrating circuit (not shown) may preferably be inserted between the output terminal of 1b.

In the power supply circuit configured as described above, the sense amplifier 31 consuming a relatively large current consumption.
VD for the input buffer circuits 11 to 14
Internal power supply voltage Vint is generated by VDC1a which is different from C1b.
Is being supplied. As a result, as compared with the first embodiment, the input buffer circuit 11 based on the current consumption of the sense amplifier 31 is used.
To 14 and the peripheral circuit 32, the influence of the fluctuation of the internal power supply voltage Vint is eliminated. Further, since the power supply circuit of this embodiment is provided with the integrating circuits 21 to 24, like the first embodiment, it absorbs fluctuations such as undershoot and overshoot of the internal power supply voltage Vint to the input buffer circuits 11 to 14. However, apparently, each of the input buffer circuits 11 to 1
It is possible to improve the margin of the high level detection threshold voltage V _IHmin of _No. 4 and prevent the malfunction such as the “wrong writing of data” shown in the conventional example.

Example 3. FIG. 3 shows a third embodiment according to the present invention.
FIG. 3 is a block diagram showing a power supply circuit of the semiconductor memory device. 3, FIG. 1 and FIG. 2, and FIG. 7 and FIG.
The same symbols are attached to the same components. The power supply circuit according to the third embodiment is characterized by including two VDCs 1a and 1b, and the VDC 1b is a dedicated VDC for each of the input buffer circuits 11 to 14. Less than,
Differences from the first and second embodiments will be described in detail.

As shown in FIG. 3, the external power supply voltage Vext
Is supplied to the sense amplifier 31 and the peripheral circuit 32 after being converted into the internal power supply voltage Vint by the VDC 1a having the circuit configuration shown in FIG. 5, and internally by the VDC 1b having the circuit configuration shown in FIG. After being converted into the power supply voltage Vint, it is directly distributed and supplied to the input buffer circuits 11 to 14 without passing through the integrating circuit.

In this embodiment, VDC1b is preferably provided at least before the internal power supply voltage Vint application terminal of the input buffer circuit 11 for the / WE signal. Further, in FIG. 3, for example, address pins and I /
An input buffer circuit (not shown) for an input signal such as an O pin may be connected to the output terminal of VDC 1b.

In the power supply circuit configured as described above, the sense amplifier 31 that consumes a relatively large current consumption.
Also, the internal power supply voltage Vint is supplied to the peripheral circuit 32 by a VDC 1a different from the VDC 1b for the input buffer circuits 11 to 14. As a result, the influence of the fluctuation of the internal power supply voltage Vint on the input buffer circuits 11 to 14 due to the current consumption of the sense amplifier 31 and the peripheral circuit 32 is eliminated. Therefore, the undershoot and overshoot of the internal power supply voltage Vint to the input buffer circuits 11 to 14 can be reduced as compared with the conventional example, and the high level detection threshold of each of the input buffer circuits 11 to 14 is apparently detected. It is possible to improve the margin of the value voltage V _IHmin and prevent malfunction such as “wrong writing of data” shown in the conventional example.

Embodiment 4 FIG. FIG. 4 shows a fourth embodiment according to the present invention.
FIG. 3 is a block diagram showing a power supply circuit of the semiconductor memory device. 4, FIG. 1 to FIG. 3, and FIG. 7 and FIG.
The same symbols are attached to the same components. The power supply circuit according to the fourth embodiment is different from the power supply circuit according to the third embodiment in that the sense amplifier 31 and the peripheral circuit 32 have V independent of each other.
The feature is that DCs 1a and 1b are provided. Less than,
Differences from the third embodiment will be described in detail.

As shown in FIG. 4, the external power supply voltage Vext
Is converted into an internal power supply voltage Vint by VDC1a having the circuit configuration shown in FIG. 5, then supplied to sense amplifier 31, and converted to internal power supply voltage Vint by VDC1b having the circuit configuration shown in FIG. Then, it is supplied to the peripheral circuit 32. Further, the external power supply voltage Vext is VDC which has the circuit configuration shown in FIG.
After being converted to the internal power supply voltage Vint by 1c, it is distributed and supplied to the input buffer circuits 11 to 14.

In the present embodiment, VDC 1c is preferably provided at least before the internal power supply voltage Vint application terminal of the input buffer circuit 11 for the / WE signal. Further, in FIG. 4, for example, address pins and I /
An input buffer circuit (not shown) for an input signal such as an O pin may be connected to the output terminal of VDC 1c.

In the power supply circuit configured as described above, the sense amplifier 31 which consumes a relatively large current consumption.
And the peripheral circuit 32, a dedicated VDC different from the VDC 1c for the input buffer circuits 11 to 14
The internal power supply voltage Vint is supplied by 1a and 1b. As a result, the influence of the fluctuation of the internal power supply voltage Vint on the input buffer circuits 11 to 14 due to the current consumption of the sense amplifier 31 and the peripheral circuit 32 is eliminated. Therefore,
Compared with the conventional example, the undershoot and overshoot of the internal power supply voltage Vint to the input buffer circuits 11 to 14 can be reduced, and the high level detection threshold voltage of each of the input buffer circuits 11 to 14 is apparently seen. V
It is possible to improve the margin of _IHmin and prevent a malfunction such as "wrong writing of data" shown in the conventional example.

The semiconductor memory device according to the present invention has a D
Not limited to RAM, SRAM, EPROM, EEPROM
Can be applied to semiconductor memory devices such as.

[0039]

As described above in detail, according to the first semiconductor memory device of the present invention, it is provided with the power supply voltage conversion circuit for converting the external power supply voltage into the internal power supply voltage lower than the external power supply voltage. In the semiconductor memory device, an integrating circuit is inserted between the output terminal of the power supply voltage conversion circuit and at least the internal power supply voltage applying terminal of the input buffer circuit for the write enable signal. Therefore,
The integrator circuit absorbs fluctuations in the undershoot 100 and overshoot 101 of the internal power supply voltage Vint as shown in FIGS. 9 and 10, and apparently detects the high level detection threshold voltage V in the input buffer circuit.
It is possible to improve the margin of _IHmin and prevent a malfunction such as "wrong writing of data" shown in the conventional example.

Further, according to the second semiconductor memory device of the present invention, the external power supply voltage is converted into the internal power supply voltage lower than the external power supply voltage and is output to the sense amplifier.
And a second power supply voltage for converting the external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputting the internal power supply voltage to at least the input buffer circuit for the write enable signal and the peripheral circuit. And a conversion circuit,
An integration circuit is inserted between the output terminal of the second power supply voltage conversion circuit and the internal power supply voltage application terminal of the input buffer circuit. Therefore, for a sense amplifier that consumes a relatively large current consumption, a first power supply voltage conversion circuit that is different from the second power supply voltage conversion circuit for the input buffer circuit is used.
The internal power supply voltage is supplied by the power supply voltage conversion circuit. As a result, the influence of the fluctuation of the internal power supply voltage on the input buffer circuit and the peripheral circuit due to the current consumption of the sense amplifier is eliminated as compared with the first semiconductor memory device. Further, the integrator circuit absorbs fluctuations of the internal power supply voltage to the input buffer circuit, such as undershoot and overshoot, similar to the first semiconductor memory device, and apparently the high level of the input buffer circuit. It is possible to improve the margin of the detection threshold voltage V _IHmin and prevent malfunction such as “wrong writing of data” shown in the conventional example.

Further, according to the third semiconductor memory device of the present invention, the external power supply voltage is converted into the internal power supply voltage lower than the external power supply voltage and output to the sense amplifier and the peripheral circuit. And a second power supply voltage conversion circuit for converting the external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputting the internal power supply voltage to an input buffer circuit for at least a write enable signal. It is characterized by that. Therefore, the internal power supply voltage is supplied to the sense amplifier and the peripheral circuit which consume relatively large current consumption by the first power supply voltage conversion circuit different from the second power supply voltage conversion circuit for the input buffer circuit. are doing. As a result, the influence of the fluctuation of the internal power supply voltage on the input buffer circuit due to the current consumption of the sense amplifier and the peripheral circuit is eliminated. Therefore, compared to the conventional example, the undershoot and overshoot of the internal power supply voltage to the input buffer circuit can be reduced,
Apparently, the margin of the high level detection threshold voltage V _IHmin in the input buffer circuit can be improved, and malfunctions such as “erroneous writing of data” shown in the conventional example can be prevented.

Further, according to the fourth semiconductor memory device of the present invention, the first power supply voltage conversion for converting the external power supply voltage into the internal power supply voltage lower than the external power supply voltage and outputting it to the sense amplifier. A circuit, a second power supply voltage conversion circuit for converting the external power supply voltage to an internal power supply voltage lower than the external power supply voltage and outputting the internal power supply voltage to a peripheral circuit, and the external power supply voltage lower than the external power supply voltage. And a third power supply voltage conversion circuit for converting the internal power supply voltage and outputting it to an input buffer circuit for at least a write enable signal. Therefore, for the sense amplifier and the peripheral circuit that consume relatively large current consumption, first and second power supply voltages dedicated to the input buffer circuit and different from the third power supply voltage conversion circuit. The conversion circuit supplies the internal power supply voltage. This allows
The influence of the fluctuation of the internal power supply voltage on the input buffer circuit due to the current consumption of the sense amplifier and the peripheral circuit is eliminated. Therefore, as compared with the conventional example, the undershoot and overshoot of the internal power supply voltage to the input buffer circuit can be reduced, and apparently the high level detection threshold voltage V in the input buffer circuit can be reduced.
It is possible to improve the margin of _IHmin and prevent a malfunction such as "wrong writing of data" shown in the conventional example.

[Brief description of drawings]

FIG. 1 is a block diagram showing a power supply circuit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a power supply circuit of a semiconductor memory device that is Embodiment 2 of the present invention.

FIG. 3 is a block diagram showing a power supply circuit of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a power supply circuit of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a power supply voltage conversion circuit (VDC) used in the embodiment and the conventional example.

FIG. 6 is a block diagram of an input buffer circuit used in the embodiment and the conventional example.

FIG. 7 is a block diagram showing a power supply circuit of a semiconductor memory device of Conventional Example 1.

FIG. 8 is a block diagram showing a power supply circuit of a semiconductor memory device of Conventional Example 2.

FIG. 9 is a timing chart of each signal showing a read-modify-write operation in the conventional DRAM.

FIG. 10 is a timing chart of each signal showing a delayed write operation in a conventional DRAM.

[Explanation of symbols]

1, 1a, 1b, 1c power supply voltage conversion circuit (VDC),
11 to 14 input buffer circuits, 21 to 24 integrating circuits, 31 sense amplifiers, 32 peripheral circuits, 41 to 46, 51, 52 FETs, 60, 61 to 64 input terminals, 70, 71 to 74 memory side terminals.

Claims (4)

[Claims] 1. A semiconductor memory device comprising a power supply voltage conversion circuit for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage, wherein an output terminal of the power supply voltage conversion circuit and at least a write enable signal are provided. A semiconductor memory device characterized in that an integrating circuit is inserted between the input buffer circuit and an internal power supply voltage applying terminal for the purpose. 2. A first power supply voltage conversion circuit which converts an external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to a sense amplifier, and the external power supply voltage is higher than the external power supply voltage. A second internal power supply voltage which is converted into a low internal power supply voltage and is output to at least an input buffer circuit for a write enable signal and a peripheral circuit;
And a power supply voltage conversion circuit, wherein an integration circuit is inserted between the output terminal of the second power supply voltage conversion circuit and the internal power supply voltage application terminal of the input buffer circuit. . 3. A first power supply voltage conversion circuit for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage and outputting the internal power supply voltage to a sense amplifier and a peripheral circuit; A semiconductor memory device comprising: a second power supply voltage conversion circuit which converts an internal power supply voltage lower than a power supply voltage and outputs the converted power supply voltage to an input buffer circuit for at least a write enable signal. 4. A first power supply voltage conversion circuit that converts an external power supply voltage into an internal power supply voltage lower than the external power supply voltage and outputs the internal power supply voltage to a sense amplifier, and the external power supply voltage is higher than the external power supply voltage. A second power supply voltage conversion circuit for converting the internal power supply voltage to a low internal power supply voltage and outputting the same to a peripheral circuit; and converting the external power supply voltage to an internal power supply voltage lower than the external power supply voltage for at least a write enable signal. A semiconductor memory device comprising a third power supply voltage conversion circuit for outputting to an input buffer circuit.