JPH08242233A - Atm switch monitoring circuit - Google Patents

Abstract

PURPOSE: To monitor and guarantee synchronizing operation among respective switch elements constituting an ATM switch. CONSTITUTION: Input signals 22-1 to 22-N are multiplexed by a multiplexing part 51 and supplied to address filters 52-1 to 52-M. Outputs from the address filters 52-1 to 52-M are counted by respective counters 53-1 to 53-M. Each of the counters 53-1 to 53-M periodically counts up the number of cells stored in a buffer in each output port. The count values of the counters 53-1 to 53-M are periodically stored in respective registers 54-1 to 54-M. The storage values of respective registers 54-1 to 54-M are compared with the storage values of registers in another switch element by respective comparing circuits 55-1 to 55-M. A synchronous deviation is monitored based upon a compared result, and at the time of detecting non-coincidence, a reset signal is sent to control the synchronism of respective switch elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM switch monitor circuit used in an asynchronous transfer mode communication system, and particularly between switch elements when it is realized by a plurality of switch elements (units such as boards) by a bit slice configuration. The present invention relates to an ATM switch monitoring circuit that monitors the synchronization of the above.

[0002]

2. Description of the Related Art This type of asynchronous transfer mode ("AT
M ”; Asynchronous Transfer Mode; see CCITT Recommendation 1.361.) The switch is usually several hundred [Mbit /
s] to several [Gbit / s] high-speed signals are processed, so that the processing speed is high, and generally a large-scale switch is configured by a bit slice configuration (“Configuration method of output buffer type ATM switch”). , Suzuki et al., IEEJ, SSE 88-172, pp. 37-42, 198.
Issued for 8 years).

In many cases, such a switch is divided into a plurality of switch elements and mounted, and a buffer control circuit is mounted on each switch element.

FIG. 4 shows such a bit slice type AT.
The M switch is shown. In the figure, the ATM switch is
K (where K is an arbitrary integer) switch elements 101-
1 ... 101-K and monitoring cell insertion unit 102-1 ... 10
2-N and detection circuits 103-1 ... 103- for monitoring cells
It consists of M and. In addition, each switch element 101-1
.. 101-K includes a switch with buffer 104 and a switch control circuit 105.

Switch input signals 201-1 ... 201-
N is input to the monitoring cell insertion units 102-1 ... 102-N. These monitoring cell insertion units 102-1 ... 102-
From N, a switch signal and signals 202-1 ... 202-N indicating the output destination of the switch are output. The signals of each switch are the switch elements 101-1 ... 101-N.
Is input to each buffered switch 104. Also,
These signals 202-1 ... 202-N are transmitted to the switch control circuits 10 of the switch elements 101-1 ... 101-K.
5 is input. The reset signal 203 is also input to each switch control circuit 105. The output signal from each buffered switch 104 is the detection circuit 10 for the monitoring cell.
3-1 ... 103-M. The output signals 204-1 ... 204-M of the switches are output from the detection circuits 103-1 ... 103-M of the monitoring cells.

The switch control circuit 105 controls the buffered switch 104 by a buffer control signal 205. The buffered switch 104 is generally
It is composed of multiple chips. Monitoring cell insertion unit 102-
102-N periodically insert monitoring cells, decode the headers of the input cells, and control the respective switches by synchronizing signals 202-1 ... 202-N indicating the output destination of the switch with the input cells. It is sent to the circuit 105.

Further, the monitoring cell detection circuits 103-1 ...
103-N drops the monitor cell and detects the phase shift of the cell. When the phase shift is detected, the reset signal 203 is sent to each switch control circuit 105 provided in all the switch elements 101-1 ... 101-K.
Is sent.

In the ATM switch monitoring circuit thus constructed, the switch control circuits 105 of all switch elements must be operated in synchronization. Therefore, conventionally, all switch elements 101-1 ... 101-
A first circuit configured to reset in synchronization with the initial startup of K, and a plurality of switch elements that take in monitoring cells from the outside of the plurality of switch elements 101-1 ... 101-K during operation. 101-1 ... 10
The normality of the monitoring cell output from 1-K is monitored periodically, and when an abnormality is detected, the switch element 10
It had a second circuit for resetting 1-1 ... 101-K again.

By the way, a plurality of switch elements 10
As a method of resetting 1-1 ... 101-K, when one switch element is used as a master and the rest are slaves, the master resets the slave to the slave according to an instruction from the control unit at the time of initialization and an abnormality. There are those which pass a signal and those which input reset from the outside when an abnormality is detected and each switch element is reset when a reset cell is detected (Japanese Patent Laid-Open No. 5-32).
7777 gazette).

[0010]

In such a conventional resetting method, a monitoring cell is periodically input from the outside of the switch, and a monitoring cell output by the switch is detected to detect between the switch elements. Since synchronous monitoring is performed, a circuit for generating / detecting a monitoring cell outside the switch is required for each input / output of the switch, which has a drawback of increasing the number of parts.

Further, if a resynchronization is performed by resetting when an abnormality occurs during operation, all circuits (input / output ports) are reset and normal input / output ports are reset, and data is discarded. There was a drawback that it would end up.

Further, an instruction to reset the switch element is detected by the computer (C
When it is performed by a control unit such as PU), there is a problem that it takes time to recover from an abnormality.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks of the conventional device and to provide an ATM switch monitoring circuit which monitors and guarantees the synchronous operation between the switch elements.

[0014]

According to a first aspect of the present invention, (a) an input port for receiving input signals of N switches (N is an arbitrary integer) and (b) M ports (M is An arbitrary integer, N ≠ M) output port that outputs the output signal of the switch and (c) the input signal from the input port is switched, and the number of accumulated cells in the buffer for each output port is periodically stored. However, the present invention is characterized by comprising a switch element capable of comparing the stored value of the stored cell number with the stored number of other cells to monitor the synchronization deviation and outputting a reset signal when they do not match. Is.

That is, according to the first aspect of the invention, at the time of initialization without defining a special cell such as a switch monitoring cell or a reset cell, and without requiring a cell generating circuit for monitoring outside the switch. Further, the reset can be performed quickly and independently from the detection of the abnormality, and the synchronization between the plurality of switch elements can be established.

According to the second aspect of the present invention, the switch element has (a) a buffer for storing the input signal from the input port, and the switch for switching the input signal and the buffer of the (b) switch can be controlled. With
The number of accumulated cells in the buffer for each output port is stored periodically, the stored value of the accumulated number of cells is compared with the accumulated number of other cells to monitor the synchronization deviation, and a reset signal is output when they do not match. And a switch control circuit that operates.

According to another aspect of the invention, the buffer control circuit stores (a) a counter for managing the number of cells stored in the buffer and (b) a counter value when a periodic signal is received. , A comparison means for outputting the count value and (c) comparing the count value stored in the storage means with the count value input from another switch element, and outputting a reset signal when the comparison result is different. Means for resetting the buffer control circuit at the timing of the periodic signal when the reset signal is received.

According to a fourth aspect of the invention, the storage means is a register.

According to the invention of claim 5, (a) N pieces (N
Is an arbitrary integer), and (b) is M input ports (M is an arbitrary integer, N ≠).
An output port for outputting the output signal of the switch of M),
(C) A switch that has a buffer that stores an input signal from the input port and that switches the input signal;
(D) The buffer of the switch can be controlled, and the number of accumulated cells in the buffer for each output port is stored periodically, and the stored value of this accumulated number of cells is compared with other accumulated numbers of cells to determine synchronization deviation. And a switch control circuit that monitors and outputs a reset signal when they do not match.

That is, according to the invention of claim 5, at the time of initialization without defining a special cell such as a switch monitoring cell or a reset cell, and without requiring a cell generating circuit for monitoring outside the switch. Further, the reset can be performed quickly and independently from the detection of the abnormality, and the synchronization between the plurality of switch elements can be established.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 3 shows an ATM switch to which the present invention is applied. In the figure, the ATM switch includes K switch elements 11 (K is an arbitrary integer).
-1 ... 11-K and monitoring cell insertion section 12-1 ... 12-
N and a monitoring cell detection circuit 13-1 ... 13-M. Also, each switch element 11-1 ... 11-K
Is composed of a switch with buffer 14 and a switch control circuit 15.

Switch input signals 21-1 ... 21-N
Is input to the monitoring cell insertion units 12-1 ... 12-N. From these monitoring cell insertion units 12-1 to 12-N, a signal of the switch and a signal 2 indicating the output destination of the switch are output.
2-1 ... 22-N is output. The signal of each switch is
The switch elements 11-1 ... 11-N are input to the buffered switches 14. In addition, these signals 22-
1 ... 22-N are switch elements 11-1 ... 11-
It is input to each K switch control circuit 15. The reset signal 23 is also input to each switch control circuit 15. An output signal from each buffered switch 14 is applied to the monitoring cell detection circuits 13-1 ... 13-M. The output signals 24-1 ... 24-M of the switches are output from the detection circuits 13-1 ... 13-M of the monitoring cells.

Here, the switch control circuit 15 controls the buffered switch 14 by the buffer control signal 25. The buffered switch 14 is generally composed of a plurality of chips. Monitoring cell insertion unit 12-1 ... 12-
N periodically inserts the monitoring cell, decodes the header of the input cell, and outputs a signal 22 indicating the output destination of the switch.
-1 ... 22-N is sent to each switch control circuit 15 in synchronization with the input cell.

Further, the monitoring cell detection circuits 13-1 ... 1
3-N drops the monitor cell and detects the phase shift of the cell. When the phase shift is detected, the reset signal 23 is sent to each switch control circuit 15 provided in all the switch elements 11-1 ... 11-K.

FIG. 1 shows a switch control circuit 15 having an ATM switch monitoring circuit. The switch control circuit 15 including the ATM switch monitoring circuit includes a multiplexing unit 51, address filters 52-1 ... 52-M, counters 53-1 ... 53-M, and registers 54-1 ... 54-.
M and comparison circuits 55-1 ... 55-M.

FIG. 2 shows an example of a time chart of control signals in the switch monitoring circuit of the present invention. In this figure, the horizontal axis represents time, and the vertical axis represents the periodic signal 28, the cell head signal 32, the output value 33 of the counter 53, the latch value of the register 54 (counter storage value (counter value output 2
9), the counter value input 30 and the reset output 31 are shown. The cycle signal 28 is synchronized with the cell head signal 33 and has a cycle that is an integral multiple of the cell length. Further, the cell accumulation number counters 53-1 to 53-M indicate the cell accumulation number in the buffer managed for each output port, and are updated every time a cell is input / output in synchronization with the cell head signal 32. To be done. The counter value output 29 indicates a value obtained by latching the count value of the cell accumulation number counter 53 at the timing of the periodic signal 28, and is output data of the register 54. The counter value input 30 indicates the number of accumulated cells in the buffer latched by the other switch element at the timing of the periodic signal.
Outputs 1. The reset output 31 is logically ORed with the reset outputs of other switch elements externally and becomes the reset input. When the reset input is active (low level in FIG. 2), the in-buffer cell accumulation number counter 53 is generated at the timing of the periodic signal 28.
-1 ... 53-M is reset.

Next, the operation will be described. The signals 22-1 ... 22-N indicating the output destinations of the switches are multiplexed by the multiplexer 51.
Are multiplexed and supplied to all output ports. Since the output filters are provided with the address filters 52-1 ... 52-M, these address filters 52-1 ... 5
By 2-M, detection of matching with the signal indicating the output destination,
When they match, the buffer write control signals 26-1 ... 2
Output 6-M. At this time, the cell head signal 32
Since "1" is input, "1" is added to the counters 53-1 to 53-M indicating the number of accumulated cells in the switch control circuit 15.

When the counter values of these counters 53-1 ... 53-M are greater than zero, the buffer read control signals 27-1 ... 27-M are sent out at the cell timing on the output side, and the counters 53-1 ... 53-M. "1" is subtracted from. Normally, the above sequence is repeated.

Further, as shown in FIG. 2A, a periodic signal 28 indicating a monitoring period is input to this switch. At the timing when the periodic signal 28 is input, the values counted by the counters 53-1 to 53-M (see FIG. 2C) are stored in the registers 54-1 to 54-.
It is latched to M (see timing ta in FIG. 2D).
The latched value is given to the comparison circuits 55-1 ... 55-M and the other switch elements 11-1.
11-K are output as counter value outputs 29-1 ... 29-M. In the comparison circuits 55-1 ... 55-M, the counter values 30-1 ... 30-M input from other switch elements and the latched values (see FIG. 2 (e)) as shown in FIG. 2 (e). ) Is compared with each other, and if the comparison result does not match, reset outputs 31-1 ... 31-M are output as shown at time tb in FIG.

Further, external reset input 32-1 ...
When the 32-M indicates reset, the time tc in FIG.
As shown in FIG.
3-1 ... 53-M is reset, and a buffer (not shown) is reset by a reset signal (not shown).

In this embodiment, it is not necessary to define a special cell such as a switch monitoring cell and a reset cell, and a monitoring cell is generated (inserted) outside the switch.
Alternatively, it does not require a circuit for detection (drop),
It is possible to reset each port immediately after initialization and when an abnormality is detected, and to establish synchronization between a plurality of switch elements.

Further, in the present embodiment, the processing speed can be made constant regardless of the switch scale and the switch speed, so that the present invention can also be applied to an ultra-high-speed ATM switch.

[0034]

As described above, according to the first aspect of the invention, the cell accumulation number in the buffer for each output port is periodically stored and the stored value of this cell accumulation number and other cell accumulation numbers are stored. It is possible to output a reset signal when there is a discrepancy by monitoring the synchronization deviations by comparing with each other.Therefore, it is not necessary to define a special cell such as a switch monitoring cell or a reset cell, and a monitoring cell outside the switch. It is possible to quickly and independently reset from the time of initialization and the detection of abnormality without requiring a generation circuit, and it is possible to establish synchronization between a plurality of switch elements.

According to the second aspect of the invention, the switch for switching the input signal of the switch and the cell accumulation number in the buffer for each output port are periodically stored, and the stored value of the cell accumulation number and other cells are stored. Since it is equipped with a switch control circuit that compares the accumulated number to monitor the synchronization deviation and outputs a reset signal when they do not match, it is possible to reliably monitor the switching of the input of the switch and the synchronization deviation.

Further, in the third aspect of the present invention, the buffer control circuit stores a counter for managing the number of cells accumulated in the buffer and the counter value when the periodic signal is received, and outputs the count value. The storage means and the comparison means for comparing the count value stored in the storage means with the count value input from another switch element and outputting a reset signal when the comparison result is different are provided. In addition, it is possible to quickly and independently perform the reset at the time of initialization and the detection of an abnormality, and it is possible to reliably establish the synchronization between the plurality of switch elements.

Further, in the invention according to the fourth aspect, since the storage means is constituted by the register, the storage means can be obtained with a simple structure.

Further, in the invention according to claim 5, the switch for switching the input signal and the cell accumulation number in the buffer for each output port are periodically stored, and the stored value of this cell accumulation number and other cell accumulation numbers are stored. And a switch control circuit that outputs a reset signal when there is a discrepancy, and that does not define a special cell such as a switch monitoring cell or a reset cell. Further, resetting can be performed quickly and independently from the time of initialization and the detection of an abnormal time without requiring a cell generation circuit for monitoring, and synchronization between a plurality of switch elements can be established.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an ATM switch monitoring circuit according to the present invention.

FIG. 2 is a flow chart for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing a configuration example of an ATM switch to which the embodiment is applied.

FIG. 4 is a block diagram showing a configuration example of a conventional ATM switch.

[Explanation of symbols]

 11-1 ... 11-K switch element 12-1 ... 12-N monitoring cell insertion unit 13-1 ... 13-M monitoring cell detection circuit 14 buffered switch 15 switch control circuit 51 multiplexing unit 52-1 ... 52-M address filter 53-1 ... 53-M counter 54-1 ... 54-M register 55-1 ... 55-M comparison circuit

Claims (5)

[Claims] 1. An input port for receiving an input signal of N switches (N is an arbitrary integer), and an output for outputting an output signal of M switches (M is an arbitrary integer, N ≠ M). A port and switching the input signal from the input port,
The number of accumulated cells in the buffer for each output port is stored periodically, the stored value of the accumulated number of cells is compared with the accumulated number of other cells to monitor the synchronization deviation, and a reset signal is output when they do not match. An ATM switch monitoring circuit, comprising: 2. The switch element has a buffer for storing an input signal from the input port, and a switch for switching the input signal, a buffer for the switch, and a buffer for each output port. And a switch control circuit that periodically stores the cell accumulation number, monitors the synchronization deviation by comparing the stored value of the cell accumulation number with other cell accumulation numbers, and outputs a reset signal when they do not match. The ATM switch monitoring circuit according to claim 1, wherein: 3. A buffer control circuit, a counter that manages the number of cells accumulated in the buffer, and a storage unit that stores the value of the counter when a periodic signal is received and outputs the count value. When the reset signal is received, the count value stored in the storage means is compared with the count value input from the other switch element, and the comparison means outputs a reset signal when the comparison result is different. 3. The ATM switch monitoring circuit according to claim 2, wherein the buffer control circuit is reset at the timing of the periodic signal. 4. The ATM switch monitoring circuit according to claim 3, wherein the storage means is a register. 5. An input port for receiving an input signal of N switches (N is an arbitrary integer) and an output for outputting output signals of M switches (M is an arbitrary integer, N ≠ M). A switch that has a port and a buffer that stores an input signal from the input port, and that switches the input signal; and the buffer of this switch can be controlled, and the number of cells accumulated in the buffer for each output port can be controlled periodically. And a switch control circuit for comparing the stored value of the cell accumulation number with other cell accumulation numbers to monitor the synchronization deviation and outputting a reset signal when they do not match. Switch monitoring circuit.