JPH08255495A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To increase the speed of random read without inconvenience such as read disturb. [Structure] A plurality of nonvolatile memory cells are connected to each other, and one end side of the first signal line 1 is provided with a selection transistor.
1 is connected to the other end, and the other end is connected to the second via the selection transistor.
The memory cell unit 30 connected to the signal line 12 of
In an EEPROM having a memory cell array arranged in a matrix, after the first signal line 11 is set to the first read potential VA and the second signal line 12 is set to the second read potential VB, When a read voltage is applied to the word line, the voltage change Δ appearing on the first signal line 11
The sense amplifier 40 detects the voltage change ΔVB appearing on VA and the second signal line 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device with an improved data read method.

[0002]

2. Description of the Related Art In recent years, NAND has been used as one of electrically rewritable non-volatile semiconductor devices (EEPROM).
A cell type EEPROM has been proposed. This EEPRO
M is, for example, a plurality of memory cells having an n-channel FET-MOS structure in which a floating gate and a control gate are stacked as a charge storage layer and are connected in series so that their sources and drains are shared by adjacent ones. This is used as one unit and connected to the bit line.

FIG. 27 shows a memory cell array of this type.
It is the top view and equivalent circuit diagram of one NAND cell part. 28 (a) and 28 (b) are each AA 'of FIG. 27 (a).
It is a BB 'sectional view.

A memory cell array composed of a plurality of NAND cells is formed in a p-type silicon substrate (or p-type well) 71 surrounded by an element isolation oxide film 72. One N
Explaining by focusing on the AND cell, in this embodiment, 8
Memory cells M1 to M8 are connected in series to form one NA
It constitutes an ND cell.

Each of the memory cells has a floating gate 74 (74 ₁ , 7 _{1) on} a substrate 71 with a tunnel insulating film 73 interposed therebetween.
4 ₂ , ..., 74 ₈ ) is formed, and the gate insulating film 75 is further formed.
Through the control gate 76 (76 ₁ , 76 ₂ , ..., 7)
6 ₈ ) is formed. The n-type diffusion layers 79, which are the sources and drains of these memory cells, are connected in such a manner that adjacent ones are shared with each other, whereby a plurality of memory cells are connected in series.

First selection gates 74 ₉ and 76 ₉ and second selection gates 74 ₁₀ and 76 ₁₀ formed at the same time as the floating gate and control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. It is provided. The substrate on which the elements are formed is covered with a CVD oxide film 77, and a bit line 78 is arranged thereon. The control gates 76 of the NAND cells are commonly used as control gates CG1, CG2, ..., CG.
It is arranged as 8. These control gate lines become word lines. Select gate 74 _9, 76 ₉ and 74 _10, 7
6 ₁₀ are also select gates SG1 and S continuously in the row direction.
It is arranged as G2.

FIG. 29 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The source line is connected to a reference potential wiring of Al, poly-Si or the like via a contact at one location for every 64 bit lines, for example. This reference potential wiring is connected to the peripheral circuit. Control gate of memory cell and first and second
Selection gates are continuously arranged in the row direction. Normal,
A set of memory cells connected to the control gate is called one page, and a set of pages sandwiched by a set of drain side (first select gate) and source side (second select gate) select gates is one NAND block or It is simply called one block.

The operation of the NAND cell type EEPROM is as follows.

Data writing is performed sequentially from the memory cell farther from the bit line. A boosted write voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential (about 10V) is applied to the control gates of the other non-selected memory cells and the first select gate. Then, 0 V (“0” write) or an intermediate potential (“1” write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell.
When the data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, and electrons are tunnel-injected from the substrate to the floating gate to shift the threshold voltage in the positive direction. When the data is "1", the threshold voltage does not change.

Data erasing is performed in block units at substantially the same time. That is, all the control gates and select gates of the block to be erased are set to 0V, and the boosted potential VppE (about 20V) is applied to the p-type well and the n-type substrate.
VppE is also applied to the control gate and select gate of the block that is not erased. As a result, in the memory cell of the block to be erased, electrons in the floating gate are emitted to the well, and the threshold voltage moves in the negative direction.

In the data read operation, the bit lines are precharged and then floated, the control gates of the selected memory cells are set to 0V, the control gates and selection gates of the other memory cells are set to the power supply voltage Vcc (for example, 3V), and the source. This is performed by setting the line to 0 V and detecting in the bit line whether or not a current flows in the selected memory cell. That is,
If the data written in the memory cell is "0" (threshold voltage Vth> 0 of the memory cell), the memory cell is turned off, so that the bit line maintains the precharge potential, but "1".
If (threshold voltage Vth <0 of memory cell), the memory cell is turned on and the bit line drops from the precharge potential by ΔV. The data of the memory cell is read by detecting these bit line potentials with a sense amplifier.

30A and 30B schematically show a conventional reading method. The memory cell unit is
It is composed of a memory cell and a selection MOS transistor. The signal line 11 corresponds to a bit line, and the signal line 12 corresponds to a source line. The bit line sensing method is shown in FIG.
A single-ended sense amplifier that compares the bit line potential and the reference potential (for example, the circuit threshold value of the inverter or the threshold value of the transistor) as shown in FIG. As described above, the differential sense amplifier may compare and amplify the potential difference between the reference line and the bit line (signal line 11). In any case, in this method, the electric charge of the bit line (signal line 11) is discharged to the ground potential through the source line (signal line 12).

In the NAND cell type EEPROM, since a plurality of memory cells are connected in cascade, the cell current during reading is small. Further, since the control gate and the first and second selection gates of the memory cell are continuously arranged in the row direction, data for one page is simultaneously read out to the bit line.

[0014]

As described above, the conventional NA
ND cell type EEPROM or NAND type mask ROM
Then, since a plurality of memory cells share the source and drain and are connected in series, the resistance at the time of reading is large, and as a result, the cell current Icell flowing through the memory cell at the time of reading is small. Assuming that the capacitance of the bit line is CB and the potential change of the bit line necessary for the sense amplifier to read when the memory cell is "1" is ΔV, the time T required to discharge the bit line in the memory cell is T = CB ・ ΔV /
Icell. Therefore, since the cell current Icell is small, the random read time also becomes long.

As a method for speeding up random read,
A method of increasing the voltage of the control gate higher than Vcc is conceivable. However, in this method, the voltage of the control gate is increased, so that charges are injected from the substrate to the floating gate during repeated reading, and the threshold voltage of the memory cell is increased. Is shifted from the negative erased state to the positive written state. This is called read disturb, and the lower the voltage of the control gate when reading the memory cell,
Lead disturbance can be reduced.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to provide a nonvolatile semiconductor memory device capable of increasing the speed of random read without inconvenience such as read disturb. To provide.

[0017]

In order to solve the above problems, the present invention employs the following configurations.

That is, according to the present invention (Claim 1), one end side is connected directly or via the selection transistor to the first signal line, and the other end side is connected directly or via the selection transistor to the second signal line. A non-volatile semiconductor memory device having a memory cell array in which non-volatile memory cells selected by word lines are arranged in a matrix.
The signal line of is set to the first read potential V1 and
Means for setting the second signal line to the second read potential V2, and applying a predetermined read voltage to the word line with the first and second signal lines set to the potentials V1 and V2, respectively. And a means for detecting a voltage change ΔV1 appearing on the first signal line and a voltage change ΔV2 appearing on the second signal line by applying the read voltage.

According to the present invention (claim 2), a plurality of non-volatile memory cells are connected, one end side is directly connected to the first signal line via a selection transistor, and the other end side is directly or In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units connected to a second signal line via a selection transistor are arranged in a matrix, the first signal line is connected to a first read potential V1.
And a means for setting the second signal line to the second read potential V2 and a state in which the first and second signal lines are set to the voltages V1 and V2 respectively, and the word line is set to a predetermined value. And a voltage change ΔV appearing on the first signal line by applying the read voltage.
1 and means for detecting a voltage change .DELTA.V2 appearing on the second signal line.

The preferred embodiments of the present invention are as follows. (1) A third signal line connected to the first signal line via the first capacitor, a fourth signal line connected to the second signal line via the second capacitor, 1 signal line to 1st
Read potential V1, the second signal line to the second read potential V2, and the third signal line to the third read potential V3.
Means for setting the fourth signal line to the fourth read potential V4, and the first to fourth signal lines for each potential V1.
To V4, the means for applying a predetermined read voltage to the word line and the voltage change .DELTA.V3 on the third signal line to which the voltage change .DELTA.V1 appearing on the first signal line due to the read voltage application is transferred. And the voltage change ΔV2 appearing on the second signal line is transferred to the fourth signal line Δ
It must be equipped with a means for detecting V4. (2) The capacities of the first and second capacitors are almost equal. (3) Non-volatile memory cells shall be composed of electrically rewritable non-volatile memory cells. (4) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and a plurality of memory cells that are adjacent to each other are connected in series to share a source and drain. Constituting a unit. (5) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and one or a duplicate memory cell is connected in parallel so that all sources and drains are shared, and a memory is formed. Configure a cell unit.

According to the present invention (claim 6), one end side is connected directly or via the selection transistor to the first signal line, and the other end side is connected directly or via the selection transistor to the second signal line. A non-volatile semiconductor memory device having a memory cell array in which non-volatile memory cells selected by word lines are arranged in a matrix.
A first signal amplifier that amplifies the potential difference between the signal line and the first reference line and outputs the amplified potential to the third signal line; the second signal line;
A second signal amplifier that amplifies the potential difference of the reference line and outputs it to the fourth signal line, the first signal line to the first read potential V1 ′, and the second signal line to the second read potential. V2 ', a means for setting the third signal line to a third read potential V3', and a fourth signal line to a fourth read potential V4 ',
Means for applying a predetermined read voltage to the word line with the first to fourth signal lines set to the respective potentials V1 'to V4', and to the first signal line by applying the read voltage. The voltage change ΔV1 ′ that appears is amplified by the first signal amplifier and the voltage change ΔV3 ′ that is output to the third signal line and the voltage change ΔV2 that appears on the second signal line are amplified by the second signal amplifier. And a means for detecting a voltage change ΔV4 ′ output to the fourth signal line.

According to the present invention (claim 7), a plurality of nonvolatile memory cells are connected to each other, one end side of which is directly connected to the first signal line through a selection transistor and the other end side of which is directly connected to the first signal line. In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units connected to a second signal line through a selection transistor are arranged in a matrix, a potential difference between a first signal line and a first reference line A first signal amplifier for amplifying and outputting to a third signal line,
A second signal amplifier that amplifies the potential difference between the second signal line and the second reference line and outputs the amplified signal to the fourth signal line, and the first signal line to the first read potential V1 ′ and the second signal amplifier The signal line is set to the second read potential V2 'and the third signal line is set to the third read potential V2'.
3 ', a means for setting the fourth signal line to the fourth read potential V4', and a means for setting the first to fourth signal lines to the respective potentials V.
A means for applying a predetermined read voltage to the word line and a voltage change ΔV1 'appearing on the first signal line due to the application of the read voltage in the first signal amplifier in a state where they are set to 1'-V4' respectively. The voltage change ΔV3 ′ that is amplified and output to the third signal line, and the voltage change ΔV2 that appears on the second signal line.
Is amplified by the second signal amplifier to detect the voltage change ΔV4 ′ output to the fourth signal line.

The preferred embodiments of the present invention are as follows. (1) Third read potential V3 'and fourth read potential V4'
Are almost equal. (2) The non-volatile memory cell shall be composed of electrically rewritable non-volatile memory cells. (3) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and a plurality of memory cells that are adjacent to each other are connected in series to share a source and drain. Constituting a unit. (4) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and one or a duplicate number of memory cells are connected in parallel so that all sources and drains are shared in parallel to form a memory. Configure a cell unit.

[0024]

According to the present invention, the potential of one of the signal lines connected to the memory cell or the memory cell unit is not detected, but the potential of both the signal lines connected to the memory cell or the memory cell unit is detected. That is, after the first and second signal lines connected to the memory cell or the memory cell unit are both held at the precharge potential, the voltage appearing on each signal line is detected by selecting the word line. Therefore, the read signal amount is about 2 compared with the conventional method.
It is possible to increase the number of times by a factor of two, which makes it possible to speed up random read. Further, since the voltage of the control gate at the time of reading is not increased, read disturb does not occur.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a circuit configuration diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

The memory cell unit 30 includes one or a plurality of memory cells and zero or one or a plurality of selection MOs.
It is composed of an S transistor. The memory cell unit 30 has one end connected to the signal line 11 and the other end connected to the signal line 12. The signal lines 11 and 12 are connected to the sense amplifier 40.

Some examples of the memory cell unit are shown in FIGS. FIG. 2A shows a so-called NAND type EEPR.
OM or NAND type mask ROM, FIG.
This is the case where the threshold values of the selection MOS transistors in (a) are different (E-type, I-type). FIG. 2C is an example of a NAND-type non-volatile memory when three selection MOS transistors are provided, and FIG. 2D is an example of a NAND-type non-volatile memory when four selection MOS transistors are provided ( In the figure, the threshold of the E-type selection MOS transistor is positive, and the threshold of the D-type selection MOS transistor is negative).

FIG. 3A shows a NOR type EEPROM or N
It is an OR type mask ROM. 3 (b) and 3 (c) show NO
This is an example of the case where one or two selection MOS transistors are provided in the R-type nonvolatile memory. In FIG. 4A, a source and a drain are shared by a plurality of memory cells, and the memory cells are connected in parallel. FIG. 4 (b) shows a configuration in which a plurality of memory cells are connected in parallel and one selection MOS transistor is coupled (reference: Onoda, H., et al., IE.
DM Tech.Dig, 1992, p.599). FIG. 4 (c) shows a configuration in which a plurality of memory cells are connected in parallel and two selection MOS transistors are coupled (reference: Kume, H., et al ,. IED
M Tech.Dig, 1992, p991, Hisamune, Y., et al., IEDM Te
ch.Dig, 1992, p19).

FIG. 5 shows another example in which a plurality of memory cells are connected in parallel (reference: Bergemont, A., et al ,. IEDM).
Tech.Dig, 1993, p15).

The read operation of this embodiment will be described with reference to FIG. In the conventional read method of the nonvolatile memory device, as shown in FIGS. 30A and 30B, the signal line 11 connected to one end of the memory cell unit is precharged and the signal line 12 connected to the other end is grounded. , The signal line 11 is discharged to the ground line through the memory cell unit. Therefore, the amount of signal read by the sense amplifier 40 is ΔVA.

On the other hand, in this embodiment, first, the signal line 11
To VA and the signal line 12 to VB (VA> VB), both the signal line 11 and the signal line 12 are floated. After that, a desired read voltage is applied to the select gate and the control gate in the memory cell unit 30. If the data written in the memory cell is "0", the memory cell is not turned on, so that the signal lines 11 and 12 maintain the precharge potential. The data written in the memory cell is "1"
Then, the memory cell is turned on, and the charge is transferred from the signal line 11 to the signal line 12 through the memory cell.

As a result, the signal line 11 drops from the precharge potential VA by ΔVA within a certain discharge time, and the signal line 1
2 rises from the precharge potential VB by .DELTA.VB. In the present embodiment, since both the potential change ΔVA of the signal line 11 and the potential change ΔVB of the signal line 12 are detected by the sense amplifier 40, the signal amount becomes ΔVA + ΔVB, which is larger than that of the conventional reading method (signal amount ΔVA). .

Assuming that the signal amount required for reading the data of the memory cell read on the signal line 11 by the sense amplifier 40 is ΔVSA, the read time T is the signal line 1.
For the capacity CA of 1 and the cell current Icell of the memory cell,
T = CA ΔVSA / Icell.

According to the reading method of the present embodiment, the signal read on the signal line within a certain (charge) discharge time of the signal line (that is, the time for applying the selection voltage to the selection gate and control gate of the selected memory cell). The amount is, for example, twice that of the conventional reading method (assuming ΔVA = ΔVB). Therefore, the time required to read the signal amount of ΔVSA is
This is, for example, half that of the conventional reading method. That is, the data reading speed is increased.

The precharge potentials of the signal lines 11 and 12 may be VA = 1.5V and VB = 0V, for example. VB =
It may be 0.5V. If the capacity of the signal line 11 is CA and the capacity of the signal line 12 is CB, then ΔVB = (CA / CB)
ΔVA.

Therefore, the capacitance CA of the signal line 11 and the signal line 1
If the capacitances CB of 2 are almost equal, the signal amount Δ of the signal line 11
Since VA and the signal amount ΔVB of the signal line 12 become equal to each other and the signal amount becomes 2ΔVA, it is twice as large as the conventional reading method. (Second Embodiment) Next, a second embodiment of the present invention will be described.
This embodiment shows an example of the sense amplifier 40, which is constructed as shown in FIGS. Figure 6
FIG. 6A shows a case where the data of the memory cell is “0”.
(B) is a case where the data of the memory cell is "1".

The signal line 11 is connected to the signal line 13 through the capacitor C1.
Further, the signal line 12 is connected to the signal line 14 through the capacitor C2, and the potential difference between the signal lines 13 and 14 is differentially amplified by the differential amplifier DA. 7 to 10 show specific configuration examples of the differential amplifier DA. 7 is a flip-flop type sense amplifier, FIGS. 8A to 8D are current mirror type sense amplifiers, FIGS. 9A and 9B are cross-couple type sense amplifiers, and FIGS. ) Is a differential amplifier configured by combining a plurality of differential amplifiers. here,
Vin1 in FIGS. 7 to 10 may be connected to the signal line 13, and Vin2 may be connected to the signal line 14.

The operation timing of the differential amplifier DA will be described below. First, the differential amplifier DA includes the signal lines 11 and 12.
To VA and VB (VA> VB), and the signal lines 13 and 14 to V
Charge to preA and VpreB (VpreA> VpreB). After precharging, the signal lines 11 to 14 are floated. After that, a predetermined read voltage is applied to the select gate and the control gate in the memory cell unit connected between the signal lines 11 and 12.

The data written in the memory cell is "0".
Then, since the memory cell is turned off, the signal lines 11 to 14 are maintained at the precharge potential (FIG. 6A). afterwards,
The potential difference between the signal lines 13 and 14 is amplified by the differential amplifier DA. For example, when the differential amplifier DA is composed of the flip-flop type sense amplifier shown in FIG. 7, the node N1 has a power supply voltage (for example, 3V) and the node N2 has 0V.

On the other hand, if the data written in the memory cell is "1", the memory cell is turned on, the signal line 11 decreases from the precharge potential by .DELTA.VA, and the signal line 12 increases from the precharge potential by .DELTA.VB. (FIG.6 (b)).
Corresponding to the potential changes of the signal lines 11 and 12, the signal lines 13 and 1
The potential of 4 changes to .DELTA.VA 'and -.DELTA.VB', respectively.
Assuming that the capacity of the signal line 13 is C3, ΔVA 'to ΔVA ×
Since it is C1 / (C1 + C3), if C1 is designed to be sufficiently larger than C3, .DELTA.VA'.about..DELTA.VA. Regarding the potential change of the signal line 14, the signal line 1
4 is larger than the capacitance C4 of 4, the potential change ΔVB ′ of the signal line 14 is substantially the same as the potential change ΔVB of the signal line 12.

The signal amount according to this embodiment is ΔVA '+ ΔVB
Therefore, as long as ΔVA '+ ΔVB'> ΔVA, the read method according to this embodiment has a larger signal amount than the conventional read method (signal amount ΔVA). As a result, the reading speed is increased.

As a result of reading the data of the memory cell, the magnitude relationship between the potentials V3 and V4 of the signal lines 13 and 14 is opposite to that at the time of precharge (that is, V3 <V4). Signal line 13,
After the magnitude relation of the potentials of 14 is determined, the signal lines 13 and 14
The potential difference is amplified by a differential amplifier. As a differential amplifier,
For example, when the flip-flop type sense amplifier as shown in FIG. 7 is used, the node N1 becomes 0V and the node N2 becomes the power supply voltage (for example, 3V).

The precharge potentials of the signal lines 11 to 14 are
For example, the precharge potential VA of the signal line 11 = 1.8V,
Precharge potential VB of signal line 12 = 0.1V, precharge potential VpreA of signal line 13 = 1.8V, signal line 14
The precharge potential VpreB may be set to 1.5V. Also, VA = 1.8V, VB = 0V, VpreA = 1.5V,
VpreB = 1.3V may be used, or VA = 3.5V, V
B = -0.2V, VpreA = 1.2V, VpreB = 0.9V
It may be.

A feedback type bit line bias circuit (FB) may be provided in the sense amplifier circuit as shown in FIG. Transistors Tr1 and Tr2 in FIG. 11 are load transistors. This improves the sensitivity of the sense amplifier. (Embodiment 3) Next, a third embodiment of the present invention will be described.
This embodiment shows another example of the sense amplifier, which is constructed as shown in FIGS. FIG.
2A shows the case of "1" read, and FIG. 12B shows the case of "0" read.

The sense amplifier according to the present embodiment includes the signal line 1
A differential amplifier (first signal amplifier) DA1 that amplifies the potential difference between the potential of 1 and the reference line 21, a differential amplifier (second signal amplifier) DA2 that amplifies the potential difference between the potential of the signal line 12 and the reference line 22, It is composed of a differential amplifier DA1 and a differential amplifier DA3 that amplifies the output difference between the differential amplifier DA2.
Further, in FIG. 12A, the signal line 1 is changed by the control signal φE.
The potential V3 of 3 and the potential V4 of the signal line 14 are equalized to VHF.

The differential amplifier circuit may be, for example, as shown in FIGS. 7 to 10 as in the second embodiment. 13A and 13B show an example of a specific configuration of the sense amplifier circuit. Regarding the input signals of the differential amplifier circuits DA1 and DA2, the signal line 1
1 and 12 are input to Vin1 of FIGS. 7 to 10, and the reference line 2
1 and 22 may be input to Vin2 in FIGS. The outputs of the differential amplifiers DA1 and DA2 may be the node N1 in the case of FIG. 7, and Vout may be the output in the cases of FIGS. Differential amplifier circuit DA
Regarding No. 3, the signal line 13 may be input to Vin1 of FIGS. 7 to 10, and the signal line 14 may be input to Vin2 of FIGS. 7 to 10.

The read operation of this embodiment will be described with reference to FIGS. First, connect the signal lines 11 and 12 to VA
, Precharge to VB. VA and VB are, for example, VA
> VrefA (VrefA; potential of the reference line 21), VB <VrefB
(VrefB; potential of the reference line 22) may be set. Further, by turning on the equalize signal φE, the signal lines 13 and 14 are made to have the same potential (equalize).
After precharging and equalization, the signal lines 11 to 14 are made floating. After that, a read voltage is applied to the select gate and the control gate in the memory cell unit.

The data written in the memory cell is "1".
If so (FIG. 12A), since the memory cell is turned on, the signal line 11 drops from the precharge potential VA, and VA-Δ
It becomes VA (<VrefA). The signal line 12 rises from the precharge potential VB to VB + ΔVB (> VrefB).
That is, as a result of reading the data of the memory cell, the magnitude relationship between the signal line 11 and the reference line 21 is opposite to that during precharge. Furthermore, the magnitude relationship between the signal line 12 and the reference line 22 is also opposite to that during precharge.

When the differential amplifiers DA1 and DA2 are activated, the potential difference between the potential VrefA of the reference line 21 and the potential VA of the signal line 11 is amplified by the differential amplifier DA1, and as a result, the potential of the signal line 13 is equalized potential VHF. To VHF-ΔVHFA. The potential VrefB of the reference line 22,
The potential difference of the potential VB of the signal line 12 is amplified by the differential amplifier DA2, and as a result, the potential of the signal line 14 rises from the equalizing potential VHF to VHF + ΔVHFB.

Next, the potential difference between the signal lines 13 and 14 is amplified by the differential amplifier DA3. For example, the differential amplifier is shown in FIG.
In the case of the current mirror type sense amplifier of (c), the output Vout of the differential amplifier DA3 is lowered.

The data written in the memory cell is "0".
If so (FIG. 12B), the memory cell is turned off.
The signal lines 11 and 12 are kept at the precharge potential. After that, when the differential amplifiers DA1 and DA2 are activated, the potential difference between the potential VrefA of the reference line 21 and the potential VA of the signal line 11 is amplified by the differential amplifier DA1, and as a result, the signal line 1
The potential of 3 rises from the equalizing potential VHF, and VHF + ΔV
Become HFA '. The potential difference between the potential VrefB of the reference line 22 and the potential VB of the signal line 12 is amplified by the differential amplifier DA2, and as a result, the potential of the signal line 14 is equalized potential VHF.
To VHF-ΔVHFB '.

Next, the potential difference between the signal lines 13 and 14 is amplified by the differential amplifier DA3. For example, the differential amplifier is shown in FIG.
In the case of the current mirror type sense amplifier of (c), the output Vout of the differential amplifier DA3 increases.

The precharge potentials of the signal lines 11 and 12 and the reference lines 21 and 22 are, for example, the precharge potential VA of the signal line 11 = 1.7V, the precharge potential VB of the signal line 12 = 0V, and the reference line 21. VrefA = 1.6V and the reference line 22 potential VrefB = 0.1V. Also,
Precharge potential VA = 1.6V of signal line 11, precharge potential VB = 0.2V of signal line 12, potential VrefA of reference line 21 = 1.4V, potential VrefB of reference line 22 = 0.
It may be 4V.

It is preferable that the capacitances of the signal line 11 and the reference line 21 are substantially equal. It is preferable that the signal line 12 and the reference line 22 have substantially the same capacitance. Therefore, the reference lines 21 and 22 may be dummy bit lines. It is preferable that the signal lines 13 and 14 have substantially the same capacitance.

A feedback type bit line bias circuit (FB) may be provided in the sense amplifier circuit as shown in FIG. Transistors Tr1 and Tr2 in FIG. 14 are load transistors. This improves the sensitivity of the sense amplifier.

The input signals of the differential amplifiers DA1 and DA2 may be as shown in FIGS. 15 (a) and 15 (b). That is, signal line 1
1 and 12 are input to Vin2 of FIGS. 7 to 10, and the reference line 2
1 and 22 may be input to Vin1 in FIGS. (Embodiment 4) Next, the read method described in Embodiment 2 is changed to N.
An example of application to an AND type EEPROM will be described below.

FIG. 16 shows a NAND type EE according to this embodiment.
It is a block diagram which shows the structure of PROM. In the figure, 51
(51A, 51B) is a memory cell array as a memory means. Reference numeral 52 is a sense amplifier circuit as a latch means for writing and reading data. 53
(53A, 53B) are row decoders for selecting word lines, 54 is a column decoder for selecting bit lines, 55 is an address buffer, 56 is an I / O sense amplifier, 57 is a data input / output buffer, and 58 is a substrate potential control circuit. Is.

FIG. 17 shows a memory cell array. In the memory cell array according to the present embodiment, the selection gate on the source side is n like the conventional memory cell array (FIGS. 27 and 29).
It is not connected to the source line of the type diffusion layer but is in contact with the bit line. Further, one bit line contact is shared by two NAND strings in the conventional memory cell array, but four N columns are shared in the memory cell array of this embodiment.
Since they are shared by the AND cell columns, the number of bit line contacts in the entire memory cell array does not increase from the conventional memory cell array.

In the memory cell array of this embodiment, 1
Two selections M to connect one NAND cell string and bit line
The thresholds of the OS transistors are set to Vth1, Vth2 (Vth1
> Vth2). High threshold Vth1
Select MOS transistor having (for example, 2V) E-ty
A selection MOS transistor having pe and a low threshold value Vth2 (for example, 0.5 V) is referred to as I-type. The voltage applied to the select gate is a voltage Vsgh (for example, 3V) (Vsgh) that turns on both the I-type transistor and the E-type transistor.
> Vt1, Vt2), and the voltage at which the I-type transistor turns on but the E-type transistor turns off (for example, 1.5 V) (Vt1>Vsgl> Vt2).

As described above, by providing two types of threshold values for the selection MOS transistors and setting two types of voltages to be applied to the selection gates, one of the adjacent NAND cell columns is electrically connected to the bit line and the other is connected to the other at the time of writing or reading. Can be made non-conductive. For example, select gate SG1 to V
When sgh and SG2 are set to Vsgl, the memory cell unit 2 in FIG. 17 is connected to the bit lines on both ends, but the memory cell unit 1 is connected to the bit line on one end side, but is connected to the bit lines on the other end side. Becomes non-conducting. Select gate SG1 to V
When sgl and SG2 are set to Vsgh, the memory cell unit 1 in FIG. 17 is connected to the bit lines on both ends, but the memory cell unit 2 is connected to the bit lines on one end side, but to the bit lines on the other end side. Becomes non-conducting.

An example of the sense amplifier circuit of this embodiment is shown in FIG.
8 shows. In FIG. 18, the bit lines BL1 and BL2 of the memory cell array of FIG. 17 are connected.

In the following, the memory cell unit 1 of FIG.
The read operation of this embodiment will be described by taking as an example the case of reading a memory cell in the memory cell, for example, the memory cell MC11.

FIG. 19 is a timing chart when "1" is read. First, at time t0, the precharge signals PRA1, PRB1, PREA, and PREB are changed from Vss to Vcc, the bit line BL1 is 0V, BL2 is 1.7V, the signal line 13 is 1.7V, and the signal line 14 is 1.5V. It is precharged (time t1).

When the precharge is completed, PRA1, PRB1,
PREA and PREB become Vss, and bit lines BL1 and B
L2 and the signal lines 13 and 14 are in a floating state.
After that, a desired voltage is applied from the row decoder 53 to the selection gate and the control gate (time t2). Control gate C
G1 is 0V, CG2 to CG8 are Vcc (eg 3V), S
G2 is 3V (Vsgh) and SG1 is 1.5V (Vsgl).

When the data written in the memory cell in the memory cell unit 1 is "1", the memory cell transistor is turned on because the threshold value of the memory cell is negative, and the cell current is changed from the bit line BL2 to BL1. Flowing. As a result, for example, the bit line BL2 changes from 1.7V to 1.5V,
The bit line BL1 goes from 0V to 0.2V. If the capacitance of the capacitor C1 is sufficiently larger than the capacitance of the signal line 13,
The potential change of the bit line BL2 is transferred to the signal line 13 and V
3 goes from 1.7V to 1.5V. Similarly, if the capacitance of the capacitor C2 is sufficiently larger than the capacitance of the signal line 14,
The potential change of the bit line BL1 is transferred to the signal line 14 and V
4 goes from 1.5V to 1.7V.

After that, at time t3, φP is 3V and φN is 0V.
V, the CMOS flip-flop is deactivated,
At time t4, φE becomes 3V, so that the CMOS flip-flop of the sense amplifier is equalized and the node N
1, N2 becomes VHF1 (for example, Vcc / 2). Time t5
After SS1 becomes 3V and the bit line and the sense amplifier are connected, φN becomes 0V to 3V and φP becomes 3V to 0V, and the potential difference between the signal lines 13 and 14 is amplified (time t
6). That is, the node N1 becomes 0V and the node N2 becomes 3V. After that, when the column selection signal CSL changes from 0V to 3V, the data latched by the CMOS flip-flop is output to I / O and I / O '(time t7).

FIG. 20 is a timing chart when "0" is read. First, at time t0, the precharge signals PRA1, PRB1, PREA, and PREB are changed from Vss to Vcc, the bit line BL1 is 0V, BL2 is 1.7V, the signal line 13 is 1.7V, and the signal line 14 is 1.5V. It is precharged (time t1).

When precharging is completed, PRA1, PRB1,
PREA and PREB become Vss, and bit lines BL1 and B
L2 and the signal lines 13 and 14 are in a floating state.
After that, a desired voltage is applied from the row decoder 53 to the selection gate and the control gate (time t2). Control gate C
G1 is 0V, CG2 to CG8 are Vcc (eg 3V), S
G2 is 3V (Vsgh) and SG1 is 1.5V (Vsgl). When the data written in the memory cell in the memory cell unit 1 is “0”, the threshold value of the memory cell is positive, the memory cell transistor is turned off and the cell current does not flow, and the bit lines BL2, BL1, Signal lines 13 and 14
Keeps the precharge potential.

After that, at time t3, φP is 3 V and φN is 0V.
V, the CMOS flip-flop is deactivated,
At time t4, φE becomes 3V, so that the CMOS flip-flop of the sense amplifier is equalized and the node N
1, N2 becomes VHF1 (for example, Vcc / 2). Time t5
After SS1 becomes 3V and the bit line and the sense amplifier are connected, φN becomes 0V to 3V and φP becomes 3V to 0V, and the potential difference between the signal lines 13 and 14 is amplified (time t
6). That is, the node N1 becomes 3V and the node N2 becomes 0V. After that, when the column selection signal CSL changes from 0V to 3V, the data latched by the CMOS flip-flop is output to I / O and I / O '(time t7).

In the above embodiment, the bit line BL1 is set to 0V, B
L2 was 1.7V, signal line 13 was 1.7V, and signal line 14 was precharged to 1.5V, but BL2 was 0V, BL1
Is 1.7 V, signal line 14 is 1.7 V, and signal line 3 is 1.5 V.
Reading may be performed by precharging to V.

The memory cell array to which the read method of this embodiment can be applied may be, for example, that shown in FIG. Figure 21
In this memory cell array, three selection MOS transistors are provided for each NAND cell column to form one memory cell unit. Two selection MOSs connected in series
Transistors are E-type (threshold Vth1> 0), D-
type (threshold value Vth2 <0). When reading the memory cell unit 1, SG1 is set to Vsgh1 (Vsg1
h1> Vth3, Vth3; threshold of E'-type transistor), SG2 is 0V, SG3 is Vsgh2 (Vsgh2> Vth1)
). When reading the memory cell unit 2, SG1 is set to Vsgh1 (Vsgh1> Vth3, Vth3; E ′).
-Type transistor threshold), SG3 to 0V, SG
2 may be set to Vsgh2 (Vsgh2> Vth1). (Fifth Embodiment) The read method described in the third embodiment is NAND.
An example in the case of being applied to a type EEPROM will be described below.

Here, the NAND type EE according to this embodiment is
The basic structure of the PROM is the same as that shown in FIG. 16, and the memory cell array of this embodiment is the same as that shown in FIG. Therefore, these explanations are omitted.

FIG. 22 shows an example of the sense amplifier circuit of this embodiment. In FIG. 22, bit lines BL1 and BL2 of the memory cell array of FIG. 17 are connected. Further, in FIG. 22, dummy bit lines (DBL1, DBL2 in FIG. 22) are used as the reference lines 21 and 22 in FIG.

The read operation of this embodiment will be described below by taking the case of reading the memory cell in the memory cell unit 1 of FIG. 17, for example, the memory cell MC11 as an example.

FIG. 23 is a timing chart when "1" is read. First, at time t0, the precharge signals PRA1, PRB1, DPRA1, DPRB1 change from Vss to Vcc, the bit line BL1 is 0V, BL2 is 1.7V, and DB is DB.
L1 is precharged to 0.1V and DBL2 is precharged to 1.6V (time t1).

When precharging is completed, PRA1, PRB1,
DPRA1 and DPRB1 become Vss, and bit lines BL1 and B
L2 is in a floating state. DBL1, DBL2
May be in a floating state or at a constant potential (VpreA, V
It may be fixed to preB). After that, a desired voltage is applied from the row decoder 53 to the selection gate and the control gate (time t2). Control gate CG1 is 0V, CG2-CG
8 is Vcc (for example, 3V), SG2 is 3V (Vsgh), S
G1 becomes 1.5V (Vsgl).

When the data written in the memory cell in the memory cell unit 1 is "1", the memory cell transistor is turned on and the cell current is changed from the bit line BL2 to BL1 because the threshold value of the memory cell is negative. Flowing. As a result, for example, the bit line BL2 changes from 1.7V to 1.5V,
The bit line BL1 goes from 0V to 0.2V.

After that, at time t3, φP becomes 3V and the sense amplifier is inactivated, and at time t4 φEQ becomes 3V, the signal lines 13 and 14 are equalized and become equal in potential. At time t5, SS1 becomes 3V, and after the bit line and the sense amplifier are connected, φP changes from 3V to 0.
Then, the differential amplifier DA1 amplifies the potential difference between the bit line BL2 and the reference line DBL2 and outputs it to the signal line 13 (time t6). In the differential amplifier DA2, the bit line BL1
And the potential difference between the reference line DBL1 and the reference line DBL1 is amplified and output to the signal line 14.

At time t7, the differential amplifier DA3 is activated and the potential difference between the signal lines 13 and 14 is amplified to V
Data is output to out and DVout.

FIG. 24 is a timing chart when "0" is read. First, at time t0, the precharge signals PRA1, PRB1, DPRA1, DPRB1 change from Vss to Vcc, the bit line BL1 is 0V, BL2 is 1.7V, and DB is DB.
L1 is precharged to 0.1V and DBL2 is precharged to 1.6V (time t1).

When precharging is completed, PRA1, PRB1,
DPRA1 and DPRB1 become Vss, and bit lines BL1 and B
L2 is in a floating state. DBL1, DBL2
May be in a floating state or at a constant potential (VpreA, V
It may be fixed to preB). After that, a desired voltage is applied from the row decoder 53 to the selection gate and the control gate (time t2). Control gate CG1 is 0V, CG2-CG
8 is Vcc (for example, 3V), SG2 is 3V (Vsgh), S
G1 becomes 1.5V (Vsgl). When the data written in the memory cell in the memory cell unit 1 is “0”, the memory cell transistor is turned off and the cell current does not flow because the threshold value of the memory cell is positive.
2, BL1 keeps the precharge level.

Thereafter, at time t3, φP becomes 3V to inactivate the sense amplifier, and at time t4 φEQ becomes 3V, so that the signal lines 13 and 14 are equalized and become equal in potential. At time t5, SS1 becomes 3V, and after the bit line and the sense amplifier are connected, φP changes from 3V to 0.
Then, the differential amplifier DA1 amplifies the potential difference between the bit line BL2 and the reference line DBL2 and outputs it to the signal line 13 (time t6). In the differential amplifier DA2, the bit line BL1
And the potential difference between the reference line DBL1 and the reference line DBL1 is amplified and output to the signal line 14.

At time t7, the differential amplifier DA3 is activated and the potential difference between the signal lines 13 and 14 is amplified to V
Data is output to out and DVout.

In the above embodiment, the bit line BL1 is 0V,
BL2 is 1.7V, DBL1 is 0.1V, DBL2 is precharged to 1.6V, but BL2 is 0V,
BL1 may be precharged to 1.7V, DBL2 to 0.1V, and DBL1 to 1.6V.

The structure shown in FIG. 21 can be used also as a memory cell array to which the read method of this embodiment can be applied. (Embodiment 6) In the embodiments so far, the read operation of the present invention has been described by taking the case of read as an example. In the case of verify read for checking whether write (or erase) is sufficiently performed after write (or erase) Also, the present invention is effective.

When a predetermined voltage is applied to the source and drain of the memory cell at the time of writing, as shown in FIG. 25, the transfer gates TRP1 and TRP2 for connecting the sense amplifier and the signal line are made conductive so that the sense amplifier is turned off. A predetermined write voltage may be applied to the signal line. Read, write verify Read, TR1, TR2
Is made non-conductive, and the reading may be performed by the above reading procedure.

Here, the present invention is applied to a NAND type EEPROM.
Write and write verify read in the case of being applied to the above will be described.

The block diagram of the NAND type EEPROM is the same as that of FIG. 16, the memory cell array is the same as that of FIG. 17, and an example of the sense amplifier circuit is FIG. In addition to FIG. 18, in FIG. 26, a verify circuit (T.
Tanaka, et al., IEEE J. Solid-State Circuit, vol.2
9, pp.1366-1373, 1994) is added. In FIG. 26, bit lines BL1 and BL of the memory cell array of FIG.
2 are connected. <Read> A case of reading the memory cells MC11, MC31, MC51 ... In the memory cell unit 1 of FIG. 17 will be described.

For reading, Program1, Progra in FIG.
Set m2 to 0V and transfer gates TRP1, TRP2
Is made non-conductive, and VRFY1 and VRFY2 are set to 0V, SA and SB.
Is set to Vcc, and reading is performed in the same procedure as described in (Example 4).

First, at time t0, the precharge signal PRA
1, PRB1, PREA, PREB are changed from Vss to Vcc, bit line BL2 is precharged to 0V, BL1 is 1.7V, signal line 14 is 1.7V, and signal line 13 is precharged to 1.5V (time t1). .

After precharging is completed, PRA1, PRB1,
PREA and PREB become Vss, and bit lines BL1 and B
L2 and the signal lines 13 and 14 are in a floating state.
After that, a desired voltage is applied from the row decoder 53 to the selection gate and the control gate (time t2). Control gate C
G1 is 0.5 V (verify voltage), CG2 to CG8 are Vcc (for example, 3 V), SG2 is 3 V (Vsgh), SG1
Is 1.5 V (Vsgl).

When the data written in the memory cell in the memory cell unit 1 is "1", the memory cell transistor is turned on because the threshold value of the memory cell is negative, and the cell current is changed from the bit line BL1 to BL2. Flowing. As a result, for example, the bit line BL1 changes from 1.7V to 1.5V,
Bit line BL2 goes from 0V to 0.2V. If the capacitance of the capacitor C1 is sufficiently larger than the capacitance of the signal line 13,
The potential change of the bit line BL2 is transferred to the signal line 13 and V
3 goes from 1.5V to 1.7V. Similarly, if the capacitance of the capacitor C2 is sufficiently larger than the capacitance of the signal line 14,
The potential change of the bit line BL1 is transferred to the signal line 14 and V
4 goes from 1.7V to 1.5V.

After that, at time t3, φP is 3 V and φN is 0.
V, the CMOS flip-flop is deactivated,
At time t4, φE becomes 3V, so that the CMOS flip-flop of the sense amplifier is equalized and the node N
1, N2 becomes VHF1 (for example, Vcc / 2). Time t5
After SS1 becomes 3V and the bit line and the sense amplifier are connected, φN becomes 0V to 3V and φP becomes 3V to 0V, and the potential difference between the signal lines 13 and 14 is amplified (time t
6). That is, the node N1 becomes 3V and the node N2 becomes 0V. Thereafter, when the column selection signal CSL changes from 0V to 3V, the data latched by the CMOS flip-flop is output to I / O and I / O '(time t7).

When "0" is read, the memory cell transistor is turned off and the cell current does not flow because the threshold value of the memory cell is positive, and the bit lines BL2, BL1 and the signal line 1
3, 14 keep the precharge potential, and N1 is 0 after sensing
V and N2 become 3V. <Write> Memory cells MC11, MC31, MC in FIG.
The writing procedure when writing to 51 ... Will be described below.

Memory cell MC in memory cell unit 1
The data to be written in 11, MC31, MC51 ... Is latched in the sense amplifier circuit. In other words, when "1" is written, the node N1 is 0V, N2 is 3V, and when "0" is written, the node N1 is 3V and N2 is 0V.

When the write operation is started, first at time t1, S
G1 and SG2 are connected to Vsgl (I type selection gate is conductive,
E type select gate is non-conducting voltage), CG1 to CG
Set 8 to Vcc. In this embodiment, the memory cell unit 1
When writing data to the memory cells MC11, MC31, MC51 ... In the memory cell MC in the memory cell unit 2
Do not write to 01, MC21, MC41 .... For that purpose, it is necessary to charge the channels of the memory cells MC01, MC21, MC41 ... From the bit lines BL0, BL2, BL4.

In this embodiment, the bit lines BL0, BL2,
BL4 ... is charged from VpreA of the sense amplifier to Vcc.
That is, by setting Program1, PREA, SS1 to Vcc (or Vcc + Vth to prevent threshold drop) and SA to Vss, the bit lines BL0, BL2 ... Are disconnected from the latch, and the write protection voltage (Vcc or V
cc-Vth) are transferred to the channels of the memory cells of the memory cell unit 2 through the bit lines BL0, BL2 ... As a result, the channels of the memory cells MC01, MC21, MC41 ... Are charged to Vcc-Vth.

On the other hand, bit lines BL1, BL3, BL5 ...
For SS1, SB, Program2, Vcc (or Vcc
+ Vth), PREB, and VRFY2 are set to Vss, depending on the data latched in the sense amplifier circuit,
A potential of Vcc or Vss (0V) is applied. Thus, for example, when "0" is written in the memory cell MC11, the bit line BL1 is set to 0V and the channel of the memory cell MC11 is set to 0V. When writing "1" to the memory cell MC11, the bit line BL1 is set to Vcc.
(For example, 3 V) or Vcc-Vth to set the memory cell MC11.
Will be charged to Vcc-Vth.

Memory cell unit 2 in which writing is not performed
Since the select gates ST01, ST21, ST41 ... Of them are E-type, they are turned off, and the channels of the memory cells MC01, MC21, MC41 ... Float at Vcc-Vth.

Memory cell MC11 for writing "1",
MC31, MC51 ... Select MOS transistors ST11, S
The drains on the memory cell side of T31, ST51 ... Are Vcc-Vth
(For example, the threshold voltage of the I-type transistor is 0.8
V is 3-0.8 = 2.2V), the source on the bit line contact side is Vcc (for example, 3V), and the select gate SG
Since 1 is Vsgl (for example, 1.5 V), the selection MOS transistors ST11, ST31, ST51, ... Are turned off. As a result, the memory cells MC11,
The channels of MC31, MC51 ... Become floating.

When "0" is written in the memory cells MC11, MC31, MC51 ..., The selection gate SG1 of the selection MOS transistors ST11, ST31, ST51 ... Is Vsg.
l (for example, 1.5V), and the source and drain are 0V, so that the selection MOS transistors ST11, ST31, ST51 ...
Is turned on, and the channel of the memory cell is kept at 0V.

After that, at time t2, the control gates CG1 to CG are
G8 is changed from Vcc to the intermediate potential VM (about 10V). Then, the memory cells MC01, MC21, M which are not written
C41 ... and memory cells MC11, M for writing "1"
Since the channels of C31, MC51 ... Are in a floating state, Vcc is generated by capacitive coupling between the control gate and the channel.
It rises from -Vth to an intermediate potential (about 10V). "0"
The channels of the memory cells MC11, MC31, MC51, ... To be written are 0V because the bit line is 0V.

After the channel of the memory cell in which write unselection and "1" write are performed is boosted from Vcc-Vth to the intermediate potential, the control gate CG1 is set to the intermediate potential VM at time t3.
To write voltage Vpp (20V). Then, the memory cells MC01, MC21, MC41 which are not written
... and memory cells MC11 and MC for writing "1"
Since the channels of 31, MC51 ... Have an intermediate potential (about 10V) and the control gate CG1 is of Vpp (about 20V), these memory cells are not written, but the channels of the memory cells MC11, MC31, MC51 ... Is 0V,
Since the control gate is Vpp (about 20 V), electrons are injected from the substrate into the floating gate to perform "0" writing.

After the writing is completed, the control gate, the selection gate and the bit line are sequentially discharged to complete the writing operation. <Write-verify read> After the write is completed, a write-verify operation is performed to check whether the write has been sufficiently performed. At the time of verify read, as in the case of read, Program1 and Program2 become Vss, and TRP1 and TR
P2 becomes non-conductive. The first half of the verify read is performed similarly to the normal read.

At time t0, precharge signals PRA1, PRA
B1, PREA, and PREB are changed from Vss to Vcc, bit line BL1 is 1.7V, BL2 is 0V, and signal line 13 is 1.V.
The signal line 14 is precharged to 5V and 1.7V (time t1).

When precharging is completed, PRA1, PRB1,
PREA and PREB become Vss, and bit lines BL1 and B
L2 and the signal lines 13 and 14 are in a floating state.
After that, a desired voltage is applied from the row decoder 53 to the selection gate and the control gate (time t2). Control gate C
G1 is 0V, CG2 to CG8 are Vcc (eg 3V), S
G2 is 3V (Vsgh) and SG1 is 1.5V (Vsgl).

When the memory cell in the memory cell unit 1 is written with "1" or is insufficiently written with "0", the threshold voltage of the memory cell is negative and the memory cell transistor is turned on. Current flows from bit line BL1 to BL2. As a result, for example, the bit line BL1 changes from 1.7V to 1.5V, and the bit line BL2 changes from 0V to 0.2V. If the capacitance of the capacitor C2 is sufficiently larger than the capacitance of the signal line 14, the potential change of the bit line BL1 is transferred to the signal line 14 and V4 changes from 1.7V to 1.5V.
become. Similarly, if the capacitance of the capacitor C1 is sufficiently larger than the capacitance of the signal line 13, the potential change of the bit line BL2 is transferred to the signal line 13 and V3 is changed from 1.5V to 1.7V.
become.

When "0" is written sufficiently, the threshold voltage of the memory cell is positive, so that the memory cell transistor does not conduct, and the bit lines BL1, BL2, V3.
V4 maintains the precharge potential. That is, V4 is 1.7.
V and V3 are 1.5V.

After bit line discharge, verify signal VRFY
2 becomes 3V, and memory cells MC11, MC31, MC51 ...
If the data written to the node is "1", the node V4
Is charged to near 3V. Here, the voltage level of the charging performed by the verify signal is the voltage V3 of 1.7V.
It should be larger.

After that, φP becomes 3V and φN becomes 0V,
The CMOS flip-flop FF is inactivated and .phi.E becomes 3V, so that the CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). After that, SA and SB become 3V,
After the signal lines 13 and 14 and the sense amplifier are connected, φN
Changes from 0V to 3V, φP changes from 3V to 0V, and signal line 13
And the potential difference of the signal line 14 is amplified, and the rewritten data is latched by the sense amplifier.

The present invention is also effective in the memory cell array of FIG. 21 as in the case of the fourth embodiment.

[0112]

As described in detail above, according to the present invention, the potential of one of the signal lines connected to the memory cell or the memory cell unit is not detected, but both of the signal lines connected to the memory cell or the memory cell unit are detected. Since the configuration for detecting the potential of is adopted, the read signal amount can be increased to about twice as much as that of the conventional method, thereby increasing the speed of random read without inconvenience such as read disturb. It becomes possible to measure.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a nonvolatile semiconductor memory device according to a first embodiment.

FIG. 2 is a circuit diagram showing an example of a NAND type memory cell unit.

FIG. 3 is a circuit diagram showing an example of a NOR type memory cell unit.

FIG. 4 is a circuit diagram showing an example of a memory cell unit in which memory cells are connected in parallel.

FIG. 5 is a circuit diagram showing another example of a memory cell unit in which memory cells are connected in parallel.

FIG. 6 is a circuit diagram when “0” reading and “1” reading are performed in the second embodiment.

FIG. 7 is a circuit diagram showing a flip-flop type sense amplifier as an example of a differential amplifier.

FIG. 8 is a circuit diagram showing a current mirror type sense amplifier as an example of a differential amplifier.

FIG. 9 is a circuit diagram showing a cross-couple type sense amplifier as an example of a differential amplifier.

FIG. 10 is a circuit diagram showing a differential amplifier configured by combining a plurality of differential amplifiers.

FIG. 11 is a circuit diagram showing another example of a sense amplifier.

FIG. 12 is a circuit diagram when “1” reading and “0” reading are performed in the third embodiment.

FIG. 13 is a circuit diagram showing a specific configuration example of a sense amplifier when performing “0” read and “1” read in the third embodiment.

FIG. 14 is a circuit diagram showing another example of the sense amplifier of the third embodiment.

FIG. 15 is a circuit diagram showing another example in which “1” read and “0” read are performed in the third embodiment.

FIG. 16 is a NAND type EE according to fourth to sixth embodiments.
The block diagram which shows the basic composition of PROM.

FIG. 17 is a circuit diagram showing a configuration of a memory cell array according to fourth to sixth embodiments.

FIG. 18 is a circuit diagram showing a sense amplifier according to a fourth embodiment.

FIG. 19 is an operation timing chart for explaining a “1” read operation of the fourth embodiment.

FIG. 20 is an operation timing chart for explaining a “0” read operation of the fourth embodiment.

FIG. 21 is a diagram showing another configuration example of the memory cell array according to the fourth to sixth embodiments.

FIG. 22 is a circuit diagram showing a sense amplifier of a fifth embodiment.

FIG. 23 is an operation timing chart for explaining a “1” read operation of the fifth embodiment.

FIG. 24 is an operation timing chart for explaining a “0” read operation of the fifth embodiment.

FIG. 25 is a circuit diagram showing a sense amplifier of a sixth embodiment.

FIG. 26 is a circuit diagram showing a sense amplifier according to a sixth embodiment.

FIG. 27 is a plan view and an equivalent circuit diagram showing a cell configuration of a conventional NAND type EEPROM.

28 is a sectional view taken along the line AA ′ and BB ′ of FIG.

FIG. 29 is an equivalent circuit diagram of a memory cell array of a conventional NAND type EEPROM.

FIG. 30 is a circuit diagram for explaining a reading method of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 11 ... 1st signal line 12 ... 2nd signal line 13 ... 3rd signal line 14 ... 4th signal line 21 ... 1st reference line 22 ... 2nd reference line 30 ... Memory cell unit 40 ... Sense Amplifier C1, C2 ... Capacitor DA1 ... First signal amplifier DA2 ... Second signal amplifier

Claims (11)

[Claims] 1. A non-volatile memory having one end connected to a first signal line directly or via a selection transistor and the other end connected to a second signal line directly or via a selection transistor and selected by a word line. In a nonvolatile semiconductor memory device having a memory cell array in which memory cells are arranged in a matrix, a first signal line is set to a first read potential V1 and a second signal line is set to a second read potential. V2 and means for setting the first and second signal lines to the respective potentials V1 and V2
Means for applying a predetermined read voltage to the word line and a voltage change ΔV1 appearing on the first signal line and a voltage change ΔV2 appearing on the second signal line when the read voltage is applied. A non-volatile semiconductor memory device comprising: 2. A plurality of nonvolatile memory cells are connected to each other, one end side of which is directly connected to the first signal line via a selection transistor and the other end side of which is directly connected to the second signal line via a selection transistor. In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units connected to lines are arranged in a matrix, a first signal line is set to a first read potential V1 and a second signal line is set. To a second read potential V2 and the first and second signal lines are connected to the respective voltages V1 and V2.
Means for applying a predetermined read voltage to the word line and a voltage change ΔV1 appearing on the first signal line and a voltage change ΔV2 appearing on the second signal line by the application of the read voltage are detected. A non-volatile semiconductor memory device comprising: 3. A non-volatile memory having one end connected to a first signal line directly or via a selection transistor and the other end connected to a second signal line directly or via a selection transistor and selected by a word line. In a non-volatile semiconductor memory device having a memory cell array in which memory cells are arranged in a matrix, a third signal line connected to a first signal line via a first capacitor, and a second signal line. A fourth signal line connected to the second signal line via a second capacitor, the first signal line to the first read potential V1, the second signal line to the second read potential V2, and the third signal line. Means for setting the line to the third read potential V3 and the fourth signal line to the fourth read potential V4, and with the first to fourth signal lines set to the potentials V1 to V4, respectively. , A predetermined reading on the word line Means for applying an output voltage, and a voltage change ΔV of the third signal line to which the voltage change ΔV1 appearing on the first signal line due to the application of the read voltage is transferred.
And a means for detecting a voltage change ΔV4 of the fourth signal line to which the voltage change ΔV2 appearing on the second signal line has been transferred. 4. A plurality of non-volatile memory cells are connected, one end side is connected directly or via a selection transistor to a first signal line, and the other end side is connected directly or via a selection transistor to a second signal line. In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units connected to a line are arranged in a matrix, a third signal line connected to a first signal line via a first capacitor , A fourth signal line connected to the second signal line via a second capacitor, the first signal line to a first read potential V1, and the second signal line to a second read potential V2. Means for setting the third signal line to the third read potential V3 and the fourth signal line to the fourth read potential V4, and the first to fourth signal lines for the respective potentials V1 to V4. With each set to Means for applying a predetermined read voltage to the voltage line, and a voltage change .DELTA.V of the third signal line to which the voltage change .DELTA.V1 appearing on the first signal line due to the application of the read voltage is transferred.
And a means for detecting a voltage change ΔV4 of the fourth signal line to which the voltage change ΔV2 appearing on the second signal line has been transferred. 5. The nonvolatile semiconductor memory device according to claim 3, wherein the first capacitor and the second capacitor have substantially the same capacitance. 6. A non-volatile memory having one end directly connected to a first signal line via a selection transistor and the other end directly connected to a second signal line via a selection transistor and selected by a word line. In a non-volatile semiconductor memory device having a memory cell array in which memory cells are arranged in a matrix, a first potential that amplifies a potential difference between a first signal line and a first reference line and outputs the amplified potential to a third signal line. The signal amplifier, the second signal amplifier that amplifies the potential difference between the second signal line and the second reference line and outputs the amplified signal to the fourth signal line, and the first signal line to the first read potential V1 '. , Means for setting the second signal line to the second read potential V2 ', the third signal line to the third read potential V3', and the fourth signal line to the fourth read potential V4 '. , The first to fourth signal lines are connected to the respective potentials V1 'to V4'. A means for applying a predetermined read voltage to the word line in each set state, and a voltage change ΔV1 ′ appearing on the first signal line due to the application of the read voltage is amplified by a first signal amplifier to generate a third voltage. Means for amplifying the voltage change ΔV3 ′ output to the second signal line and the voltage change ΔV2 appearing on the second signal line by the second signal amplifier to detect the voltage change ΔV4 ′ output to the fourth signal line. A non-volatile semiconductor memory device comprising: 7. A plurality of nonvolatile memory cells are connected to each other, one end side of which is directly connected to the first signal line via a selection transistor and the other end side of which is directly connected to the second signal line via a selection transistor. In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units connected to lines are arranged in a matrix, a third signal line is amplified by amplifying a potential difference between the first signal line and the first reference line. A first signal amplifier for outputting to the first signal line, a second signal amplifier for amplifying a potential difference between the second signal line and the second reference line and outputting the amplified signal to the fourth signal line, and a first signal line for the first signal line. Read potential V1 ', the second signal line to the second read potential V2', the third signal line to the third read potential V3 ', and the fourth signal line to the fourth read potential V4'. And a first to a fourth signal line for each of the above Means for applying a predetermined read voltage to the word line and the voltage change ΔV1 'appearing on the first signal line due to the application of the read voltage in the first signal amplifier in a state where the read voltage is set to V1' to V4 'respectively. The voltage change ΔV3 ′ that is amplified by and is output to the third signal line and the voltage change ΔV2 that appears on the second signal line is amplified by the second signal amplifier and is output to the fourth signal line. A nonvolatile semiconductor memory device comprising: means for detecting ΔV4 ′. 8. The sixth read potential V3 ′ and the fourth read potential V4 ′ are substantially equal to each other, as claimed in claim 6 or 7.
The nonvolatile semiconductor memory device described. 9. The nonvolatile memory cell according to claim 1, wherein the nonvolatile memory cell is an electrically rewritable nonvolatile memory cell. Semiconductor memory device. 10. The non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and a plurality of memory cells adjacent to each other are connected in series so as to share a source and a drain. 10. The non-volatile semiconductor memory device according to claim 9, wherein the memory cell unit is configured as a memory cell unit. 11. The non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and one or duplicate memory cells are connected in parallel so that all sources and drains are shared. 10. The non-volatile semiconductor memory device according to claim 9, wherein the memory cell unit is configured to be formed.