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JPH08255926A - Semiconductor light emitting element and fabrication thereof - Google Patents

Semiconductor light emitting element and fabrication thereof

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Publication number
JPH08255926A
JPH08255926A JP5768795A JP5768795A JPH08255926A JP H08255926 A JPH08255926 A JP H08255926A JP 5768795 A JP5768795 A JP 5768795A JP 5768795 A JP5768795 A JP 5768795A JP H08255926 A JPH08255926 A JP H08255926A
Authority
JP
Japan
Prior art keywords
layer
semiconductor
light emitting
type
sapphire substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5768795A
Other languages
Japanese (ja)
Inventor
Masayuki Sonobe
雅之 園部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP5768795A priority Critical patent/JPH08255926A/en
Publication of JPH08255926A publication Critical patent/JPH08255926A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain a high performance semiconductor light emitting element, and a fabrication method thereof, in which contamination due to etching of gallium nitride based semiconductor layer is prevented. CONSTITUTION: The semiconductor light emitting element comprises a semiconductor layer of gallium nitride based compound having an emission layer comprising an n-type layer 13 and a p-type layer 14 formed on a sapphire substrate 11, and electrodes connected with the n-type layer and the p-type layer 14. One electrode 15 on the p-side or n-side is connected with the surface layer of a laminated semiconductor layer and the other electrode 16 on the n-side or p-side is provided on the rear surface of the sapphire substrate 11 while being connected with the semiconductor layer through a through hole 17 made on the saphire substrate 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体発光素子およびそ
の製法に関する。さらに詳しくは、青色発光に好適なチ
ッ化ガリウム系化合物半導体からなる半導体発光素子お
よびその製法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device and its manufacturing method. More specifically, it relates to a semiconductor light emitting device made of a gallium nitride based compound semiconductor suitable for blue light emission and a method for manufacturing the same.

【0002】ここにチッ化ガリウム系化合物半導体と
は、III 族元素のGaとV族元素のNとの化合物または
III 族元素のGaの一部がAl、Inなど他のIII 族元
素と置換したものおよび/またはV族元素のNの一部が
P、Asなど他のV族元素と置換した化合物からなる半
導体をいう。
Here, a gallium nitride compound semiconductor is a compound of a group III element Ga and a group V element N or
A semiconductor made of a compound in which a part of Ga of the group III element is replaced with another group III element such as Al and In and / or a part of N of the group V element is replaced with another group V element such as P and As. Say.

【0003】また、半導体発光素子とは、pn接合また
はダブルヘテロ接合を有する発光ダイオード(以下、L
EDという)、スーパルミネッセントダイオード(以
下、SLDという)または半導体レーザダイオード(以
下、LDという)などの光を発生する半導体素子をい
う。
A semiconductor light emitting element is a light emitting diode having a pn junction or a double heterojunction (hereinafter referred to as L
A semiconductor element that emits light, such as an ED), a superluminescent diode (hereinafter, SLD), or a semiconductor laser diode (hereinafter, LD).

【0004】[0004]

【従来の技術】従来青色のLEDは赤色や緑色に比べて
輝度が小さく実用化に難点があったが、近年チッ化ガリ
ウム系化合物半導体を用い、Mgをドーパントした低抵
抗のp型半導体層がアニール処理または電子線照射処理
によりえられたことにより、輝度が向上し脚光をあびて
いる。
2. Description of the Related Art Conventionally, blue LEDs have a lower brightness than red and green and are difficult to put into practical use. In recent years, however, gallium nitride compound semiconductors have been used, and a low resistance p-type semiconductor layer doped with Mg has been formed. By being obtained by the annealing treatment or electron beam irradiation treatment, the brightness is improved and the spotlight is exposed.

【0005】ところで、チッ化ガリウム系のLEDは、
たとえば図5に示されるような構造になっている。この
LEDを製造するには、まずサファイア(Al2 3
結晶)基板21に400〜700℃の低温で有機金属化
合物気相成長法(以下、MOCVD法という)によりキ
ャリアガスH2 とともに有機金属化合物ガスであるトリ
メチルガリウム(以下、TMGという)またはトリエチ
ルガリウム(TEG)およびアンモニア(NH3 )を供
給し、n型のGaNからなる低温バッファ層22を形成
し、ついで900〜1200℃の高温で同じガスを供給
し同じ組成のn型のGaNからなる高温バッファ層23
を形成する。
By the way, gallium nitride LEDs are
For example, the structure is as shown in FIG. In order to manufacture this LED, first, an organic metal compound is formed on a sapphire (Al 2 O 3 single crystal) substrate 21 at a low temperature of 400 to 700 ° C. together with a carrier gas H 2 by a metal organic compound vapor phase growth method (hereinafter, referred to as MOCVD method). Compound gas trimethylgallium (hereinafter referred to as TMG) or triethylgallium (TEG) and ammonia (NH 3 ) are supplied to form a low temperature buffer layer 22 made of n-type GaN, and then at a high temperature of 900 to 1200 ° C. High temperature buffer layer 23 made of n-type GaN having the same composition and supplying the same gas
To form.

【0006】ついで前述のガスに、さらにトリメチルア
ルミニウム(以下、TMAという)を導入して、n型の
Alx Ga1-x N(0<x<1)層を成膜し、タブルヘ
テロ接合形成のためのn型クラッド層24を形成する。
これらのn型層を形成するには、前述の各成分ガスにS
iをSiH4 ガスとして導入することにより形成され
る。
Then, trimethylaluminum (hereinafter referred to as TMA) is further introduced into the above-mentioned gas to form an n-type Al x Ga 1-x N (0 <x <1) layer to form a tabular heterojunction. An n-type clad layer 24 for forming is formed.
To form these n-type layers, S is added to each of the above component gases.
It is formed by introducing i as SiH 4 gas.

【0007】つぎに、バンドギャップエネルギーがクラ
ッド層のそれより小さくなる材料、たとえば前述の原料
ガスのTMAに代えてトリメチルインジウム(以下、T
MIという)を導入し、Gay In1-y N(0<y≦
1)からなる活性層25を形成する。
Next, a material having a bandgap energy smaller than that of the clad layer, for example, trimethylindium (hereinafter T
MI) is introduced, and Ga y In 1-y N (0 <y ≦
An active layer 25 consisting of 1) is formed.

【0008】ついで、n型クラッド層24の形成と同じ
原料ガスで、不純物原料ガスをSiH4 に代えてp型不
純物としてのMgまたはZnのためのビスシクロペンタ
ジエニルマグネシウム(Mg(C552)(以下、C
2 Mgという)またはジメチル亜鉛(以下、DMZn
という)の有機金属化合物ガスを加えて反応管に導入
し、p型Alx Ga1-x Nからなるp型クラッド層26
を形成する。これによりn型クラッド層24と活性層2
5とp型のクラッド層26とによりダブルヘテロ接合が
形成される。
[0008] Then, in the same feed gas with the formation of the n-type cladding layer 24, biscyclopentadienyl magnesium (Mg (C 5 H for Mg or Zn in the impurity source gas as a p-type impurity in place of SiH 4 5 ) 2 ) (hereinafter C
p 2 Mg) or dimethyl zinc (hereinafter DMZn)
Said) and introducing into the reaction tube, the p-type cladding layer 26 made of p-type Al x Ga 1-x N.
To form. Thereby, the n-type cladding layer 24 and the active layer 2
5 and the p-type cladding layer 26 form a double heterojunction.

【0009】さらにキャップ層27とするため、前述の
バッファ層23と同様のガスで、不純物原料ガスとして
Cp2 MgまたはDMZnを供給してp型のGaN層を
気相成長させる。
Further, in order to form the cap layer 27, Cp 2 Mg or DMZn is supplied as an impurity source gas with the same gas as that of the buffer layer 23 described above to vapor-deposit a p-type GaN layer.

【0010】そののち、SiO2 などの保護膜を半導体
の成長層表面全面に設け、400〜800℃、15〜6
0分間程度のアニールを行い、p型クラッド層26およ
びキャップ層27の活性化を図る。ついで保護膜を除去
したのちn側の電極を形成するため、レジストを塗布し
パターニングして、図5に示されるように、成長した各
半導体層の一部を塩素系プラズマによる反応性イオンエ
ッチングであるドライエッチングを行ってn型GaN層
であるバッファ層23を露出させる。ついでAl、Au
などの金属膜をスパッタリングなどにより形成してp側
およびn側の両電極28、29を形成し、ダイシングす
ることによりLEDチップを形成している。
After that, a protective film such as SiO 2 is provided on the entire surface of the growth layer of the semiconductor, and the temperature is 400 to 800 ° C. for 15 to 6
Annealing is performed for about 0 minutes to activate the p-type cladding layer 26 and the cap layer 27. Then, after removing the protective film, in order to form an n-side electrode, a resist is applied and patterned, and as shown in FIG. 5, a part of each grown semiconductor layer is subjected to reactive ion etching by chlorine-based plasma. A certain dry etching is performed to expose the buffer layer 23, which is an n-type GaN layer. Then Al, Au
An LED chip is formed by forming a metal film such as by sputtering to form the p-side and n-side electrodes 28 and 29, and dicing.

【0011】[0011]

【発明が解決しようとする課題】従来のチッ化ガリウム
系化合物半導体を用いた半導体発光素子は、前述のよう
に、基板としてサファイア基板を用いているため、裏面
側からn側電極をとることができず、積層された半導体
層の一部をエッチングしてn型半導体層であるバッファ
層23を露出させ、その露出面にn側電極29を設けて
いる。このエッチングを行うのに、チッ化ガリウム系半
導体層をウェットエッチングにより行うには250℃以
上で行わなければならず、作業が大変である。またドラ
イエッチングで行うと、半導体層の表面がダメージを受
け、表面があれるとともに抵抗が増大する。とくにドラ
イエッチングはマスクとしてのSiO2 などとの選択比
がよいという理由からCl2 とBCl3 の混合ガスなど
の塩素系プラズマで行われているが、Cl2 は半導体層
の組成にAlがあると、AlとClとが化合して塩化ア
ルミニウムが生成され、エッチングにより露出した面に
付着する。このAlとClとの化合物がエッチングによ
り露出した側壁に付着すると、発生する光の出力を低下
させたり、散乱させたりするという問題がある。さらに
電極形成時に接触抵抗を増大させたり、p層とn層間の
リークの原因となり、印加電力をロスするという問題が
ある。
Since the conventional semiconductor light emitting device using the gallium nitride based compound semiconductor uses the sapphire substrate as the substrate as described above, the n-side electrode can be taken from the back surface side. Therefore, a part of the stacked semiconductor layers is etched to expose the buffer layer 23, which is an n-type semiconductor layer, and the n-side electrode 29 is provided on the exposed surface. To perform this etching, the gallium nitride-based semiconductor layer must be wet-etched at a temperature of 250 ° C. or higher, which is a difficult task. Further, when the dry etching is performed, the surface of the semiconductor layer is damaged, and the resistance increases as the surface is damaged. In particular, dry etching is performed with chlorine-based plasma such as a mixed gas of Cl 2 and BCl 3 because of its good selection ratio with respect to SiO 2 as a mask, but Cl 2 has Al in the composition of the semiconductor layer. And Al and Cl combine to generate aluminum chloride, which adheres to the surface exposed by etching. If the compound of Al and Cl adheres to the side wall exposed by etching, there is a problem that the output of generated light is reduced or scattered. Further, there is a problem that the contact resistance is increased at the time of forming the electrode, or it causes leakage between the p layer and the n layer, resulting in loss of applied power.

【0012】さらにCl2 ガスは一般に有毒で、取扱い
が難しいという問題がある。
Further, there is a problem that Cl 2 gas is generally toxic and difficult to handle.

【0013】本発明はこのような問題を解決し、サファ
イア基板の裏面側から他方の電極を取り出しチッ化ガリ
ウム系半導体層のエッチングをしなくてもよい半導体発
光素子を提供することを目的とする。
It is an object of the present invention to solve such a problem and provide a semiconductor light emitting device in which the other electrode is taken out from the back surface side of the sapphire substrate and the gallium nitride based semiconductor layer does not have to be etched. .

【0014】本発明のさらに他の目的は、チッ化ガリウ
ム系半導体層のエッチングをしても、半導体層にダメー
ジを与えることなく、しかもエッチング面などにコンタ
ミネーションが付着しないようにして高特性の半導体発
光素子がえられる製法を提供することを目的とする。
Still another object of the present invention is that even if the gallium nitride based semiconductor layer is etched, the semiconductor layer is not damaged, and contamination is not adhered to the etching surface, etc. It is an object of the present invention to provide a method for producing a semiconductor light emitting device.

【0015】[0015]

【課題を解決するための手段】本発明の半導体発光素子
は、サファイア基板上に少なくともn型層およびp型層
を含み発光層を有するチッ化ガリウム系化合物半導体層
が積層され、前記n型層およびp型層にそれぞれ接続さ
れる電極が設けられてなる半導体発光素子であって、前
記積層された半導体層の表層に接続してp側またはn側
の一方の電極が設けられ、前記サファイア基板に設けら
れた貫通孔を介して露出した半導体層に接続して該サフ
ァイア基板の裏面にn側またはp側の他方の電極が設け
られている。
In the semiconductor light emitting device of the present invention, a gallium nitride-based compound semiconductor layer having a light emitting layer including at least an n-type layer and a p-type layer is laminated on a sapphire substrate, and the n-type layer is formed. And a p-type layer, each of which is provided with an electrode connected to the p-type layer, wherein the p-side or n-side electrode is provided so as to be connected to a surface layer of the stacked semiconductor layers. The other electrode on the n-side or the p-side is provided on the back surface of the sapphire substrate so as to be connected to the exposed semiconductor layer through the through-hole provided in.

【0016】ここに発光層とは、クラッド層に挟まれた
活性層に限らず、pn接合のLEDなどでは、電子と正
孔の結合により光を発生するpn接合近傍をも含む意味
である。
Here, the light emitting layer is not limited to an active layer sandwiched between clad layers, and is meant to include the vicinity of a pn junction that generates light by the combination of electrons and holes in a pn junction LED or the like.

【0017】本発明の半導体発光素子の製法は、サファ
イア基板上に少なくともn型層およびp型層を含み発光
層を有するチッ化ガリウム系化合物半導体を積層し、前
記n型層およびp型層にそれぞれ接続される電極を設け
る半導体発光素子の製法であって、前記電極の一方を前
記積層された半導体層の表面に設け、前記電極の他方を
前記サファイア基板に集束イオンビームにより設けた貫
通孔を介して露出した半導体層に接触するように前記サ
ファイア基板の裏面に電極材料を付着することにより設
けることを特徴とする。
According to the method of manufacturing a semiconductor light emitting device of the present invention, a gallium nitride based compound semiconductor having at least an n-type layer and a p-type layer and having a light-emitting layer is laminated on a sapphire substrate, and the n-type layer and the p-type layer are formed. A method of manufacturing a semiconductor light-emitting device, wherein electrodes to be connected to each other are provided, wherein one of the electrodes is provided on a surface of the laminated semiconductor layers, and the other of the electrodes has a through hole provided by a focused ion beam on the sapphire substrate. It is characterized in that an electrode material is attached to the back surface of the sapphire substrate so as to come into contact with the semiconductor layer exposed through the electrode material.

【0018】[0018]

【作用】本発明の半導体発光素子によれば、サファイア
基板の裏面側からサファイア基板に貫通孔を設けて下層
の半導体層の一部を裏面側に露出させることにより、一
方の電極は積層された半導体層の表層(たとえばp型)
に設けられ、他方の電極はサファイア基板の裏面に設け
られることにより貫通孔を介して半導体層の下層(たと
えばn型)に接続される。そのため半導体層をエッチン
グしないで両電極が設けられ、同じチップ面積に対する
発光面積を大きく、かつ、チップのボンディングが容易
な半導体発光素子がえられる。
According to the semiconductor light emitting device of the present invention, one electrode is laminated by forming a through hole in the sapphire substrate from the back side of the sapphire substrate and exposing a part of the lower semiconductor layer to the back side. Surface layer of semiconductor layer (for example, p-type)
And the other electrode is provided on the back surface of the sapphire substrate to be connected to the lower layer (for example, n-type) of the semiconductor layer through the through hole. Therefore, both electrodes are provided without etching the semiconductor layer, and a semiconductor light emitting element in which the light emitting area for the same chip area is large and the chip bonding is easy can be obtained.

【0019】前記サファイア基板に貫通孔を設けるには
集束イオンビーム(focused ion beam 、以下、FIBと
いう)装置などのイオンビームを用いることによりサフ
ァイア基板でも加工して貫通孔を設けることができる。
In order to form the through hole in the sapphire substrate, the sapphire substrate can be processed to form the through hole by using an ion beam such as a focused ion beam (hereinafter referred to as FIB) device.

【0020】また、本発明の半導体発光素子の製法によ
れば、チッ化ガリウム系化合物半導体層のエッチングを
するのにFIBなどのイオンビームを用いているため、
半導体層に照射される粒子はイオンビームによりはるか
に小さく、かつ、エネルギーは大きい。その結果、コン
タミネーションの付着もなく清浄なエッチング面がえら
れる。そのため、側面から発光するLEDや半導体レー
ザの発光特性を向上させることができる。
According to the method for manufacturing a semiconductor light emitting device of the present invention, an ion beam such as FIB is used for etching the gallium nitride based compound semiconductor layer.
The particles irradiated onto the semiconductor layer are much smaller by the ion beam, and the energy is larger. As a result, a clean etching surface can be obtained without adhesion of contamination. Therefore, it is possible to improve the light emission characteristics of the LED or the semiconductor laser that emits light from the side surface.

【0021】[0021]

【実施例】つぎに図面を参照しながら本発明の半導体発
光素子の製法を説明する。図1は本発明の半導体発光素
子の一実施例であるLEDの断面説明図、図2はその製
造工程を示す工程断面説明図、図3〜4は本発明の半導
体発光素子の製法の他の実施例の半導体レーザチップの
工程断面説明図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor light emitting device of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory sectional view of an LED which is an embodiment of the semiconductor light emitting device of the present invention, FIG. 2 is an explanatory sectional view of a process showing the manufacturing process thereof, and FIGS. 3 to 4 are other manufacturing methods of the semiconductor light emitting device of the present invention. FIG. 6 is a process cross-sectional explanatory view of the semiconductor laser chip of the example.

【0022】図1において、サファイア(Al2 3
結晶)基板11上に、たとえばn型のGaNなどからな
る低温バッファ層12が400〜700℃の低温で0.
01〜0.2μm程度に形成され、その上に900〜1
200℃の高温でSiなどをドーパントしたn型のGa
Nなどからなるn型層13が形成され、さらにその上に
Mgなどをドーパントとしたp型のGaNなどからなる
p型層14が形成されてGaN層からなるホモpn接合
が形成されている。p型層14上には、Al、Ti、C
r、Ni、Au、Mgなどからなるp側電極15が設け
られ、サファイア基板11の裏面にはサファイア基板1
1に設けられた貫通孔17を介してn型の低温バッファ
層12に接続されたn側電極16が設けられてpn接合
のLEDが形成されている。
In FIG. 1, a low temperature buffer layer 12 made of, for example, n-type GaN is formed on a sapphire (Al 2 O 3 single crystal) substrate 11 at a low temperature of 400 to 700 ° C.
It is formed to have a thickness of about 01 to 0.2 μm, and 900 to 1 on it.
N-type Ga doped with Si or the like at a high temperature of 200 ° C.
An n-type layer 13 made of N or the like is formed, and a p-type layer 14 made of p-type GaN or the like using Mg or the like as a dopant is further formed thereon to form a homo-pn junction made of a GaN layer. Al, Ti, C are formed on the p-type layer 14.
A p-side electrode 15 made of r, Ni, Au, Mg or the like is provided, and the sapphire substrate 1 is provided on the back surface of the sapphire substrate 11.
The n-side electrode 16 connected to the n-type low temperature buffer layer 12 through the through hole 17 provided in No. 1 is provided to form a pn junction LED.

【0023】本発明では、サファイア基板11に貫通孔
17が設けられ、その裏面にn側電極16が設けられて
いることに特徴がある。すなわち、従来サファイア基板
11があるため、n側電極はp型層14の一部をエッチ
ングしてn型層13を露出させ、n型層13の露出面に
n側電極が設けられていたが、本発明ではFIBによれ
ば、サファイア基板11でも加工することができること
を見出し、サファイア基板11の裏面から貫通孔17を
形成し、n型の低温バッファ層12またはn型層13に
電気的に接続されるn側電極をサファイア基板11の裏
面側に設けられたものである。
The present invention is characterized in that the sapphire substrate 11 is provided with the through hole 17 and the rear surface thereof is provided with the n-side electrode 16. That is, since the conventional sapphire substrate 11 is provided, the n-side electrode is formed by etching a part of the p-type layer 14 to expose the n-type layer 13, and the n-side electrode is provided on the exposed surface of the n-type layer 13. According to the FIB of the present invention, it was found that the sapphire substrate 11 can also be processed, and the through hole 17 is formed from the back surface of the sapphire substrate 11 to electrically connect the n-type low temperature buffer layer 12 or the n-type layer 13 to each other. The n-side electrode to be connected is provided on the back surface side of the sapphire substrate 11.

【0024】本発明によれば、サファイア基板11の裏
面側にn側電極16が設けられているため、p型層14
のGaNなどからなるチッ化ガリウム系化合物半導体層
をエッチングする必要がない。そのため、Cl2やCl2
とBCl3の混合ガスなどの塩素系プラズマなどのドラ
イエッチングにより発生するAlとClの化合物からな
るコンタミネーションなどの付着がなく発光効率がよく
なるとともに、チップ面積全体のpn接合を利用するこ
とができ、同じチップ面積に対し多くの発光量がえらえ
る。しかも裏面に電極が出ているため、リードフレーム
などにボンディングするだけで一方の電極の接続をする
ことができ、ワイヤボンディングの工数を減らすことも
できる。
According to the present invention, since the n-side electrode 16 is provided on the back surface side of the sapphire substrate 11, the p-type layer 14 is provided.
It is not necessary to etch the gallium nitride-based compound semiconductor layer made of GaN or the like. Therefore, Cl 2 and Cl 2
The emission efficiency is improved without the adhesion of contamination such as a compound of Al and Cl generated by dry etching of chlorine-based plasma such as a mixed gas of BCl 3 and BCl 3 , and the pn junction of the entire chip area can be used. , A large amount of light emission can be obtained for the same chip area. Moreover, since the electrode is exposed on the back surface, one electrode can be connected only by bonding to a lead frame or the like, and the number of wire bonding steps can be reduced.

【0025】つぎにこのLEDの製法の一実施例を図2
を参照しながら説明する。まず図2(a)に示されるよ
うに、300〜500μm程度の厚さのサファイア基板
11を反応管内に設置し、400〜700℃にてキャリ
アガスのH2 とともにTMGを50sccm、NH3
15sccm、ドーパントのSiとするためのSiH4
を10sccm導入し、5〜10分間反応させて0.0
1〜0.2μm程度の厚さの低温バッファ層12を形成
する。この低温バッファ層12はサファイア基板11と
GaN単結晶層との格子整合をとるもので、前述の低温
で多結晶として成長するが、つぎのGaN単結晶の成長
層の際の高温で単結晶化される。
Next, an embodiment of this LED manufacturing method is shown in FIG.
Will be described with reference to. First, as shown in FIG. 2A, a sapphire substrate 11 having a thickness of about 300 to 500 μm is placed in a reaction tube, and TMG is 50 sccm and NH 3 is 15 sccm together with H 2 as a carrier gas at 400 to 700 ° C. , SiH 4 as dopant Si
Is introduced at 10 sccm and reacted for 5 to 10 minutes to 0.0
The low temperature buffer layer 12 having a thickness of about 1 to 0.2 μm is formed. This low-temperature buffer layer 12 has a lattice matching between the sapphire substrate 11 and the GaN single crystal layer, and grows as a polycrystal at the above-mentioned low temperature, but becomes a single crystal at a high temperature in the next growth layer of the GaN single crystal. To be done.

【0026】つぎに図2(b)に示されるように、反応
管内の温度を900〜1200℃の高温にして、前述と
同じガスを反応管内に導入し、n型GaN単結晶層から
なるn型層13を積層する。
Next, as shown in FIG. 2 (b), the temperature inside the reaction tube is raised to a high temperature of 900 to 1200 ° C., the same gas as described above is introduced into the reaction tube, and an n-type GaN single crystal layer is formed. The mold layer 13 is laminated.

【0027】さらに図2(c)に示されるように、同じ
温度でドーパントとしてのSiHガスに代えてMgま
たはZnをCpMgまたはDMZnとして50sc
cm導入してp型GaNからなるp型層14を1〜2μ
m程度の厚さに成長する。
Further, as shown in FIG. 2 (c), Mg or Zn is replaced with Cp 2 Mg or DMZn at 50 sc instead of SiH 4 gas as a dopant at the same temperature.
cm to introduce the p-type layer 14 made of p-type GaN by 1 to 2 μm.
It grows to a thickness of about m.

【0028】そののち反応管を室温に下げ、基板ごと反
応管から取り出し蒸着装置でAl、Ti、Cr、Ni、
Au、Mgなどの金属をp型層14上に成膜し、パター
ニングしてp側電極15を形成する。そののちサファイ
ア基板11の裏面側にホトレジスト膜18を1.5〜2
μm程度設け、貫通孔17を設ける場所をパターニング
して開口を設け、たとえば集束イオンビームの照射を行
うことにより、サファイア基板11を加工して貫通孔1
7を設ける(図2(d)参照)。
After that, the reaction tube is cooled down to room temperature, and the substrate is taken out of the reaction tube and Al, Ti, Cr, Ni, and
A metal such as Au or Mg is deposited on the p-type layer 14 and patterned to form the p-side electrode 15. After that, a photoresist film 18 is formed on the back surface side of the sapphire substrate 11 by 1.5 to 2
The sapphire substrate 11 is processed by processing the sapphire substrate 11 by, for example, irradiating a focused ion beam to form an opening by patterning a place where the through hole 17 is provided and providing the through hole 1.
7 is provided (see FIG. 2D).

【0029】ついで、p側電極15と同様にTi、Al
などの金属膜を蒸着などにより設けることにより、図1
に示されるように、サファイア基板の裏面にn側電極1
6が設けられたLEDチップがえられる。このLEDチ
ップをリードフレームなどにダイボンディングすること
によりn側電極16は接続され、p側電極15のみをワ
イヤボンディングすることにより組み立てられ、透明樹
脂で覆うことによりLEDがえられる。
Then, similarly to the p-side electrode 15, Ti, Al
As shown in FIG.
, The n-side electrode 1 on the back surface of the sapphire substrate.
An LED chip provided with 6 is obtained. The n-side electrode 16 is connected by die-bonding this LED chip to a lead frame or the like, assembled by wire-bonding only the p-side electrode 15, and covered with a transparent resin to obtain an LED.

【0030】前述の例ではチッ化ガリウム系化合物半導
体層としてGaNを用い、ホモpn接合の例であった
が、ヘテロpn接合、ダブルヘテロ接合などのLED、
SLD、LDについても同様に行える。またチッ化ガリ
ウム系化合物半導体としてはGaN以外に、一般にAl
p Gaq Inl-p-q N(0≦p<1、0<q≦1、0<
p+q≦1)のp、qを適当に選択した材料でもよく、
さらにNの一部または全部をAsおよび/またはPなど
で置換した材料でも同様に本発明を適用できる。つぎ
に、図3〜4を参照しながら本発明の製法の他の実施例
である半導体レーザの製法について説明する。
In the above example, GaN was used as the gallium nitride based compound semiconductor layer and the example was a homo pn junction. However, LEDs such as a hetero pn junction and a double hetero junction,
The same can be done for SLD and LD. In addition to GaN, gallium nitride compound semiconductors are generally Al
p Ga q In lpq N (0 ≦ p <1, 0 <q ≦ 1, 0 <
A material in which p and q of p + q ≦ 1) are appropriately selected,
Furthermore, the present invention can be similarly applied to a material in which a part or all of N is replaced with As and / or P or the like. Next, a method of manufacturing a semiconductor laser, which is another embodiment of the manufacturing method of the present invention, will be described with reference to FIGS.

【0031】まず図3(a)に示されるように、従来技
術で説明したのと同様に、有機金属ガスおよび不純物ガ
スを導入してMOCVD法により、サファイア基板1上
にn型GaNからなる低温バッファ層2を0.01〜
0.2μm程度、900〜1200℃でn型GaNから
なる高温バッファ層3を2〜4μm程度、n型Alx
1-x N(0<x<1)からなる下部クラッド層4を
0.1〜0.3μm程度、クラッド層よりもバンドギャ
ップエネルギーが小さくなる材料、たとえばノンドープ
のGay In1-y N(0<y≦1)からなる活性層5を
0.02〜0.1μm程度、p型Alx Ga1-x Nから
なる上部クラッド層6を0.1〜0.3μm程度、p型
GaNからなるキャップ層7を0.3〜1μmそれぞれ
連続的に成膜する。
First, as shown in FIG. 3A, in the same manner as described in the prior art, a low temperature composed of n-type GaN is formed on the sapphire substrate 1 by the MOCVD method by introducing an organic metal gas and an impurity gas. The buffer layer 2 is 0.01 to
The high temperature buffer layer 3 made of n-type GaN at about 0.2 μm and 900 to 1200 ° C. is formed at about 2 to 4 μm and n-type Al x G.
The lower clad layer 4 made of a 1-x N (0 <x <1) has a band gap energy smaller than that of the clad layer by about 0.1 to 0.3 μm, for example, non-doped Ga y In 1-y N 2. The active layer 5 made of (0 <y ≦ 1) has a thickness of about 0.02 to 0.1 μm, the upper clad layer 6 made of p-type Al x Ga 1-x N has a thickness of about 0.1 to 0.3 μm, and p-type GaN. The cap layer 7 consisting of 0.3 to 1 μm is continuously formed.

【0032】つぎに図3(b)に示されるように、積層
された半導体層の表面にレジスト膜10を塗布し、半導
体層のエッチングされる部分が開口するようにパターニ
ングする。
Next, as shown in FIG. 3B, a resist film 10 is applied to the surface of the laminated semiconductor layers and patterned so that the etched portions of the semiconductor layers are opened.

【0033】つぎに、開口部11により露出している半
導体層を、たとえばFIBによりエッチング加工を行
い、図3(c)に示されるように、活性層5を貫通して
n型の高温バッファ層3が露出するまでエッチングす
る。本実施例の製法では、このチッ化ガリウム系化合物
半導体層の積層体のエッチングをFIBを用いて行うこ
とに特徴がある。
Next, the semiconductor layer exposed through the opening 11 is etched by, for example, FIB, and penetrates the active layer 5 to pass through the n-type high temperature buffer layer as shown in FIG. 3 (c). Etch until 3 is exposed. The manufacturing method of this embodiment is characterized in that the stack of gallium nitride based compound semiconductor layers is etched by using FIB.

【0034】この半導体層の積層表面およびエッチング
により露出した半導体層の表面にAl、Ti、Cr、N
i、Au、Mgなどからなる金属膜を成膜してパターニ
ングすることにより、p側電極8およびn側電極9をそ
れぞれキャップ層7およびエッチングにより露出した高
温バッファ層3上に形成する(図4(d)参照)。
Al, Ti, Cr, N are formed on the surface of the laminated semiconductor layer and the surface of the semiconductor layer exposed by etching.
A p-side electrode 8 and an n-side electrode 9 are formed on the cap layer 7 and the high temperature buffer layer 3 exposed by etching, respectively, by depositing and patterning a metal film made of i, Au, Mg or the like (FIG. 4). (See (d)).

【0035】そののちp側電極8をマスクとしてキャッ
プ層7および上部クラッド層6の一部をドライエッチン
グによりエッチングしてメサ形状とし、基板1をダイシ
ングすることにより、p側電極8の4〜10μmの帯状
の形状にストライプが形成された半導体レーザのチップ
がえられる(図4(e)参照)。このメサ状エッチング
も同様にFIBを用いたドライエッチングで行うことが
望ましい。またLEDのばあいは、このメサ形状エッチ
ングを行わないで、図4(d)の状態でダイシングして
チップ化することよりダブルヘテロ接合のLEDがえら
れる。
After that, the cap layer 7 and a part of the upper cladding layer 6 are etched by dry etching using the p-side electrode 8 as a mask to form a mesa shape, and the substrate 1 is diced, whereby 4 to 10 μm of the p-side electrode 8 is formed. A semiconductor laser chip in which stripes are formed in a strip shape is obtained (see FIG. 4E). It is desirable that this mesa etching be similarly performed by dry etching using FIB. In the case of an LED, a double heterojunction LED can be obtained by dicing in the state of FIG. 4 (d) to form a chip without performing the mesa shape etching.

【0036】前記実施例ではメサエッチングすることに
より電流の注入領域をストライプ形状にする半導体レー
ザの例で説明したが、たとえばクラッド層内にストライ
プ溝の形成された反対導電型の電流ブロッキング層を設
ける構造やプレーナストライプ型構造の半導体レーザで
も本発明により清浄なエッチング面をうることができ、
チッ化ガリウム系化合物半導体層を用いた青色の半導体
レーザをうることができる。また、レーザダイオードに
限らずLEDでも同様で、さらにチッ化ガリウム系の半
導体材料も前述の組成に限定されず、一般にAlp Ga
q In1-p-q N(0≦p<1、0<q≦1、0<p+q
≦1)からなるダブルヘテロ接合やpn接合の半導体発
光素子に適用できる。さらに前記Alp Gaq In
1-p-q NのNの一部または全部をAsおよび/またはP
などで置換した材料でも同様に本発明を適用できる。
In the above-mentioned embodiment, the semiconductor laser is explained as an example in which the current injection region is formed into a stripe shape by mesa etching. However, for example, a current blocking layer of the opposite conductivity type having a stripe groove formed in the cladding layer is provided. Even a semiconductor laser having a structure or a planar stripe type structure can obtain a clean etching surface by the present invention,
A blue semiconductor laser using a gallium nitride based compound semiconductor layer can be obtained. The same applies not only to laser diodes but also to LEDs, and the gallium nitride-based semiconductor material is not limited to the above-mentioned composition, and is generally Al p Ga.
q In 1-pq N (0 ≦ p <1, 0 <q ≦ 1, 0 <p + q
It can be applied to a semiconductor light emitting device having a double heterojunction or a pn junction consisting of ≦ 1). Further, the Al p Ga q In
1-pq N part or all of N is As and / or P
The present invention can be similarly applied to a material substituted with, for example.

【0037】[0037]

【発明の効果】本発明の半導体発光素子によれば、チッ
プ面積の全体にわたって発光領域を形成できるため、輝
度の大きな発光素子がえられるとともにコンタミネーシ
ョンの付着などがないため、発光効率が向上する。
According to the semiconductor light emitting device of the present invention, since the light emitting region can be formed over the entire chip area, a light emitting device with high brightness can be obtained and contamination is not attached, so that the light emitting efficiency is improved. .

【0038】また、本発明の製法によれば、FIBを用
いてエッチングしているため、サファイア基板に貫通孔
をあけることができ、絶縁性のサファイア基板上に形成
された半導体発光素子の裏面側から電極を取り出すこと
ができ組立が容易になる。
Further, according to the manufacturing method of the present invention, since the etching is performed by using FIB, it is possible to form the through hole in the sapphire substrate, and the back surface side of the semiconductor light emitting device formed on the insulating sapphire substrate. The electrode can be taken out from the device, which facilitates the assembly.

【0039】さらにチッ化ガリウム系化合物半導体層を
エッチングするばあいにもコンタミネーションが付着せ
ず、清浄なエッチング面がえられ、発光効率の高い半導
体発光素子がえられる。
Further, when the gallium nitride compound semiconductor layer is etched, contamination is not adhered, a clean etched surface is obtained, and a semiconductor light emitting device having high luminous efficiency is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体発光素子の一実施例であるLE
Dの断面説明図である。
FIG. 1 is an example of an LE of a semiconductor light emitting device of the present invention.
It is a section explanatory view of D.

【図2】図1の製造工程を示す断面説明図である。2A and 2B are cross-sectional explanatory views showing the manufacturing process of FIG.

【図3】本発明の半導体発光素子の他の製法の一実施例
の製造工程を示す図である。
FIG. 3 is a diagram showing a manufacturing process of another embodiment of the method for manufacturing the semiconductor light emitting device of the present invention.

【図4】本発明の半導体発光素子の他の製法の一実施例
の製造工程を示す図である。
FIG. 4 is a diagram showing a manufacturing process of another embodiment of the method for manufacturing the semiconductor light emitting device of the present invention.

【図5】従来のチッ化ガリウム系化合物半導体を用いた
LEDの断面説明図である。
FIG. 5 is a cross-sectional explanatory view of an LED using a conventional gallium nitride based compound semiconductor.

【符号の説明】[Explanation of symbols]

1 基板 4 n型クラッド層 5 活性層 6 p型クラッド層 11 サファイア基板 13 n型層 14 p型層 15 p側電極 16 n側電極 1 substrate 4 n-type clad layer 5 active layer 6 p-type clad layer 11 sapphire substrate 13 n-type layer 14 p-type layer 15 p-side electrode 16 n-side electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 サファイア基板上に少なくともn型層お
よびp型層を含み発光層を有するチッ化ガリウム系化合
物半導体層が積層され、前記n型層およびp型層にそれ
ぞれ接続される電極が設けられてなる半導体発光素子で
あって、前記積層された半導体層の表層に接続してp側
またはn側の一方の電極が設けられ、前記サファイア基
板に設けられた貫通孔を介して露出した半導体層に接続
して該サファイア基板の裏面にn側またはp側の他方の
電極が設けられてなる半導体発光素子。
1. A gallium nitride based compound semiconductor layer having at least an n-type layer and a p-type layer and having a light emitting layer is laminated on a sapphire substrate, and electrodes provided respectively to the n-type layer and the p-type layer are provided. A semiconductor light-emitting device having the above structure, wherein a p-side or n-side electrode connected to a surface layer of the stacked semiconductor layers is provided, and the semiconductor is exposed through a through hole provided in the sapphire substrate. A semiconductor light emitting device, which is connected to a layer and is provided with the other electrode on the n side or the p side on the back surface of the sapphire substrate.
【請求項2】 サファイア基板上に少なくともn型層お
よびp型層を含み発光層を有するチッ化ガリウム系化合
物半導体を積層し、前記n型層およびp型層にそれぞれ
接続される電極を設ける半導体発光素子の製法であっ
て、前記電極の一方を前記積層された半導体層の表面に
設け、前記電極の他方を前記サファイア基板に集束イオ
ンビームにより設けた貫通孔を介して露出した半導体層
に接触するように前記サファイア基板の裏面に電極材料
を付着することにより設けることを特徴とする半導体発
光素子の製法。
2. A semiconductor in which a gallium nitride based compound semiconductor having at least an n-type layer and a p-type layer and having a light emitting layer is laminated on a sapphire substrate, and electrodes provided respectively to the n-type layer and the p-type layer are provided. A method of manufacturing a light emitting device, wherein one of the electrodes is provided on a surface of the stacked semiconductor layers, and the other of the electrodes is in contact with a semiconductor layer exposed through a through hole provided by a focused ion beam on the sapphire substrate. A method for manufacturing a semiconductor light emitting device, characterized in that the electrode material is provided on the back surface of the sapphire substrate as described above.
JP5768795A 1995-03-16 1995-03-16 Semiconductor light emitting element and fabrication thereof Pending JPH08255926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5768795A JPH08255926A (en) 1995-03-16 1995-03-16 Semiconductor light emitting element and fabrication thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5768795A JPH08255926A (en) 1995-03-16 1995-03-16 Semiconductor light emitting element and fabrication thereof

Publications (1)

Publication Number Publication Date
JPH08255926A true JPH08255926A (en) 1996-10-01

Family

ID=13062862

Family Applications (1)

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Country Status (1)

Country Link
JP (1) JPH08255926A (en)

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