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JPH08250589A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH08250589A
JPH08250589A JP8191195A JP8191195A JPH08250589A JP H08250589 A JPH08250589 A JP H08250589A JP 8191195 A JP8191195 A JP 8191195A JP 8191195 A JP8191195 A JP 8191195A JP H08250589 A JPH08250589 A JP H08250589A
Authority
JP
Japan
Prior art keywords
wiring
film
semiconductor device
contact hole
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8191195A
Other languages
Japanese (ja)
Inventor
Hiroshi Sakurai
博 桜井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP8191195A priority Critical patent/JPH08250589A/en
Publication of JPH08250589A publication Critical patent/JPH08250589A/en
Pending legal-status Critical Current

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Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To increase the allowance of alignment of a contact hole with wiring without increasing the width of the wiring itself and without increasing the contact resistance. CONSTITUTION: A sidewall 28 made of a conductive film is formed on a wiring 25, with the wiring 25 and the sidewall 28 as stoppers, a contact hole 32 reaching the wiring 25 is opened in an SiO2 film 31. Thus, even if the misalignment with the wiring 25 occurs, the hole 32 is scarcely deepened from the surface of the wiring 25. Further, since the sidewall 28 is conductive, the contact resistance of the hole 31 is not increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本願の発明は、コンタクト孔が開
口されるべき配線を有する半導体装置の製造方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a wiring in which a contact hole is to be opened.

【0002】[0002]

【従来の技術】図2は、本願の発明の一従来例で製造し
た半導体装置を示している。この一従来例では、Al−
Si膜11等である配線を層間絶縁膜としてのSiO2
膜12で覆い、Al−Si膜11に対するコンタクト孔
13をSiO2 膜12に開口し、このコンタクト孔13
を介してAl−Si膜11に接続すべき上層側の配線で
あるAl−Si膜(図示せず)を形成していた。
2. Description of the Related Art FIG. 2 shows a semiconductor device manufactured by a conventional example of the present invention. In this conventional example, Al-
The wiring such as the Si film 11 is formed of SiO 2 as an interlayer insulating film.
The contact hole 13 for the Al-Si film 11 is covered with the film 12, and the contact hole 13 is opened in the SiO 2 film 12.
An Al-Si film (not shown), which is an upper wiring layer to be connected to the Al-Si film 11 via the via, is formed.

【0003】ところが、Al−Si膜11の幅とコンタ
クト孔13の寸法とが同等程度である場合に、コンタク
ト孔13を開口するためのリソグラフィ工程でAl−S
i膜11に対する合わせずれが生じると、図2に示した
様に、オーバエッチングのために、コンタクト孔13の
一部がAl−Si膜11の表面よりも深くなる。
However, when the width of the Al-Si film 11 and the dimension of the contact hole 13 are about the same, Al-S is used in the lithography process for opening the contact hole 13.
When the misalignment with respect to the i film 11 occurs, a part of the contact hole 13 becomes deeper than the surface of the Al—Si film 11 due to overetching, as shown in FIG.

【0004】この結果、上層側の配線であるAl−Si
膜に段切れが発生したり、コンタクト孔13内にボイド
が形成されたりして、半導体装置の信頼性が低かった。
そこで、下層配線のうちでコンタクト孔が開口されるべ
き部分の幅を太くするという合わせ余裕が配線に設けら
れていた。
As a result, the upper layer wiring, Al--Si
The reliability of the semiconductor device was low due to the occurrence of step breakage in the film and the formation of voids in the contact holes 13.
Therefore, the wiring is provided with an alignment margin in which the width of the portion of the lower layer wiring where the contact hole is to be opened is increased.

【0005】[0005]

【発明が解決しようとする課題】しかし、コンタクト孔
の合わせ余裕を配線に設けると、配線のピッチを広くせ
ざるを得ず、従来の方法では、集積度の高い半導体装置
を製造することが困難であった。
However, if the wiring is provided with a contact hole alignment margin, the pitch of the wiring must be widened, and it is difficult to manufacture a highly integrated semiconductor device by the conventional method. Met.

【0006】[0006]

【課題を解決するための手段】請求項1の半導体装置の
製造方法は、導電膜から成る側壁を配線に形成する工程
と、前記配線及び前記側壁を絶縁膜で覆う工程と、前記
配線及び前記側壁をストッパにして前記絶縁膜をエッチ
ングすることによって、少なくとも前記配線に達するコ
ンタクト孔を開口する工程とを具備することを特徴とし
ている。
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a side wall made of a conductive film is formed on a wiring, a step of covering the wiring and the side wall with an insulating film, the wiring and the side wall. And etching the insulating film using the side wall as a stopper to open a contact hole that reaches at least the wiring.

【0007】請求項2の半導体装置の製造方法は、前記
配線がAlを主成分としており、前記側壁が高融点金属
を主成分としていることを特徴としている。
The method of manufacturing a semiconductor device according to a second aspect is characterized in that the wiring contains Al as a main component and the side wall contains a refractory metal as a main component.

【0008】[0008]

【作用】請求項1の半導体装置の製造方法では、配線に
対して自己整合的に形成することができる側壁を導電膜
で形成し、配線のみならず側壁をもストッパにしてコン
タクト孔を開口しているので、配線自体の幅を広くせず
且つコンタクト抵抗を増大させることなく配線に対する
コンタクト孔の合わせ余裕を大きくすることができる。
In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the side wall that can be formed in self-alignment with the wiring is formed of a conductive film, and not only the wiring but also the side wall is used as a stopper to open the contact hole. Therefore, it is possible to increase the alignment margin of the contact hole with respect to the wiring without increasing the width of the wiring itself and increasing the contact resistance.

【0009】また、配線に側壁を形成した状態でこれら
の配線及び側壁を絶縁膜で覆っているので、配線に側壁
を形成しない場合に比べて、絶縁膜の下地の表面が滑ら
かであり、配線間の段差部を絶縁膜で埋め込み易い。
Further, since the wiring and the side wall are covered with the insulating film in the state where the side wall is formed on the wiring, the surface of the base of the insulating film is smoother than that in the case where the side wall is not formed on the wiring. It is easy to fill the stepped portion with an insulating film.

【0010】請求項2の半導体装置の製造方法では、A
lを主成分とする配線に高融点金属を主成分とする側壁
を形成しており、配線が断線しても側壁で導通が維持さ
れるので、配線及び側壁の全体的なエレクトロマイグレ
ーション耐性及びストレスマイグレーション耐性が高
い。
In the method of manufacturing a semiconductor device according to claim 2, A
Since the side wall containing a refractory metal as a main component is formed in the wiring containing l as a main component and continuity is maintained at the side wall even if the wiring is broken, overall electromigration resistance and stress of the wiring and the side wall are maintained. High migration resistance.

【0011】[0011]

【実施例】以下、本願の発明の一実施例を、図1を参照
しながら説明する。本実施例では、図1(a)に示す様
に、膜厚が30nm程度のTi膜21と、膜厚が70n
m程度のTiN膜22と、膜厚が600nm程度のAl
−Si膜23と、膜厚が100nm程度のTiN膜24
とをスパッタ法で順次に堆積させる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In this embodiment, as shown in FIG. 1A, a Ti film 21 having a film thickness of about 30 nm and a film thickness of 70 n are formed.
m TiN film 22 and Al having a film thickness of about 600 nm
-Si film 23 and TiN film 24 having a film thickness of about 100 nm
And are sequentially deposited by the sputtering method.

【0012】そして、TiN膜24上で配線のパターン
のレジスト(図示せず)をリソグラフィ法で形成し、こ
のレジストをマスクにしたRIEを上述の膜に施して、
配線25を形成する。なお、Al−Si膜23の代わり
にAl−Si−Cu膜等を用いてもよい。
Then, a resist (not shown) having a wiring pattern is formed on the TiN film 24 by a lithographic method, and RIE using the resist as a mask is applied to the above film,
The wiring 25 is formed. Instead of the Al-Si film 23, an Al-Si-Cu film or the like may be used.

【0013】次に、図1(b)に示す様に、膜厚が30
nm程度である密着層としてのTiN膜26をスパッタ
法で堆積させ、更にW膜27をCVD法で堆積させる。
そして、これらの膜の全面をRIEでエッチバックし
て、W膜27及びTiN膜26から成る側壁28を配線
25に形成する。
Next, as shown in FIG. 1B, the film thickness is 30
A TiN film 26 as an adhesion layer having a thickness of about nm is deposited by a sputtering method, and a W film 27 is further deposited by a CVD method.
Then, the entire surfaces of these films are etched back by RIE to form sidewalls 28 of the W film 27 and the TiN film 26 on the wiring 25.

【0014】次に、図1(c)に示す様に、層間絶縁膜
としてのSiO2 膜31を全面に形成し、SiO2 膜3
1上でコンタクト孔のパターンのレジスト(図示せず)
をリソグラフィ法で形成する。そして、このレジストを
マスクにすると共に配線25及び側壁28をストッパに
したRIEをSiO2 膜31に施して、コンタクト孔3
2を開口する。
Next, as shown in FIG. 1C, a SiO 2 film 31 as an interlayer insulating film is formed on the entire surface, and the SiO 2 film 3 is formed.
1. Contact hole pattern resist on top (not shown)
Are formed by a lithographic method. Then, RIE using the resist as a mask and the wirings 25 and the sidewalls 28 as stoppers is performed on the SiO 2 film 31 to contact the contact holes 3
Open 2.

【0015】次に、図1(d)に示す様に、膜厚が30
nm程度である密着層としてのTiN膜33をスパッタ
法で堆積させ、更にW膜34をCVD法で堆積させる。
そして、これらの膜の全面をRIEでエッチバックし
て、W膜34及びTiN膜33から成るプラグ35をコ
ンタクト孔32内に形成する。
Next, as shown in FIG. 1D, the film thickness is 30
A TiN film 33 as an adhesion layer having a thickness of about nm is deposited by the sputtering method, and a W film 34 is further deposited by the CVD method.
Then, the entire surface of these films is etched back by RIE to form a plug 35 composed of the W film 34 and the TiN film 33 in the contact hole 32.

【0016】その後、膜厚が100nm程度のTi膜3
6と、膜厚が600nm程度のAl−Si膜37と、膜
厚が100nm程度のTiN膜38とをスパッタ法で順
次に堆積させる。
Then, a Ti film 3 having a film thickness of about 100 nm is formed.
6, an Al—Si film 37 having a film thickness of about 600 nm, and a TiN film 38 having a film thickness of about 100 nm are sequentially deposited by a sputtering method.

【0017】そして、TiN膜38上で配線のパターン
のレジスト(図示せず)をリソグラフィ法で形成し、こ
のレジストをマスクにしたRIEを上述の膜に施して、
上層側の配線41を形成する。なお、Al−Si膜37
の代わりにAl−Si−Cu膜等を用いてもよい。その
後、図示してはいないが、表面保護膜やボディングパッ
ドに対する開口等を形成して、この半導体装置を完成さ
せる。
Then, a resist (not shown) having a wiring pattern is formed on the TiN film 38 by a lithographic method, and RIE using the resist as a mask is applied to the above film,
The wiring 41 on the upper layer side is formed. The Al-Si film 37
Alternatively, an Al-Si-Cu film or the like may be used. After that, although not shown, openings for the surface protection film and the boding pad are formed to complete the semiconductor device.

【0018】以上の様な実施例では、コンタクト孔32
の開口に際して配線25及び側壁28の両方をストッパ
にしているので、図1(c)(d)からも明らかな様
に、配線25に対する合わせずれがコンタクト孔32に
生じても、コンタクト孔32が配線25の表面よりも深
くなりにくい。しかも、側壁28も導電性を有している
ので、コンタクト孔32におけるコンタクト抵抗は増大
しない。
In the above embodiment, the contact hole 32
Since both the wiring 25 and the side wall 28 are used as stoppers at the time of opening, as is apparent from FIGS. 1C and 1D, even if misalignment with the wiring 25 occurs in the contact hole 32, the contact hole 32 remains. It is hard to be deeper than the surface of the wiring 25. Moreover, since the side wall 28 also has conductivity, the contact resistance in the contact hole 32 does not increase.

【0019】[0019]

【発明の効果】請求項1の半導体装置の製造方法では、
配線自体の幅を広くせず且つコンタクト抵抗を増大させ
ることなく配線に対するコンタクト孔の合わせ余裕を大
きくすることができるので、配線のピッチを狭くして、
集積度の高い半導体装置を製造することができる。ま
た、配線間の段差部を絶縁膜で埋め込み易いので、簡易
な工程で半導体装置を製造することができる。
According to the method of manufacturing a semiconductor device of claim 1,
Since it is possible to increase the alignment allowance of the contact hole with respect to the wiring without increasing the width of the wiring itself and increasing the contact resistance, the pitch of the wiring can be narrowed.
A highly integrated semiconductor device can be manufactured. Further, since the step portion between the wirings is easily filled with the insulating film, the semiconductor device can be manufactured by a simple process.

【0020】請求項2の半導体装置の製造方法では、配
線及び側壁の全体的なエレクトロマイグレーション耐性
及びストレスマイグレーション耐性が高いので、信頼性
の高い半導体装置を製造することができる。
In the method of manufacturing a semiconductor device according to the second aspect of the present invention, since the wiring and the sidewall have high electromigration resistance and stress migration resistance as a whole, a highly reliable semiconductor device can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本願の発明の一実施例を工程順に示す半導体装
置の側断面図である。
FIG. 1 is a side sectional view of a semiconductor device showing an embodiment of the present invention in the order of steps.

【図2】本願の発明の一従来例で製造した半導体装置の
側断面図である。
FIG. 2 is a side sectional view of a semiconductor device manufactured by a conventional example of the invention of the present application.

【符号の説明】[Explanation of symbols]

25 配線 28 側壁 31 SiO2 膜 32 コンタクト孔25 wiring 28 side wall 31 SiO 2 film 32 contact hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 導電膜から成る側壁を配線に形成する工
程と、 前記配線及び前記側壁を絶縁膜で覆う工程と、 前記配線及び前記側壁をストッパにして前記絶縁膜をエ
ッチングすることによって、少なくとも前記配線に達す
るコンタクト孔を開口する工程とを具備することを特徴
とする半導体装置の製造方法。
1. At least a step of forming a side wall made of a conductive film on a wiring, a step of covering the wiring and the side wall with an insulating film, and etching the insulating film using the wiring and the side wall as stoppers. And a step of opening a contact hole reaching the wiring.
【請求項2】 前記配線がAlを主成分としており、 前記側壁が高融点金属を主成分としていることを特徴と
する請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring has Al as a main component, and the sidewall has a refractory metal as a main component.
JP8191195A 1995-03-14 1995-03-14 Manufacture of semiconductor device Pending JPH08250589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8191195A JPH08250589A (en) 1995-03-14 1995-03-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8191195A JPH08250589A (en) 1995-03-14 1995-03-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH08250589A true JPH08250589A (en) 1996-09-27

Family

ID=13759638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8191195A Pending JPH08250589A (en) 1995-03-14 1995-03-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH08250589A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023101A (en) * 1997-12-10 2000-02-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US6025645A (en) * 1997-12-19 2000-02-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US6284618B1 (en) 1997-10-29 2001-09-04 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor device having a conductor pattern side face provided with a separate conductive sidewall
KR100301644B1 (en) * 1997-04-08 2001-10-19 포만 제프리 엘 Interconnects using metal spacers and method for forming same
US8343830B2 (en) 2005-09-30 2013-01-01 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100301644B1 (en) * 1997-04-08 2001-10-19 포만 제프리 엘 Interconnects using metal spacers and method for forming same
US6284618B1 (en) 1997-10-29 2001-09-04 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor device having a conductor pattern side face provided with a separate conductive sidewall
US6344406B2 (en) 1997-10-29 2002-02-05 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing a semiconductor device having a conductor pattern side face provided with a separate conductive sidewall
US6023101A (en) * 1997-12-10 2000-02-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US6025645A (en) * 1997-12-19 2000-02-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US6127265A (en) * 1997-12-19 2000-10-03 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device with a stacked via
US8343830B2 (en) 2005-09-30 2013-01-01 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
US8680596B2 (en) 2005-09-30 2014-03-25 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same

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