JPH08264791A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To reduce generation of strain and film defect at the time of solid phase growth, by forming a lower gate insulating film on a lower gate electrode composed of a polycrystalline silicon film on an insulating film, including the lower gate electrode, and forming a silicon nitride film in the region except a seed region. CONSTITUTION: On a single crystal silicon substrate 1, the following are formed; an insulating film 2 composed of a silicon oxide film, a lower gate electrode 4 composed of a polycrystalline silicon film on the insulating film 2 composed of the silicon oxide film, and a lower gate insulating film 10. A silicon nitride film 3 is formed in the region except a seed region 6. An active layer region 7 is formed on a silicon nitride film 3. An upper gate insulating film 11 is formed on the surface of an active layer region 7. An upper gate electrode 5 is formed on the upper insulating film 11. A source region 8 and a drain region 9 are formed in the active layer region 7 of a region matching the upper gate 5. A mask oxide film 12 of a silicon oxide film and an interlayer insulating film 13 are formed. An aluminum electrode 14 is formed via a contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double-gate type field effect thin film transistor formed on an insulating film, which has an active layer region of a sufficient single crystal region and has a design margin and excellent reliability. The present invention relates to a semiconductor device having characteristics and a manufacturing method thereof.

[0002]

2. Description of the Related Art Generally, a field effect thin film transistor formed on an insulating film is used for an active matrix of liquid crystal, a sensor, a three-dimensional circuit element and the like.

As a conventional example, the structure of a double gate type field effect thin film transistor will be described with reference to the sectional view of FIG.

As shown in FIG. 7, a single crystal silicon substrate 1
A low resistance lower gate electrode 4 made of a polycrystalline silicon film is located on an insulating film 2 which is a silicon oxide film on which a seed region 6 is formed.

Further, a thin silicon oxide film is provided as a lower gate insulating film 10 on the lower gate electrode 4, an active layer region 7 is provided on the lower gate insulating film 10, and an upper layer of the thin silicon oxide film is provided as an upper gate insulating film 11. A membrane is provided.

An upper gate electrode 5 formed of a polycrystalline silicon film having a low resistance is located on the upper portion thereof, and has a source region 8 and a drain region 9, a mask oxide film 12, an interlayer insulating film 13, and a metal electrode 14. Is formed by an ordinary semiconductor element manufacturing method.

Conventionally, a single crystal silicon film to be the active layer region 7 is formed on the entire surface in the state of an amorphous silicon film so as to include the exposed seed region 6 on the surface of the single crystal silicon substrate 1, and thereafter, The amorphous silicon film is crystallized by heat treatment in a nitrogen atmosphere.

At this time, the amorphous silicon film has a temperature of 570.
Formed below ℃, the subsequent heat treatment in a nitrogen atmosphere,
The amorphous silicon film on the seed region 6 is converted into a single crystal silicon film by performing the operation at a temperature of 600 ° C. or lower for 10 hours or more,
Further, the amorphous silicon film on the insulating film 2 is also converted into a single crystal silicon film to form the active layer region 7.

The problem here is that the amorphous silicon film formed on the insulating film 2 makes it difficult to grow crystals laterally from the seed region 6, that is, in the direction parallel to the single crystal silicon substrate 1. Can be mentioned.

The solid phase growth film for transmitting the crystallinity and orientation, which are the information on the surface of the single crystal silicon substrate 1, to the amorphous silicon film for crystallization will be described in more detail with reference to the plan view of FIG. Explained.

As shown in FIG. 8, a silicon oxide film is formed on a single crystal silicon substrate 1 having a plane orientation (100), and the silicon oxide film is patterned in the <100> direction to form a seed region 6.

An amorphous silicon film is formed on the entire upper surface thereof, and heat treatment is performed in a nitrogen atmosphere to crystallize the amorphous silicon film.

In this case, when crystallization starts from the seed region 6 and shifts from the vertical direction to the horizontal direction, {11
From the growth of the 0} plane to the slow growth rate during the growth process {11
1} surface appears and regulates the lateral growth rate.

Further, the insulating film 2 made of a silicon oxide film.
As the solid-phase growth proceeds, the silicon bond bonded to the oxygen atom is strained in the growth direction.

Furthermore, in the amorphous silicon oxide film, since the lattice has no regularity, the solid-phase grown active layer region 7 is locally stressed and includes dislocations arranged irregularly. Become.

That is, the distance between the interface between the active layer region 7 which is a solid phase growth film and the silicon oxide film which is the insulating film 2 is solid phase grown on the silicon oxide film, and the film quality of the active layer region 7 is stabilized. It becomes a factor to inhibit.

In particular, the above-mentioned strain has a shape factor such as being concentrated in the vicinity of a step like the lower gate electrode 4.

[0018]

In the solid phase growth film formed on the insulating film 2, the solid phase growth is performed at the interface between the insulating film 2 and the solid phase growth film, the shape of the region to be subjected to solid phase growth, and the like. The solid-phase growth distance for growing on the insulating film 2 which is parallel to the single crystal silicon substrate 1 is determined by controlling the strain and defects in the film.

When the solid phase growth distance from the end of the seed region 6 is short, the channel region sandwiched between the upper gate electrode 5 and the lower gate electrode 4 cannot be covered by the solid phase growth film which is a single crystal silicon film. It may cause deterioration of characteristics.

Furthermore, when the solid phase growth distance is short, the gate size and the distance from the seed region end to the gate electrode end must be determined so that the channel region can be covered with the solid phase growth film. There is little margin in making decisions.

An object of the present invention is to solve the above problems and provide a semiconductor device which has a sufficient margin of single crystal active layer region on an insulating film, has a design margin, and is excellent in reliability, and a manufacturing method thereof. To do.

[0022]

In order to achieve the above object, the structure of the semiconductor device of the present invention and the manufacturing method thereof adopt the following means.

The semiconductor device of the present invention includes an insulating film provided on a single crystal silicon substrate, a lower gate electrode made of a polycrystalline silicon film provided on the insulating film, and a lower gate insulating film provided on the lower gate electrode. A silicon nitride film provided in a region other than the seed region, an active layer region provided on the silicon nitride film, an upper gate insulating film provided on the surface of the active layer region, an upper gate electrode provided on the upper gate insulating film, and an upper gate electrode The semiconductor device is provided with a source region and a drain region provided in the active layer region of the region matching with.

The method of manufacturing a semiconductor device of the present invention includes the steps of forming an insulating film on a single crystal silicon substrate and forming a lower gate electrode made of a polycrystalline silicon film on the insulating film, and on the lower gate electrode. A step of forming a lower gate insulating film on the entire surface, a step of forming a silicon nitride film, a step of removing the silicon nitride film in the seed region and an insulating film in the seed region, and a seed region in which the surface of the polycrystalline single crystal silicon substrate is exposed. To form an amorphous silicon film on the entire surface, heat treatment in a nitrogen atmosphere to convert the amorphous silicon film into a single crystal silicon film, and the single crystal silicon film except for the seed region. It includes a step of forming an upper gate insulating film by separating into islands, a step of forming an upper gate electrode, and a step of forming a source region and a drain region.

The semiconductor device of the present invention includes an insulating film provided on a single crystal silicon substrate, a seed region where the surface of the single crystal silicon substrate is exposed, a lower gate electrode made of a polycrystalline silicon film provided on the insulating film, and a lower portion. A lower gate insulating film provided on the gate electrode, a silicon nitride film provided in a region other than the seed region, an active layer region provided on the silicon nitride film, an upper gate insulating film provided on the surface of the active layer region, and an upper gate insulating film A semiconductor device comprising: an upper gate electrode provided on the upper gate electrode; and a source region and a drain region provided in an active layer region in a region matching the upper gate electrode.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an insulating film on a single crystal silicon substrate and forming a lower gate electrode made of a polycrystalline silicon film, and forming a lower gate insulating film on the lower gate electrode. Forming step, forming a silicon nitride film, removing the silicon nitride film in the seed region and the insulating film in the seed region, cleaning the seed region where the single crystal silicon substrate surface is exposed, Forming a high-quality silicon film, performing a heat treatment in a nitrogen atmosphere to convert the amorphous silicon film into a single-crystal silicon film, and separating the single-crystal silicon film into islands so as to include a seed region, It includes a step of forming an insulating film, a step of forming an upper gate electrode, and a step of forming a source region and a drain region.

[0027]

According to the semiconductor device structure and the manufacturing method of the present invention, the lower gate insulating film is provided on the lower gate electrode made of the polycrystalline silicon film on the insulating film, the lower gate electrode is included, and the area other than the seed region is included. A silicon nitride film is provided in the area.

As a result, the silicon nitride film, which is more silicon than the silicon oxide film, becomes an interface with the solid phase growth film, and it is possible to reduce strain and film defects that occur during solid phase growth.

As a result, geometrical problems such as defects concentrated on the steps of the lower gate electrode are alleviated, and the solid-phase growth distance can be increased. Further, the expanded solid-phase growth distance also expands the design margin such as the gate size and the distance from the end of the seed region to the end of the gate electrode.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a semiconductor device and its manufacturing method in an embodiment of the present invention will be described below with reference to the drawings. A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be specifically described with reference to FIGS. First, the structure of the semiconductor device according to the embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 5, single crystal silicon substrate 1
An insulating film 2 made of a silicon oxide film provided above, a lower gate electrode 4 made of a polycrystalline silicon film and a lower gate insulating film 10 are provided on the insulating film 2 made of the silicon oxide film, and the region except the seed region 6 is provided. A silicon nitride film 3 is provided.

Further, the active layer region 7 is provided on the silicon nitride film 3, the upper gate insulating film 11 provided on the surface of the active layer region 7, the upper gate electrode 5 provided on the upper gate insulating film 11, and the upper gate electrode. 5, the source region 8 and the drain region 9, which are provided in the active layer region 7 in the region corresponding to 5, the mask oxide film 12 made of a silicon oxide film, and the interlayer insulating film
3 and a metal electrode 14 which is an aluminum electrode through a contact hole.

In the conventional semiconductor device shown in FIG. 7, the lower gate electrode 4 and the lower gate insulating film 10 are provided on the insulating film 2, and the active layer region 7 is formed on the lower gate electrode 4 and the lower gate insulating film 10. In the invention, the lower gate electrode 4 and the lower gate insulating film 10 are provided on the silicon oxide film which is the insulating film 2, and the silicon nitride film 3 is provided on the region other than the seed region 6,
The active layer region 7 is provided.

In the conventional example, since the chemically stable silicon oxide film is the interface with the solid phase growth film, distortion and defects are likely to occur during solid phase growth.

Further, many such defects are concentrated on the steps of the lower gate electrode 4 and the reliability of the solid phase growth film is lowered, and the solid phase growth distance is shortened.

On the other hand, an amorphous silicon film to be the active layer region 7 and a region other than the seed region 6 including the lower gate electrode 4 and the lower gate insulating film 10 formed on the insulating film 2 as in the present invention. The silicon nitride film 3 is interposed between the two.

Then, since the silicon is stoichiometrically more silicon than the silicon oxide film, the composition of the interface with the silicon film which is the active layer region 7 is continuously changed from the silicon nitride film 3 and is a stable interface. And the stress generated between the single crystal silicon substrate 1 and the single crystal silicon substrate 1 can be relaxed.

That is, it is possible to alleviate defects such as concentration in the step portion of the lower gate electrode 4, increase the reliability of the solid phase growth film itself, and increase the solid phase growth distance.

Next, a manufacturing method for forming the structure of the semiconductor device shown in FIG. 5 will be described with reference to the sectional views of FIGS.

First, as shown in FIG. 1, <11
A single crystal silicon substrate 1 having facets in the <100> direction inclined by 45 ° with respect to the 0> facet was prepared, and the insulating film 2 having a film thickness of 300 nm was formed at a temperature of 1000 ° C. in a mixed gas atmosphere of oxygen and nitrogen. A silicon oxide film is formed.

Then, the polycrystal silicon film 15 to be the lower gate electrode 4 is formed by the chemical vapor deposition method under a reduced pressure, using a silane-based gas at a temperature of 610 ° C. and a pressure of 0.3 Torr. It is formed with a thickness of 300 nm.

Next, ⁷⁵ As ⁺ ions are implanted into the polycrystalline silicon film which will be the lower gate electrode 4, and the energy 40 is applied.
Ion implantation is performed with KeV and a dose of 1 × 10 ¹⁵ atoms / cm ² .

Next, as shown in FIG. 2, a region to be the lower gate electrode 4 is covered with a photoresist by using a photolithography technique, and the other region is etched by plasma using a chlorine-based gas.

Next, in an oxygen atmosphere at 900 ° C., about 10
A lower gate insulating film 10 having a thickness of nm is formed.

Next, on the entire surface including the lower gate electrode 4,
The temperature is 700 ° C., and the reaction gas is dichlorosilane (Si
A silicon nitride film 3 having a film thickness of 10 nm is formed by a chemical vapor deposition method in a mixed gas atmosphere of ₂ H ₂ Cl ₂ ) and ammonia (NH ₃ ).

Next, as shown in FIG. 3, patterning is performed by photolithography so that the areas other than the seed regions 6 are covered with photoresist, and CF ₄ and CBr, which are halogen gases, are used.
The silicon nitride film 3 in the seed region 6 is removed at a power of 50 W and a pressure of 100 mTorr in a mixed gas atmosphere of F ₃ , helium (He), and oxygen (O ₂ ).

After that, the silicon oxide film which is the insulating film 2 in the seed region 6 is removed with a hydrofluoric acid-based aqueous solution to expose the surface of the single crystal silicon substrate 1 in the seed region 6.

Then, in a reduced pressure chemical vapor deposition apparatus,
After vacuuming at a pressure of about 1 × 10 ⁻⁵ Torr, a mixed gas of chlorine (Cl ₂ ) and hydrogen (H ₂ ) is introduced into the tube,
Under the conditions of a pressure of 0.3 mTorr and a temperature of 570 ° C., the single crystal silicon substrate 1 processed so far is held in the tube for 10 minutes.

As a result, the surface of the single crystal silicon substrate 1 including the seed region 6 is etched to expose the clean surface of the single crystal silicon substrate 1.

As the surface treatment of the single crystal silicon substrate 1 which is the surface of the seed region 6, hydrogen (H ₂ ) treatment may be performed for 30 minutes or longer at a temperature of 950 ° C. or higher.

Subsequently, as shown in FIG. 4, the same chemical vapor deposition apparatus was continuously used, and the temperature was 570 ° C. and the pressure was 0.
An amorphous silicon film to be the active layer region 7 is formed with a thickness of 300 nm by using monosilane gas (SiH ₄ ) at 3 Torr.

After that, heat treatment is performed for 10 hours at a temperature of 570 ° C. in a nitrogen atmosphere at a flow rate of 2000 cc / min, and subsequently, heat treatment at 1000 ° C. is continuously performed for 2 hours.

By performing this two-step heat treatment, the amorphous silicon film in which the bond distance and bond angle between the silicon atoms are fluctuated is a single crystal having an interatomic arrangement as a crystal. Using the silicon substrate 1 as a seed crystal, particles are moved or rearranged at the interface between them to grow into a continuous crystal film, and the amorphous silicon film in the upper part of the seed region 6 and in the periphery thereof including the lateral direction becomes a single crystal silicon film. Convert.

In the semiconductor device structure of the present invention, as compared with the structure shown in the conventional example, the distance from the end of the seed region 6 to the single crystal silicon substrate 1 in the horizontal direction is approximately doubled, that is, 5 times.
μm.

Next, as shown in FIG. 5, the active layer region 7 except the seed region 6 converted into the single crystal silicon film by the photolithography technique is processed into an island shape by using chlorine-based plasma.

In the conventional semiconductor device structure, the solid phase growth distance is short, and the lower gate electrode 4 and the upper gate electrode 5 are
It was necessary to make it close to the seed region 6, and a transistor fabrication region sufficient to completely separate the seed region 6 could not be taken.

In the embodiment of the present invention described above, the seed region is completely separated, but the active layer region 7
May be processed into an island shape so as to include the seed region 7.

Next, a silicon oxide film to be the upper gate insulating film 11 is formed over the entire surface to a thickness of about 10 nm in an oxygen atmosphere.

Next, a polycrystalline silicon film, which is a material for the upper gate electrode 5, is formed in a monosilane atmosphere at a temperature of 610 ° C. to a thickness of 350 nm.

Next, the region to be the upper gate electrode 5 is covered with a photoresist by photolithography, and the polycrystalline silicon film is etched with chlorine-based plasma to form the upper gate electrode 5.

Next, a mask oxide film 12 which is a silicon oxide film is formed to a thickness of 10 nm in an oxygen atmosphere, and ⁷⁵ As ⁺ ions are implanted with an energy of 40 KeV and an implantation amount of 1 × 1.
Ion implantation is performed at 0 ¹⁵ atoms / cm ² to form the source region 8 and the drain region 9.

Here, the mask oxide film 12 is a buffer layer at the time of ion implantation into the source region 8 and the drain region 9, and the impurities contained in the interlayer insulating film 13 are diffused below the upper gate electrode 5 to form a threshold value. It serves as a stopper to prevent the voltage from fluctuating.

After that, the interlayer insulating film 13 is formed in the same manner as in the usual semiconductor element manufacturing method, and after the contact hole is formed, the metal electrode 14 is formed.

After that, a heat treatment in a hydrogen atmosphere at a temperature of 380 ° C. for a time of 25 minutes is performed, followed by a heat treatment in a nitrogen atmosphere at the same temperature for a temperature of 15 minutes, and a double gate type electric field having a structure as shown in FIG. An effect type thin film transistor is obtained.

A graph of FIG. 6 shows an example of characteristics of a double-gate type field effect thin film transistor of N type conductivity obtained by the structure of the semiconductor device and the manufacturing method thereof described above. The graph of FIG. 6 compares the characteristics of the drain current with respect to the upper gate voltage between the conventional example and the structure of the present invention, and shows the subthreshold coefficient when the distance from the end of the seed region 6 to the end of the gate electrode is changed. It is the result obtained. Here, the subthreshold coefficient indicates the gate voltage required for the drain current to increase by one digit.

At this time, the gate length is 0.6 μm, and the lower gate electrode 4 and the upper gate electrode 5 are moved by the same distance. The manufacturing conditions and manufacturing process are the same, and the drain voltage during measurement is 2V.

In the conventional semiconductor device, the subthreshold coefficient increases when the distance from the end of the seed region 6 to the end of the gate electrode becomes 2.5 μm or more. On the other hand, in the semiconductor device of the present invention, the seed region 6
When the distance from the edge to the edge of the gate electrode is about 4.5 μm, the change of the subthreshold coefficient is hardly recognized.

This indicates that the channel region under the gate electrode contains a polycrystalline silicon film which has not been single-crystallized, in addition to the solid phase growth film converted into the single crystal silicon film.

That is, since the polycrystalline silicon film is included in the channel region, carriers are scattered by the crystal grain boundaries and film defects, and the responsiveness of the transistor is lowered, which causes an increase in the subthreshold coefficient. Has appeared in.

In the graph of FIG. 6, the subthreshold coefficient gradually increases and saturates at a certain value.
At the beginning of the increase, the proportion of the single crystal silicon film of the solid phase growth film is smaller than that of the polycrystalline silicon film, and it is shown that the proportion of the polycrystalline silicon film contained in the channel region increases as the distance from the seed region 6 increases. There is.

That is, FIG. 6 shows that the semiconductor device of the present invention is solid-phase grown as a single crystal silicon film in the horizontal direction with the single crystal silicon substrate 1 as compared with the conventional semiconductor device. is there.

Therefore, by using the structure of the present invention, the solid phase growth distance is expanded, and the design margin such as the gate size and the distance from the seed region end to the gate electrode end is also expanded.

Although the N-type double gate type field effect thin film transistor has been described in the above-mentioned embodiments, the structure and manufacturing method of the present invention are applied to the P type double gate type field effect thin film transistor. Also, the same effects as those described above can be obtained.

[0074]

As described above, in the structure of the semiconductor device of the present invention and the manufacturing method thereof, the silicon nitride film is provided in the region including the lower gate electrode and other than the seed region. As a result, it is possible to reduce strain and film defects that occur during solid phase growth.

As a result, geometrical problems such as defects concentrated on the steps of the lower gate electrode are alleviated, and the solid-phase growth distance can be increased. Further, the expanded solid-phase growth distance also expands the design margin such as the gate size and the distance from the end of the seed region to the end of the gate electrode.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing process of a manufacturing method thereof according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing process of a manufacturing method thereof according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing process of a manufacturing method thereof according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing process of the manufacturing method thereof in the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing process of the manufacturing method thereof in the embodiment of the present invention.

FIG. 6 shows a distance from a seed region end to a gate electrode end and a subthreshold coefficient of an N-type field effect thin film transistor in a semiconductor device of an embodiment of the present invention and an N type field effect thin film transistor in a conventional technique. It is a graph which shows the relationship of.

FIG. 7 is a cross-sectional view showing a semiconductor device in a conventional example.

FIG. 8 is a plan view for explaining the solid phase growth method.

[Explanation of symbols]

 1 Single Crystal Silicon Substrate 2 Insulating Film 3 Silicon Nitride Film 4 Lower Gate Electrode 5 Upper Gate Electrode 6 Seed Region 7 Active Layer Region 8 Source Region 9 Drain Region

Claims (11)

[Claims] 1. An insulating film provided on a single crystal silicon substrate, a lower gate electrode made of a polycrystalline silicon film provided on the insulating film, a lower gate insulating film provided on the lower gate electrode, and a region other than a seed region. A silicon nitride film provided on the silicon nitride film, an active layer region provided on the silicon nitride film, an upper gate insulating film provided on the surface of the active layer region, an upper gate electrode provided on the upper gate insulating film, and a region matching the upper gate electrode. A semiconductor device comprising a source region and a drain region provided in an active layer region. 2. An insulating film made of a silicon oxide film provided on a single crystal silicon substrate, a lower gate electrode made of a polycrystalline silicon film provided on the insulating film, and a lower gate insulating film provided on the lower gate electrode. A silicon nitride film provided in a region other than the seed region, an active layer region provided on the silicon nitride film, an upper gate insulating film provided on the surface of the active layer region, an upper gate electrode provided on the upper gate insulating film, and an upper gate A semiconductor device comprising a source region and a drain region provided in an active layer region of a region matching with an electrode. 3. An insulating film made of a silicon oxide film provided on a single crystal silicon substrate, a lower gate electrode made of a polycrystalline silicon film provided on the insulating film made of the silicon oxide film, and a lower portion provided on the lower gate electrode. A gate insulating film, a silicon nitride film provided in a region other than the seed region,
An active layer region formed of a single crystal silicon film or a polycrystalline silicon film provided on a silicon nitride film, an upper gate insulating film provided on the surface of the active layer region, an upper gate electrode provided on the upper gate insulating film, and an upper gate A semiconductor device comprising a source region and a drain region provided in an active layer region of a region matching with an electrode. 4. A step of forming an insulating film on a single crystal silicon substrate and forming a lower gate electrode made of a polycrystalline silicon film on the insulating film, and forming a lower gate insulating film on the entire surface including the lower gate electrode. And the step of forming a silicon nitride film, the step of removing the silicon nitride film in the seed region and the insulating film in the seed region, the seed region where the surface of the polycrystalline silicon substrate is exposed is cleaned, and the entire surface is amorphous. A step of forming a high-quality silicon film, a step of heat-treating in a nitrogen atmosphere to convert the amorphous silicon film into a single-crystal silicon film, and separating the single-crystal silicon film from the region except the seed region into islands to form an upper gate. A method of manufacturing a semiconductor device, comprising: a step of forming an insulating film; a step of forming an upper gate electrode; and a step of forming a source region and a drain region. 5. An insulating film provided on a single crystal silicon substrate, and a seed region in which a surface of the single crystal silicon substrate is exposed,
A lower gate electrode made of a polycrystalline silicon film provided on the insulating film, a lower gate insulating film provided on the lower gate electrode, and a silicon nitride film provided in a region other than the seed region,
An active layer region provided on the silicon nitride film, an upper gate insulating film provided on the surface of the active layer region, an upper gate electrode provided on the upper gate insulating film, and a source region provided on the active layer region in a region matching the upper gate electrode. And a drain region. 6. An insulating film made of a silicon oxide film provided on a single crystal silicon substrate, a seed region where the single crystal silicon substrate is exposed, a lower gate electrode made of a polycrystalline silicon film provided on the insulating film, and a lower portion thereof. A lower gate insulating film provided on the gate electrode, a silicon nitride film provided in a region other than the seed region, an active layer region provided on the silicon nitride film, an upper gate insulating film provided on the surface of the active layer region, and an upper gate insulating film A semiconductor device comprising: an upper gate electrode provided on an upper part of the semiconductor device; and a source region and a drain region provided in an active layer region of a region matching the upper gate electrode. 7. An insulating film made of a silicon oxide film provided on a single crystal silicon substrate, a seed region where the single crystal silicon substrate is exposed, a lower gate electrode made of a polycrystalline silicon film provided on the insulating film, and a lower gate. A lower gate insulating film provided on the electrode, a silicon nitride film provided in a region other than the seed region, an active layer region formed of a single crystal silicon film or a polycrystalline silicon film provided on the silicon nitride film, and an active layer region surface. A semiconductor device comprising: an upper gate insulating film provided; an upper gate electrode provided on the upper gate insulating film; and a source region and a drain region provided in an active layer region of a region matching the upper gate electrode. 8. A step of forming an insulating film on a single crystal silicon substrate to form a lower gate electrode made of a polycrystalline silicon film, a step of forming a lower gate insulating film on the lower gate electrode, and a silicon nitride film. And a step of removing the silicon nitride film in the seed region and the insulating film in the seed region, a step of cleaning the seed region where the surface of the single crystal silicon substrate is exposed, and forming an amorphous silicon film over the entire surface. , A step of converting the amorphous silicon film into a single crystal silicon film by heat treatment in a nitrogen atmosphere, a step of separating the single crystal silicon film into islands so as to include a seed region, and forming an upper gate insulating film, A method of manufacturing a semiconductor device, comprising: a step of forming an upper gate electrode; and a step of forming a source region and a drain region. 9. An insulating film provided on a single crystal silicon substrate, a seed region in which a surface of the single crystal silicon substrate is exposed,
A lower gate electrode made of a polycrystalline silicon film provided on the insulating film, a lower gate insulating film provided on the lower gate electrode, and a silicon nitride film provided in a region other than the seed region,
The active layer region provided on the silicon nitride film, the upper gate insulating film provided on the surface of the active layer region, the upper gate electrode provided on the upper gate insulating film, and the active layer region on the seed region side of the region matching the upper gate electrode. Source area to
A semiconductor device comprising: a drain region provided in an active layer region opposite to a seed region with an upper gate electrode sandwiching a region aligned with the upper gate electrode. 10. An insulating film made of a silicon oxide film provided on a single crystal silicon substrate, a seed region where the single crystal silicon substrate is exposed, and a lower gate made of a polycrystalline silicon film provided on the insulating film made of a silicon oxide film. An electrode, a lower gate insulating film provided on the lower gate electrode, a silicon nitride film provided in a region other than the seed region, an active layer region provided on the silicon nitride film, and an upper gate insulating film provided on the surface of the active layer region, The upper gate electrode provided on the upper gate insulating film, the source region provided on the active layer region on the seed region side of the region matching the upper gate electrode, and the seed region sandwiching the upper gate electrode in the region matching the upper gate electrode. And a drain region provided in an active layer region opposite to the semiconductor device. 11. An insulating film made of a silicon oxide film provided on a single crystal silicon substrate, a seed region where the single crystal silicon substrate is exposed, and a lower gate made of a polycrystalline silicon film provided on the insulating film made of a silicon oxide film. An electrode, a lower gate insulating film provided on the lower gate electrode, a silicon nitride film provided in a region other than the seed region, and an active layer region made of a single crystal silicon film or a polycrystalline silicon film provided on the silicon nitride film, The upper gate insulating film provided on the surface of the active layer region, the upper gate electrode provided on the upper gate insulating film, the source region provided on the active layer region on the seed region side of the region matching the upper gate electrode, and the upper gate electrode A drain region provided in the active layer region opposite to the seed region with the upper gate electrode in the matching region interposed therebetween. Semiconductor device.