JPH08288466A - MOS semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To suppress the generation of current due to a parasitic bipolar transistor generated in an active region of a MOS semiconductor device. A parasitic bipolar current suppressing region (P-type high-concentration impurity layer) is provided between an offset drain region (N-type low-concentration impurity layer 15) and a source region (N-type high-concentration impurity layer 24) in an active region. 21) is formed.
On the field region side, a channel stopper region (P-type high concentration impurity layer 20) for increasing the threshold value of the parasitic MOS transistor 300 is formed under the thick selective oxide film 18a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS (Metal Oxide Semiconductor) semiconductor device having an offset drain structure and a method for manufacturing the same, and more particularly to selective oxidation (LOC).
The present invention relates to a MOS semiconductor device in which an element isolation region (field region) is formed by an OS (Local Oxidation of Silicon) method and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, for example, CCD (Charge Coupled D
CMOS (Complementl) used for evice driver
(y Metal Oxide Semiconductor) In semiconductor devices, while miniaturization progresses, the power supply voltage is constant, so the electric field strength in the drain region increases, hot carriers are generated, and new electron-hole pairs are generated. As a result, the threshold voltage of the MOS transistor fluctuates and the drain voltage drops. This tendency is more likely to occur in electrons than in holes, and has been a problem particularly on the N-channel MOS transistor side.

In order to solve such a problem, conventionally,
In the N-channel MOS transistor region, an N-type drain region is formed separately from the gate electrode, and an N-type low concentration layer is also formed continuously in the drain region, so that an electric field near the drain region is formed. A so-called offset drain structure that avoids concentration is adopted to achieve high breakdown voltage.

On the other hand, in this type of CMOS semiconductor device,
The LOCOS method is adopted as an element isolation technique, and a thick oxide film is formed in the field region. In the CMOS semiconductor device in which the thick field oxide film is formed, the wiring made of polycrystalline silicon or the like is formed on the thick oxide film, so that the parasitic MOS transistor is inevitably generated in the field region.

In order to reduce the influence of the parasitic MOS transistor generated in this field region, ion implantation is performed from above the selective oxide film to form an impurity layer (channel stopper) of the same conductivity type as the substrate to form a threshold value ( Increase V _th ),
The so-called channel stopper method is adopted.

FIG. 4 shows an N of a CMOS semiconductor device having a conventional offset drain and channel stopper structure.
It shows a manufacturing process on the channel transistor side.

That is, as shown in FIG.
A thin silicon oxide film (S) is formed on the semiconductor substrate (silicon substrate) 111 in which the mold well region 112 is formed by thermal oxidation.
iO ₂ ) 113 is formed. Then, CVD (Chemica
After forming a silicon nitride film (Si ₃ N ₄ ) 114 as an oxidation resistant film on the entire surface by the vapor deposition method, the silicon nitride film 114 is etched to form a selective oxide film pattern (LOCOS pattern).

Subsequently, N-type impurity ions are selectively implanted using the patterned silicon nitride film 114 as a mask to form an N-type low-concentration impurity layer 115 to be an offset drain in a region where an offset drain is to be formed. At the same time, the N-type low-concentration impurity layers 116 and 117 are formed in the field formation region.

Successively, selective oxidation is performed using the silicon nitride film 114 as a mask, and as shown in FIG. 4B, the low concentration impurity layer 115 and the low concentration impurity layers 116 and 117.
Thick selective oxide films 118b and 118a are formed thereon. Then, after removing the silicon nitride film 114, the selective oxide film 118a in the field region is formed on the entire surface.
A resist film 119 having an opening 119a is formed corresponding to the above. Then, impurity ions are introduced using this resist film 119 as a mask to form P as a channel stopper region.
A mold high concentration impurity layer 120 is formed.

Next, as shown in FIG. 4C, CVD
After a polycrystalline silicon layer is formed on the entire surface by the method and impurity ions are introduced, the polycrystalline silicon layer is patterned to form the gate electrode 123 of the MOS transistor in the active region and the wiring layer 122 in the field region. Form. Then, the gate electrode 1
23 and the selective oxide films 118a and 118b are used as a mask to perform ion implantation to form an N-type high-concentration impurity layer 124 which becomes a source region of the MOS transistor, and at the same time, between the low-concentration impurity layer 115 and the low-concentration impurity layer 116. Then, an N-type high-concentration impurity layer 125 to be a drain region is formed.

[0011]

As described above, the conventional CM is used.
The OS semiconductor device has an offset drain structure, and a channel stopper (P-type high concentration impurity layer 120) is formed for the parasitic MOS transistor generated in the field region to raise the threshold value (V _th ). Therefore, the high breakdown voltage is attempted, but the following problems occur in the active region.

That is, in the active region where the MOS transistor is formed, the source (high concentration impurity layer 12
4), the substrate (well region 112) and the drain (high-concentration impurity layer 125) have an NPN structure.
The parasitic bipolar transistor 130 shown in FIG. There is a problem that a current (parasitic bipolar current) flows between the emitter and the base of the parasitic bipolar transistor 130 (that is, between the source and the well region of the MOS transistor), which lowers the breakdown voltage of the MOS transistor.

The present invention has been made in view of the above problems, and an object thereof is to provide a MOS semiconductor device capable of suppressing a parasitic bipolar current generated in an active region and a manufacturing method thereof.

[0014]

SUMMARY OF THE INVENTION A MOS semiconductor device of the present invention is a MOS semiconductor device in which a MOS transistor is formed in an active region and a parasitic MOS transistor is generated in a field region. A gate electrode of a MOS transistor formed on the surface of the semiconductor substrate via an insulating film, a source region of a MOS transistor formed of a high-concentration impurity layer of the other conductivity type formed in the semiconductor substrate, and the gate in the semiconductor substrate. A drain region of a MOS transistor formed of a high-concentration impurity layer of the other conductivity type formed at a position separated from the electrode, and a low-concentration impurity layer formed between the drain region in the semiconductor substrate and the gate electrode. Offset drain region, the offset drain region and the source in the semiconductor substrate And a parasitic bipolar current suppressing region formed of a high-concentration impurity layer of one conductivity type and a channel stopper region of a parasitic MOS transistor formed in the field region formed of a high-concentration impurity layer of one conductivity type. It has and.

The MOS semiconductor device of the present invention is particularly suitable for CMs.
It is applied to a semiconductor device having an OS structure. In this case,
The MOS transistor is an N-channel transistor, and the source region, the drain region, and the offset drain region are each formed of an N-type impurity layer,
The parasitic bipolar current suppressing region and the channel stopper region are each formed of a P-type impurity layer.

Further, it is preferable that the parasitic bipolar current suppressing region is formed at a position lower than a channel region formed between the source region and the drain region of the MOS transistor.

A method of manufacturing a MOS semiconductor device according to the present invention comprises:
On the other hand, a pattern of an oxidation resistant film is formed on the main surface of a conductive type semiconductor substrate, and impurity ions are selectively introduced using the oxidation resistant film as a mask to form an offset drain in an offset drain formation planned region. Forming a first low-concentration impurity layer and forming a second low-concentration conductivity type second low-concentration impurity layer in the field formation planned region; and performing selective oxidation using the oxidation resistant film as a mask. Forming a thick selective oxide film on each of the low-concentration impurity layer and the second low-concentration impurity layer, and after removing the oxidation resistant film, an active region and a field region are formed on the semiconductor substrate. A resist film having an opening corresponding to each selective oxide film is formed, and impurity ions are introduced using the resist film as a mask to form a parasitic bipolar current suppressing region. A step of simultaneously forming an electric conductivity type first high-concentration impurity layer and a second conductivity type second high-concentration impurity layer to be a channel stopper region; and a gate electrode of a MOS transistor above the parasitic bipolar current suppressing region. After the formation, impurity ions are introduced by using the gate electrode and the selective oxide film as a mask to form a first high-concentration impurity layer of the other conductivity type serving as a source region, and at the same time as the first low-concentration impurity layer. And a step of forming a second high-concentration impurity layer of the other conductivity type which becomes a drain region between the second low-concentration impurity layer and the second low-concentration impurity layer.

[0018]

In the MOS semiconductor device of the present invention, the parasitic bipolar current suppressing region formed of the high-concentration impurity layer having the same conductivity type as the base is formed in the active region between the offset drain region and the source region. For,
Generation of current (parasitic bipolar current) by the parasitic bipolar transistor is suppressed.

Further, in the method of manufacturing a MOS semiconductor device of the present invention, the first high concentration impurity layer which becomes the parasitic bipolar current suppressing region and the second high concentration impurity layer which becomes the channel stopper region are simultaneously formed.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a structure of an N-channel transistor side of a CMOS semiconductor device according to an embodiment of the present invention.

In this CMOS semiconductor device, a P-type well region 12 is formed on the surface of a semiconductor substrate (silicon substrate) 11, and an N region is formed in the active region of the P-type well region 12.
A channel MOS transistor 200 is formed.
On the other hand, in the field region, the parasitic MOS transistor 30
0 has occurred.

The MOS transistor 200 includes a gate electrode 23 formed on the surface of the P-type well region 12 via an insulating film (silicon oxide film 13) and a source region (N-type) formed in the P-type well region 12. High concentration impurity layer 24)
And a drain region (N-type high-concentration impurity layer 25) formed at a position separated from the gate electrode 23. An offset drain region (N-type low-concentration impurity layer 15) is formed under the thick selective oxide film 18b between the drain region and the gate electrode 23.

In the present embodiment, the channel region of the MOS transistor 200 is further provided between the offset drain region (N type low concentration impurity layer 15) and the source region (N type high concentration impurity layer 24) of the active region. A parasitic bipolar current suppressing region (P-type high-concentration impurity layer 21) is formed at a position lower than the above.

On the other hand, on the field region side, under the thick selective oxide film 18a, together with the N type low concentration impurity layers 16 and 17, a channel stopper region (P type of the P type) for increasing the threshold value of the parasitic MOS transistor 300 is formed. A high concentration impurity layer 20) is formed.

As described above, in the CMOS semiconductor device of this embodiment, the N-channel MOS in the active region is formed.
Immediately below the transistor 200, a substrate (P-type well region 1
A high-concentration impurity layer 21 (parasitic bipolar current suppressing region) of the same conductivity type as 2) is formed. Here, a parasitic NPN bipolar transistor 400 is generated in this region as schematically shown in FIG. The characteristics of the parasitic NPN bipolar transistor 400 are governed by the behavior of minority carriers (electrons) injected from the emitter (that is, the N-type high concentration layer 24) into the base layer (that is, the P-type well region 12). In the present embodiment, the presence of the parasitic bipolar current suppressing region (P-type high concentration impurity layer 21) reduces the generation of minority carriers (electrons) and suppresses the parasitic bipolar current flowing between the emitter and the base.
That is, as shown in FIG. 3, the current limiting resistor R _B is inserted in the base of the parasitic bipolar transistor 400.

Next, a method of manufacturing this CMOS semiconductor device will be described with reference to FIG.

First, as shown in FIG. 2A, a semiconductor substrate (silicon substrate) in which a P-type well region 12 is formed.
A thin silicon oxide film 13 is formed on 11 by thermal oxidation. Then, after forming a silicon nitride film 14 as an oxidation resistant film by a CVD (Chemical Vapor Deposition) method, the silicon nitride film 14 is etched to form a selective oxide film pattern (LOCOS pattern).

Then, N-type impurity ions are selectively implanted using the patterned silicon nitride film 14 as a mask to form an N-type low-concentration impurity layer 15 (first 1 low concentration impurity layer) and N type low concentration impurity layers 16 and 17 (second low concentration impurity layer) are formed in the field formation planned region.

Subsequently, selective oxidation is performed using the silicon nitride film 14 as a mask, and as shown in FIG. 2B, a thick film selective oxidation is performed on the low-concentration impurity layer 15 and the low-concentration impurity layers 16 and 17, respectively. The films 18b and 18a are formed, respectively. Subsequently, after removing the silicon nitride film 14, the resist film 1 having openings 19a and 19b on the entire surface corresponding to the selective oxide films 18a and 18b in the field region, respectively.
9 is formed. Impurity ions are introduced using the resist film 19 as a mask to form a high-concentration impurity layer 21 (first high-concentration impurity layer) of one conductivity type which becomes a parasitic bipolar current suppressing region and a P-type high concentration which becomes a channel stopper region. The concentration impurity layer 120 (second high concentration impurity layer) is formed at the same time.

Next, as shown in FIG. 2C, CVD
After forming a polycrystalline silicon layer on the entire surface by the method and introducing impurity ions, this polycrystalline silicon layer is patterned to form the gate electrode 23 of the MOS transistor in the active region and the wiring layer 22 in the field region. Form. Subsequently, ion implantation is performed using the gate electrode 23 and the selective oxide films 18a and 18b as a mask to form an N-type high-concentration impurity layer 24 which becomes a source region of the MOS transistor, and at the same time, the low-concentration impurity layer 15 and the low-concentration impurity layer 15 are formed. An N-type high-concentration impurity layer 25 to be a drain region is formed between the layer 16 and the layer 16. Through the above steps, the CMOS semiconductor device shown in FIG. 1 can be realized.

According to such a method, the high-concentration impurity layer 21 which becomes the parasitic bipolar current suppressing region and the high-concentration impurity layer 20 which becomes the channel stopper region can be simultaneously formed. That is, there is no need to newly add a process for forming the parasitic bipolar current suppressing region, and the conventional process can be used as it is.

Although the structure of the N-channel MOS transistor side in the CMOS semiconductor device has been described in the above embodiment, the structure is not limited to the CMOS semiconductor device.
It goes without saying that the present invention can also be applied to the case of the structure of the channel MOS transistor alone.

[0034]

As described above, in the MOS semiconductor device of the present invention, a parasitic bipolar current formed of a high-concentration impurity layer of the same conductivity type as that of the substrate is located in the active region between the offset drain region and the source region. Since the suppression region is formed, it is possible to suppress the generation of the parasitic bipolar current and to achieve a higher breakdown voltage.

Further, in the method of manufacturing a MOS semiconductor device of the present invention, the first high concentration impurity layer which becomes the parasitic bipolar current suppressing region and the second high concentration impurity layer which becomes the channel stopper region are simultaneously formed. Therefore, the MOS semiconductor device of the present invention can be easily realized without increasing the number of steps for forming the parasitic bipolar current suppressing region.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a structure of a CMOS semiconductor device according to an embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view showing a manufacturing process of the CMOS semiconductor device of FIG.

FIG. 3 is a vertical cross-sectional view for explaining the effect of the CMOS semiconductor device of FIG.

FIG. 4 is a vertical cross-sectional view showing a manufacturing process of a conventional CMOS semiconductor device.

5 is a vertical cross-sectional view for explaining a problem of the CMOS semiconductor device of FIG.

[Explanation of symbols]

 11 silicon substrate 12 P-type well region 14 silicon nitride film (oxidation resistant film) 15 low concentration impurity layer (offset drain region) 20 high concentration impurity layer (channel stopper region) 21 high concentration impurity layer (parasitic bipolar current suppression region) 23 gate electrode 24 high concentration impurity layer (source region) 25 high concentration impurity layer (drain region) 200 N-channel MOS transistor 300 parasitic MOS transistor 400 parasitic bipolar transistor

Claims (5)

[Claims] 1. A MOS semiconductor device having a MOS transistor formed in an active region and a parasitic MOS transistor formed in a field region, wherein the MOS is formed on the surface of a conductive type semiconductor substrate through an insulating film. A gate electrode of a transistor, a source region of a MOS transistor formed of a high-concentration impurity layer of the other conductivity type formed in the semiconductor substrate, and another conductivity type formed in a position in the semiconductor substrate separated from the gate electrode. Composed of a high-concentration impurity layer of
A drain region of the transistor, an offset drain region formed of a low-concentration impurity layer formed between the drain region in the semiconductor substrate and the gate electrode, and the offset drain region and the source region in the semiconductor substrate. A parasitic bipolar current suppressing region formed of a high-concentration impurity layer of one conductivity type and a channel stopper region of a parasitic MOS transistor formed in the field region formed of a high-concentration impurity layer of one conductivity type A MOS semiconductor device characterized by the above. 2. The MOS transistor is a complementary MOS
An N-channel transistor that forms a transistor, wherein the source region, the drain region, and the offset drain region are each formed of an N-type impurity layer,
The MOS semiconductor device according to claim 1, wherein the parasitic bipolar current suppressing region and the channel stopper region are each formed of a P-type impurity layer. 3. The parasitic bipolar current suppressing region is M
3. The MOS semiconductor device according to claim 2, wherein the MOS semiconductor device is formed below a channel region formed between the source region and the drain region in the OS transistor. 4. A pattern of an oxidation resistant film is formed on a main surface of a conductive type semiconductor substrate, and impurity ions are selectively introduced using the oxidation resistant film as a mask to form an offset drain in a region where an offset drain is to be formed. Forming a second low-concentration impurity layer of the other conductivity type and a second low-concentration impurity layer of the other conductivity type in the field formation planned region, and performing selective oxidation using the oxidation resistant film as a mask. A step of forming a first selective oxide film on the first low-concentration impurity layer and a second selective oxide film on the second low-concentration impurity layer; and After the removal, a first selective oxide film and a resist film having openings corresponding to the first selective oxide film are formed on the semiconductor substrate, and impurity ions are introduced using the resist film as a mask to make parasitic Ba A step of simultaneously forming a first high-concentration impurity layer of one conductivity type that becomes a polar current suppressing region and a second high-concentration impurity layer of one conductivity type that becomes a channel stopper region; and a position above the parasitic bipolar current suppressing region. After forming the gate electrode of the MOS transistor in the substrate, ion implantation is performed using the gate electrode and the selective oxide film as a mask to form the other high conductivity type first high-concentration impurity layer to be the source region, and at the same time, the first Forming a second high-concentration impurity layer of the other conductivity type, which becomes a drain region, between the low-concentration impurity layer and the second low-concentration impurity layer. . 5. The MOS transistor is a complementary MOS
As an N-channel transistor that constitutes a transistor,
5. The source region, the drain region and the offset drain region are each formed of an N-type impurity layer, and the parasitic bipolar current suppressing region and the channel stopper region are each formed of a P-type impurity layer. A method for manufacturing the described MOS semiconductor device.