JPH08298287A - Metal wiring of semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] To prevent spattering of metal wiring in the lower layer during via hole etching, to achieve good reproducibility and low damage. A tungsten film having a thickness of 50 nm is formed as a metal layer 3 on the entire surface of a conductor layer 2 mainly made of aluminum, a resist pattern is formed by a photolithography method, and the resist pattern is used as a mask to form the metal layer 3. Conductor layer 2
Are simultaneously etched to form wiring. An interlayer insulating film 4 is formed thereon, a via hole resist pattern 5 is formed thereon, and dry etching is performed using the resist 5 as a mask and an etching gas containing fluorine. Polymer 8-at the bottom of the hole by over-etching
1, 8-2 are deposited, and the polymers 8-1, 8-2 suppress the sputtering of the lower metal layer 3 and the conductor layer 2 thereunder. The polymers 8-1 and 8-2 are removed together with the resist by ashing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device characterized by the step of forming a metal wiring used in a semiconductor device and a via hole connecting between a lower layer and an upper layer metal wiring.

[0002]

2. Description of the Related Art Aluminum-based wiring made of aluminum or an aluminum alloy containing a small amount of Si or Cu in aluminum is used as a metal wiring of a semiconductor device. A silicon oxide film-based interlayer insulating film is formed between the lower and upper metal wirings, and a via hole (also referred to as a through hole) is formed in the interlayer insulating film to form a space between the metal wirings formed above and below the interlayer insulating film. Make electrical connection.

In the process of forming a via hole, it is often necessary to form a via hole in a place where the thickness of the interlayer insulating film is greatly different, and the difference in the thickness of the interlayer insulating film is sometimes 2 times the minimum thickness portion of the interlayer insulating film. It may exceed twice. In order to form via holes at such different thicknesses, if a via hole is formed by dry etching using an etching gas containing fluorine, the via hole is formed in a shallow depth, that is, in a thin portion of the interlayer insulating film. The via hole that is formed in this way overetches the underlying metal wiring under the hole more than the via hole formed in the thick portion. If the metal wiring at the bottom of the via hole is made of aluminum-based material only,
Aluminum reacts with fluorine as a reaction gas to form aluminum fluoride at the bottom of the via hole. This fluoride is sputtered by ion-assisted reaction during overetching and adheres to the sidewall of the via hole, or is formed in a frill-like state protruding from the via hole to the surface. Further, since this fluoride is insulating, it increases the resistance value of the via hole and causes a decrease in reliability, which is not preferable.

In order to solve the problem due to the sputtering of the aluminum-based material at the time of over-etching when forming the via holes in the portions having different thicknesses of the interlayer insulating film, the silicon-based material is prevented from being sputtered on the upper layer of the aluminum-based material. It is conceivable to stack them as a film. However, when a silicon-based material is directly laminated on an aluminum-based material, both layers react with each other by heat treatment to form aluminum silicide, which causes defects such as an increase in wiring resistance.

Therefore, a method has been proposed in which a TiON film is interposed as a barrier metal layer as a reaction prevention film between an aluminum-based material layer and a silicon-based material as a sputtering prevention film (JP-A-4-213823). See the bulletin). In the etching step of forming a via hole on the metal wiring having such a structure, the etching condition is mainly an ion assist reaction during the etching of the interlayer insulating film and a radical reaction during the etching of the silicon-based material and the TiON layer thereunder. It is set to be the subject. By doing so, even if the via holes having different depths are formed at the same time and the etching of the interlayer insulating film is completed early in the shallow via hole, the underlying aluminum-based material is not exposed, so that there is an advantage that the aluminum-based material is not sputtered.

However, when the conductor layer in which the silicon-based material is laminated on the aluminum-based material layer via the TiON layer of the barrier metal layer is patterned into the wiring shape by the dry etching method, the same gas should be used for etching. However, it is necessary to switch the etching gas by etching the silicon material and etching the barrier metal layer and the aluminum material layer. Therefore, the process is complicated, the yield is reduced, and the manufacturing cost is increased.

Further, since the etching of the silicon-based material layer and the barrier metal layer formed on the aluminum-based material layer is performed mainly by the radical reaction, each layer is side-etched and the diameter of the hole bottom is partially reduced. Only spread. This lowers the reliability of the via hole and also lowers the degree of freedom in layout design. Further, since the etching process is a more complicated two-step etching, it is difficult to secure reproducibility.

[0008]

SUMMARY OF THE INVENTION According to the present invention, a metal wiring structure capable of preventing the spattering of a metal wiring in a lower layer at the time of etching a via hole and reducing the resistance value of the metal wiring, and a metal wiring structure of a lower layer at the time of etching a via hole are provided. It is an object of the present invention to provide a manufacturing method capable of preventing spatter, achieving good reproducibility and achieving low damage etching.

[0009]

In the metal wiring of the present invention, an aluminum-based material layer made of aluminum or an aluminum alloy is used as a main conductor layer, and the fluoride is volatile in the uppermost layer of the conductor layer. Metal layers are laminated.

The manufacturing method of the present invention is characterized by forming the via hole on the metal wiring by including the following steps (A) to (E). (A) A step of forming a metal wiring in which an aluminum-based material layer made of aluminum or an aluminum alloy is used as a main conductor layer, and a metal layer whose fluoride is volatile is laminated on the uppermost layer of the conductor layer. , (B) a step of forming a silicon oxide film-based interlayer insulating film on the metal wiring, (C) forming a resist film on the interlayer insulating film, and forming the resist so that an opening is formed at a position where a via hole is formed. Patterning the film,
(D) Using the patterned resist film as a mask, dry etching the interlayer insulating film with an etching gas containing fluorine to form a via hole reaching the metal wiring, (E) the resist film and formation An ashing process for removing the polymer layer existing at the bottom of the formed via hole.

The material of the metal layer is preferably tungsten, molybdenum or tantalum. In the main conductor layer, it is preferable that a titanium layer is laminated on at least one of the lower surface and the upper surface of the aluminum-based material layer, which can improve the reliability of the metal wiring.

A silicon oxide film type interlayer insulating film is used as an interlayer insulating film between metal wirings, and CF ₄ , C ₂ F ₆ , C ₄ F ₈ and C are used as an etching gas for forming a via hole.
When dry etching is performed using an etching gas such as HF ₃ or CH ₂ F ₂ , the vapor pressure of the fluoride generated on the metal surface when the metal in the plasma due to the gas containing carbon and fluorine is touched. It is known that when carbon is high, a polymer (fluorocarbon) in which carbon and fluorine are bonded is deposited on the surface (JJAP, Vol.31,
See PP.3731-3735 (1992)). The document states that CHF ₃
When a via hole was formed by dry etching using gas, the surface of Al exposed to CHF ₃ plasma was analyzed, and although a fluoride of Al was observed, it was described that the presence of a polymer was not observed. ing. On the other hand, when silicon or tungsten was exposed to CHF ₃ plasma, the presence of a polymer (fluorocarbon) composed of fluorine or carbon was observed on the surface, and no fluoride of silicon or tungsten was formed. The reason is that when the vapor pressure of the fluoride in a certain material is high, the polymer is deposited on the surface, and conversely, when the vapor pressure of the fluoride is low, the polymer is not deposited. The present invention uses the polymer as an anti-sputtering film.

FIG. 1 shows a state in which an interlayer insulating film is formed on the metal wiring of the present invention, and a via hole is formed in the interlayer insulating film. The metal wiring of the present invention is formed on the interlayer insulating film 1 made of a silicon oxide-based material such as BPSG (boron and phosphorus-containing silicon oxide film) and NSG (silicon oxide film containing no impurities). Here, the aluminum-based material layer 2 is used as the main conductor layer 2.
It is shown that the titanium layers 2a and 2c are laminated on b and the lower surface and the upper surface thereof, respectively. Aluminum-based material layer 2
b is Al or an Al alloy slightly containing Si or Cu in Al, and the film thickness thereof is 300 to 800 nm, preferably 400 to 600 nm, and Al, AlSiCu, Al
It can be formed by a sputtering method using an aluminum-based material such as Cu or AlSi as a target. The Ti layers 2a and 2c have a film thickness of 10 to 50 nm, preferably 20 to
It has a thickness of 40 nm and can be formed by a sputtering method using Ti as a target. The main conductor layer 2 includes the case of only the aluminum-based material layer 2b.
It also includes the case where only one of a and 2c is laminated.

Aluminum-based material layer 2b and Ti layer 2
At the time of forming a and 2c, it is preferable to sequentially stack the layers without exposing the layers to the atmosphere. As a result, it is possible to prevent an oxide from being formed at the interface of each layer, and to form a conductor layer having a good laminated interface without an increase in wiring resistance. In the main conductor layer 2, when a Ti layer is formed on at least one of the lower surface and the upper surface of the aluminum-based material layer 2b, the interface between the aluminum-based material layer 2b and the Ti layer during heat treatment by various processes. An alloying reaction occurs at. This alloying reaction significantly improves the reliability of the wiring.

On the upper surface of the main conductor layer 2, a metal layer 3 whose fluoride is volatile is laminated. This metal layer 3 is preferably a refractory metal of any one of tungsten, molybdenum, and tantalum or a silicide thereof. These refractory metals or their silicides have high fluoride vapor pressures, that is, highly volatile metal layers. The thickness of the metal layer 3 is 10 to 300 nm, preferably 20 to 100 nm. This metal layer 3 is SiH
Mixed gas of ₄ , H ₂ and WF ₆ , SiH ₄ , H ₂ and MoF ₅
Can be formed by a plasma CVD method using a mixed gas of the above or a mixed gas of SiH ₄ , H ₂ and TaF ₆ or a sputtering method using W, Mo or Ta as a target.
As a material of the metal layer 3, any metal other than W, Mo or Ta, such as a refractory metal or a transition metal, can be used as long as the fluoride has a high vapor pressure. Reference numeral 4 is a silicon oxide film-based interlayer insulating film, the thickness of which varies depending on the location under the influence of various steps in the lower layer, for example, metal wiring and element isolation field oxide film (LOCOS oxide film). A via hole 6 is formed in the interlayer insulating film 4.

In the metal wiring shown in FIG. 1, since the metal layer 3 is laminated on the main conductor layer 2, a low resistance wiring can be realized, and the conductor layer 2 and the metal layer 3 are metal wirings. It is possible to perform processing simultaneously in dry etching, and it is possible to secure reproducibility and reduce the process running cost. In addition, the metal layer 3 also acts as an antireflection film for ultraviolet rays during exposure in the photolithography process for forming via holes, and has the effect of preventing halation during resist patterning.

The diameter of the via hole 6 is 0.2 to 0.8 μm, which is a value appropriately determined by the device design rule. Since the thickness of the interlayer insulating film 4 changes depending on the location, the via hole 6 formed in the interlayer insulating film 4 having a different thickness.
Is a hole with different depth depending on the location. During the dry etching for forming the via hole 6, a hole having a shallower depth (a hole in a place where the interlayer insulating film 4 is thin) is over-etched. During this over-etching, the fluorine contained in the etching gas and the metal layer 3 combine to generate a fluoride. Since this fluoride has a high vapor pressure, it volatilizes from the surface. As such reactions proceed,
The proportion of fluorine at the bottom of the hole is relatively reduced, and the polymer is deposited in the state of excess carbon. This polymer deposits as the overetch time increases, so
Shallow via holes result in thicker polymer deposition. This polymer protects the surface of the metal layer 3 and suppresses the main conductor layer 2 from being sputtered during overetching. Since the deposited polymer can be easily removed by oxygen plasma ashing at the time of removing the resist, there is no influence on the subsequent process.

The manufacturing method of the present invention for forming a via hole will be described with reference to FIG. (A) NSG film or B having various steps on the surface under the influence of LOCOS step or lower metal wiring step
CVD of silicon oxide film-based interlayer insulating film 1 such as PSG film
Form by the method. A main conductor layer 2 is formed thereon. As an example, the main conductor layer 2 has a three-layer structure,
The first Ti layer 2a is formed by the sputtering method, and thereafter Al, AlSiCu, Al is formed on the Ti layer 2a without being exposed to the atmosphere.
An aluminum-based wiring material layer 2b such as Cu or AlSi is formed by a sputtering method in another film forming chamber, and then a Ti layer 2c is further formed thereon by a sputtering method in another film forming chamber without being exposed to the atmosphere. Form a film. The Ti layer may be laminated on the upper and lower sides of the aluminum-based wiring material layer 2b, or may be only one. In this way, if the conductor layers 2a to 2c are continuously formed without exposure to the atmosphere, there is no oxidation at the interface between the layers,
It is possible to suppress an increase in wiring resistance.

Next, the metal layer 3 is deposited on the main conductor layer 2 by C
The layers are stacked by the VD method or the sputtering method. Then, a resist pattern is formed on the metal layer 3 by the lithography method. In this photolithography process, the metal layer 3 functions as an antireflection film for ultraviolet rays. Using the resist pattern as a mask, the metal layer 3 and the main conductor layer 2 are simultaneously etched by a dry etching method to form a metal wiring.

Next, after removing the resist pattern, a silicon oxide film type insulating film such as NSG or BPSG is formed on the metal wiring by the CVD method, and the SOG is formed thereon.
After forming (spin-on-glass) on the entire surface, the surface is flattened by etching back or polishing the surface, and then a silicon oxide insulating film such as NSG or BPSG film is again formed by the CVD method. To form an interlayer insulating film 4 having a flattened surface. The film thickness of the interlayer insulating film 4 changes depending on the location due to the influence of the step difference in the lower layer.
A resist pattern 5 for forming a via hole is formed on the interlayer insulating film 4 by a photolithography method.

(B) Using the resist pattern 5 as a mask, the interlayer insulating film 4 is formed of a single gas containing carbon and fluorine, such as CF ₄ , C ₂ F ₆ , C ₃ F ₈ , CHF ₃ or C ₂ F _2. Dry etching is performed using gas or a mixed gas thereof as an etching gas. The dry etching progresses, and the metal layer 3 as an underlying layer is first exposed in a thin portion of the interlayer insulating film 4. In the hole 6-1 where the metal layer 3 is exposed, fluorine contained in the etching gas and the metal layer 3 react with each other to form a substance having a high vapor pressure, which is volatilized from the surface. Due to this surface reaction, the carbon-rich polymer 8-1 is deposited on the bottom of the hole, protecting the surface of the metal film 3 from ion bombardment during overetching and suppressing sputtering. On the other hand, in the thick portion of the interlayer insulating film, the hole 6-2 does not reach the lower metal layer 3.

(C) As the etching further progresses, the via hole 6-2 formed in the thick portion of the interlayer insulating film eventually reaches the lower metal layer 3 and the hole 6-.
Polymer 8-2 also begins to deposit on the bottom of 2. in the meantime,
Since the polymer 8-1 continues to be deposited in the over-etched hole 6-1, the thickness of the polymer is (polymer 8-1)> (polymer 8-2).
Further, during the over-etching, the main conductor layer 2 is protected by the polymers 8-1 and 8-2, so that the sputter of the main conductor layer 2 is continuously suppressed.

(D) Finally, the patterned resist 5 is removed by ashing with oxygen plasma. At this time, the polymers 8-1 and 8-2 which were formed at the bottoms of the holes 6-1 and 6-2 by the oxygen plasma and had the effect of suppressing the sputtering are also removed at the same time.

[0024]

【Example】

(Example 1) Example 1 is an example in which the metal layer 3 is tungsten. This will be described together with the manufacturing method with reference to FIG. (A) TEOS (tetraethyl orthosilicate; Tetra-Ethyl-Ortho-Sili) as a raw material on a substrate with a step
NSG film 1 by plasma CVD method using
Was deposited. The maximum film thickness of the NSG film 1 was 900 nm. Then, a Ti film 2a was formed to a thickness of 20 nm on the entire surface by a sputtering method using Ti as a target in a substrate temperature of 400 ° C., a pressure of 2.0 mTorr, and an Ar atmosphere. Subsequently, the substrate is transferred to another film forming chamber in a vacuum without being exposed to the atmosphere, and the substrate temperature is set to 40 by a sputtering method targeting AlSiCu (containing 1% of Si and 0.5% of Cu).
AlSiCu at 0 ° C, pressure of 2.0 mTorr and Ar atmosphere
The film 2b was deposited on the entire surface to a thickness of 600 nm. Further on,
The substrate is transported to another film forming chamber in a vacuum without being exposed to the atmosphere, and the Ti film 2c is formed on the entire surface in a substrate temperature of 400 ° C., a pressure of 2.0 mTorr, and an Ar atmosphere by a sputtering method using Ti as a target. The film was formed to a thickness of 20 nm. In this way, the conductor layer 2 composed mainly of aluminum was continuously formed to a thickness of 640 nm without exposure to the atmosphere.

Next, the substrate is transported in the air, and a mixed gas containing SiH ₄ , H ₂ and WF ₆ is used by a plasma CVD method at a pressure of 80 Torr and a substrate temperature of 450 ° C. to form a metal on the entire surface of the conductor layer 2. As the layer 3, a tungsten film was formed to a thickness of 50 nm. After that, a resist pattern is formed on the metal layer 3 by a photolithography method, and the metal layer 3 and the conductor layer 2 are mixed with BCl ₃ and Cl ₂ by a dry etching method using microwave and RF (high frequency). Using a pressure of 10 mTorr, substrate temperature of 40 ° C., RF power of 60
Simultaneously etched with W. Since the metal layer 3 and the conductor layer 2 can be simultaneously etched, reproducible etching was possible.

Next, an NSG film of 400 n is formed thereon by using the plasma CVD method using TEOS, SiH ₄ and O _2.
m is formed on the entire surface, SOG is formed on the entire surface, etch back is performed by dry etching, and then TEO is again formed by plasma CVD.
An NSG film having a thickness of 400 nm was formed over the entire surface using S, SiH _4, and O ₂ to form an interlayer insulating film 4 having good surface flatness. The thickness of the flattened interlayer insulating film 4 varies depending on the location due to the influence of the step difference in the base. As a result of measuring the film thickness, a difference of 2 times or more was observed at the maximum of 950 nm and the minimum of 400 nm. A resist pattern 5 for via holes having a diameter of 0.45 μm was formed thereon by a photolithography method.

(B) RI using the resist 5 as a mask
CHF ₃ gas or C ₂ F ₆ gas is used with E (reactive ion etching) method, pressure is 150 mTorr, and substrate temperature is 20.
Etching was performed at ° C. As a result of cross-sectional SEM observation of the sample in this state, a polymer was deposited at the bottom of the hole, and the polymer suppressed the sputtering of the lower metal layer 3. The thickness of the polymer 8-1 in the via hole 6-1 formed in the thin region of the interlayer insulating film is the same as that of the polymer 8-1 in the via hole 6-2 formed in the thick region of the interlayer insulating film.
It was found to be thicker than the thickness of 2.

(C) Next, as a result of subjecting this sample to resist ashing in oxygen plasma and performing cross-sectional SEM observation again, the polymers 8-1 and 8-2 at the bottom of the via hole were also removed together with the resist.

In the steps of FIGS. 2A to 2C, in order to evaluate the reliability of the wiring layer, the titanium layer is not provided as the conductor layer 2 on the lower layer or the upper layer, and the conductor layer 2 is formed. A sample including only the aluminum alloy layer 2b was also prepared. Figure 2
It processed like (A)-(C). In order to evaluate the reliability of the wiring layer, as a result of the usual electromigration evaluation, the sample in which the Ti layer was not formed on the lower surface or the upper surface of the conductor layer 2 had a remarkably short life. This result was not related to the presence or absence of the metal layer 3 on the conductor layer 2. It is considered that this is because the alloy layer of Ti and Al was not formed. On the other hand, when the Ti layer was laminated on either the lower surface or the upper surface of the aluminum alloy layer 2b, the wiring life was long.

(Comparative Example) For comparison, the result of performing the other steps in the same manner as in Example 1 without laminating the metal layer 3 will be described with reference to FIG. (A) The step of forming the metal layer 3 is omitted from the step of FIG. Since the metal layer 3 does not exist in the patterning for forming the metal wiring, only the conductor layer 2 centered on aluminum was etched and patterned.

(B) In the dry etching of the interlayer insulating film 4 for forming the via hole, the via hole 6-
No polymer was deposited on the bottoms of Nos. 1 and 6-2, and the sputtered products 7-1 and 7-2 of the lower layer metal were attached to the side walls of the holes.
Via hole 6-2 formed in a thick region of interlayer insulating film 4
The sputtered material 7-1 of the via hole 6-1 formed in the region where the interlayer insulating film was thinner than the sputtered material 7-2 of FIG.

(C) Even after the ashing process in oxygen plasma for removing the resist, the sputtered material 7-
1,7-2 still remained. Spatter 7-
1, 7-2 are interlayer insulating films 4 for forming via holes
The same occurs when a gas containing no fluorine is used as the dry etching gas, and it cannot be removed by ashing in oxygen plasma.

(Example 2) In Example 2, a molybdenum layer was used as the metal layer 3. Instead of forming the tungsten film as the metal layer 3 in Example 1, a molybdenum film was formed. The molybdenum film is formed by a sputtering method using molybdenum as a target, the substrate temperature is 450 ° C., the pressure is 2.0 mTorr,
A film having a thickness of 60 nm was formed on the conductor layer 2 in an Ar atmosphere. A via hole was formed in the other steps in the same manner as in Example 1, and the same results as in Example 1 were obtained.

(Example 3) In Example 2, a tantalum layer was used as the metal layer 3. Instead of forming the tungsten film as the metal layer 3 in Example 1, a tantalum film was formed.
The tantalum film was formed on the conductor layer 2 to a thickness of 50 nm by a sputtering method using tantalum as a target in a substrate temperature of 450 ° C., a pressure of 2.0 mTorr, and an Ar atmosphere. A via hole was formed in the other steps in the same manner as in Example 1, and the same results as in Example 1 were obtained.

[0035]

In the metal wiring of the present invention, a wiring having a low resistance can be realized by laminating a metal layer on a conductor layer mainly composed of an aluminum material layer made of aluminum or an aluminum alloy. it can. By stacking a titanium layer on at least one of the lower surface and the upper surface of the aluminum-based material layer, which is the main conductor layer, the reliability of the metal wiring can be improved. Since the fluoride of the metal layer is volatile, during the dry etching for forming the via hole, when the via hole in the place where the interlayer insulating film is thin is over-etched, the fluorine contained in the etching gas and the metal layer are When combined, fluoride is generated and volatilized, and the polymer is deposited on the bottom of the via hole. This polymer protects the surface of the metal layer, suppresses the main conductor layer from being sputtered at the time of over-etching, and has good reproducibility and enables low-damage etching. Since the polymer can be easily removed by oxygen plasma ashing at the time of removing the resist, there is no influence on the subsequent steps.

Since the metal layer can be processed at the same time as the main conductor layer thereunder in dry etching for forming metal wiring, reproducibility is ensured and process running cost is reduced even if the metal layer is provided. There is no disadvantage. Further, the metal layer also acts as an antireflection film for ultraviolet rays during exposure in the photolithography process, and also has an effect of preventing halation during resist patterning. In the step of forming the main conductor layer, at least one of before and after the formation of the aluminum-based material layer, when the titanium layer is continuously formed without being exposed to the atmosphere between the formation of the aluminum-based material layer, each layer is formed. Oxidation of the interface can be prevented, and an increase in wiring resistance can be suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an example showing a state in which a via hole is formed.

FIG. 2 is a process sectional view of an example of a manufacturing method showing a process of forming a via hole.

FIG. 3 is a process cross-sectional view showing a process of forming a via hole in a comparative example.

[Explanation of symbols]

 1,4 Interlayer insulating film 2 Conductor layers 2a, 2c Ti layer 2b Aluminum-based material layer 3 Fluoride volatile metal layer 6,6-1,6-2 Via hole 8-1,8-2 Polymer

Claims (6)

[Claims] 1. A metal wiring used in a semiconductor device, wherein an aluminum-based material layer made of aluminum or an aluminum alloy is a main conductor layer, and the fluoride is volatile in the uppermost layer of the conductor layer. A metal wiring of a semiconductor device, wherein a metal layer is laminated. 2. The metal wiring according to claim 1, wherein the material of the metal layer is a refractory metal of any one of tungsten, molybdenum and tantalum or a silicide thereof. 3. The metal wiring according to claim 1, wherein a titanium layer is laminated on at least one of a lower surface and an upper surface of the aluminum-based material layer in the main conductor layer. 4. A method of manufacturing a semiconductor device, comprising the step of forming a via hole on a metal wiring by including the following steps (A) to (E). (A) A step of forming a metal wiring in which an aluminum-based material layer made of aluminum or an aluminum alloy is used as a main conductor layer, and a metal layer whose fluoride is volatile is laminated on the uppermost layer of the conductor layer. , (B) a step of forming a silicon oxide film type interlayer insulating film on the metal wiring, (C) a resist film is formed on the interlayer insulating film, and the resist is formed so as to have an opening at a position where a via hole is formed. Patterning the film, (D) using the patterned resist film as a mask, dry etching the interlayer insulating film using an etching gas containing fluorine to form a via hole reaching the metal wiring. Step (E) an ashing step of removing the resist film and the polymer layer existing at the bottom of the formed via hole. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the material of the metal layer is a refractory metal of any one of tungsten, molybdenum, and tantalum or a silicide thereof. 6. In the step of forming the main conductor layer, titanium is continuously formed at least before and / or after the formation of the aluminum-based material layer and without being exposed to the atmosphere between the formation of the aluminum-based material layer. The method for manufacturing a semiconductor device according to claim 4, wherein a layer is formed.