JPH08314842A - Data transfer system - Google Patents

Abstract

PURPOSE: To provide a high-extendability data transfer system with which proper amount of data can be prefetched by previously recognizing the data transfer amount of an input/output instruction and the extension of an input/ output device is facilitated. CONSTITUTION: A channel controller 400, which receives the input/output instruction from a central processing unit 100, activates any one of plural use request buses 730 provided for every transfer data amount and requests the usage of an input/output bus 700. A use permitted bus 740 connects the channel controller 400 while using a daisy chain. A bus connector 300, to which the usage of bus is requested, judges the amount of data to look ahead from the result of arbitration between the transfer data amounts and looks ahead the data from a main memory 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system, and more particularly to a data transfer system capable of adding input / output devices.

[0002]

2. Description of the Related Art Conventionally, in this type of technique, the transfer performance between an input / output device and a main storage device is improved by pre-reading data from a main storage device. For example, in Japanese Patent Laid-Open No. 5-151138, a transfer performance table storing the transfer performance of each input / output device is provided, and by referring to this transfer performance table, prefetch suitable for the input / output device being transferred is provided. A technique for determining the amount of data and performing prefetching from the main storage device to the data buffer is described.
This conventional data transfer device divides the prefetch data buffer into unit areas, refers to the transfer performance table every time an input / output instruction is received, and allocates the necessary number of unit areas according to the transfer performance. Then, when the prefetch data buffer is full, a request suppression signal is output to the data transfer control circuit to limit the amount of prefetched data.

Further, for example, a PCI bus (Peripheral Com)
In a data transfer system employing a conventional input / output bus such as a ponent interconnect bus), the amount of transfer data cannot be accurately determined at the start of data transfer.
A fixed amount of data is fixedly read ahead ("OPEN DE
SIGN], No. 7, Volume 2, Issue 2, Pages 4 to 14
0 pages, published by CQ Publishing Co., Ltd.).

[0004]

In the above-mentioned prior art,
The amount of data to be prefetched is adjusted by limiting the amount of data buffer to be allocated in advance. Then, this allocation is determined based on the transfer performance of each input / output device. Therefore, the data transfer amount for each input / output command is not considered, and extra data may be prefetched depending on the actual data transfer amount.

On the other hand, if it is attempted to report the amount of data transfer from each channel connection device in advance, arbitration between channel control devices becomes complicated and a problem arises in expandability. That is, if it is attempted to separately provide a path for reporting the data amount from each channel control device, a signal line must be added every time the channel control device is added.

An object of the present invention is to realize a proper amount of data prefetch by previously recognizing the data transfer amount of an input / output command.

Another object of the present invention is to provide a data transfer system having a high expandability by facilitating the addition of an input / output device by easily reporting the data transfer amount of the input / output command. Is to do.

[0008]

In order to solve the above problems, a data transfer system according to the present invention requests the use of an input / output bus from a plurality of channel controllers to a bus connecting device via a use request bus. A data transfer processing system that permits use of the input / output bus via the use permission bus from the bus connection device to the plurality of channel control devices, wherein the use request bus corresponds to an amount of data to be transferred. The use permission bus comprises a plurality of signal lines corresponding to the amount of data to be transferred, and connects the plurality of channel control devices from the bus connection device in a chain.

Another data transfer system of the present invention comprises an input / output bus connecting a plurality of channel control devices and a bus connecting device, and a plurality of signal lines corresponding to the amount of data to be transferred. From the bus connection device to the plurality of signal lines corresponding to the amount of data to be transferred, and a usage request bus for requesting the bus connection device to use the input / output bus from the channel control device. A permission bus for permitting the use of the input / output bus from the bus connection device by connecting the control devices in a chain.

Another data transfer system of the present invention comprises a bus connecting device connected to a system bus connecting a central processing unit and a main memory, and a plurality of channel control devices each controlling a plurality of input / output devices. In a data transfer system having an input / output bus connecting the bus connection device and the plurality of channel control devices, the data transfer system includes a plurality of signal lines corresponding to the amount of data to be transferred. A bus requesting device for requesting the bus connection device to use the input / output bus, and a plurality of signal lines corresponding to the amount of data to be transferred. A permission bus for connecting and permitting the use of the input / output bus from the bus connection device.

In another data transfer system of the present invention, when the use request bus receives a request for the same signal line from at least one of the channel control devices,
Inform the bus connection device that a request has been made for the signal line.

In another data transfer system according to the present invention, the bus connection device selects one of the use request buses requested to use the input / output bus from the channel control device. Then, a permission signal is given to the corresponding signal line of the use permission bus.

In another data transfer system of the present invention, the bus connection device includes a data buffer for pre-reading data from the main storage.

[0014]

Next, an embodiment of the data transfer system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a data transfer system according to an embodiment of the present invention includes a central processing unit 100, a main memory 200, a bus connection device 300, a channel control device 400, and an input / output device 500. Have. The central processing unit 100 and the main memory 200 are connected to the system bus 600, and the channel control device 400 is connected to the input / output bus 70.
Connected to 0. The bus connection device 300 connects between the system 600 and the input / output bus 700. In addition, each channel control device 400 has an input / output device 5
00 is connected.

The central processing unit 100 is a device that performs processing such as various calculations, and has a role of issuing input / output instructions. The main memory 200 stores data to be executed and commands to be executed and input / output instructions. The main memory 200 is the central processing unit 100 or the bus connection unit 3.
In response to a memory access request from 00, data is sent out onto the system bus 600. The bus connection device 300
It is a device that connects the system bus 600 and the input / output bus 700. The channel control device 400 is a device that manages the subordinate input / output device 500. As the input / output device 500, for example, a disk device, a magnetic tape device, or the like is connected.

The system bus 600 includes an address line, a data line, and a control line, and is used for exchanging signals between the central processing unit 100, the main memory 200, and the bus connection device 300. The input / output bus 700 is composed of an address line, a data line and a control line, and has a main memory 200 and an input / output device 500.
And issuance of an input / output instruction from the central processing unit 100 to the channel control device 400.

The usage request bus 730 is used to request usage of the input / output bus 700 from the channel controller 400. A plurality of use request buses 730 are provided according to the amount of data to be transferred. In this embodiment, the use request bus 730 is composed of four signal lines, the first one is 4 bytes, the second is 16 bytes, the third is 32 bytes, and the fourth is 64 bytes. As a result, the channel control device 400 that intends to transfer, for example, 16-byte data activates the third use request bus 730. In addition, each signal from each channel control device 400 corresponds to the use request bus 73.
On the other hand, each of the channel controllers 400 to be connected receives a request or a request is sent to the bus connection device 300 because there is a wired OR operation for each data transfer.

The use permission bus 740 is connected to the bus connection device 30.
0 is used to allow the channel controller 400 to use the I / O bus 700. This use permission bus 74
0 connects each channel control device 400 by a daisy chain. Further, like the use request bus 730, a plurality of use permission buses 740 are provided according to the requested transfer data amount. In this embodiment, like the usage request bus 730, it is assumed that it comprises four signal lines.
The fourth means 4 bytes, the second means 16 bytes, the third means 32 bytes, and the fourth means 64 bytes. As a result, for example, when 16-byte data transfer is permitted, the third use permission bus 740 is activated, and the most upstream channel control device in the channel control device 400 that has issued the 16-byte use request. The device 400 will obtain the usage right.

The data request bus 710 is an input / output bus 70.
The channel control device 400 permitted to use 0 is used to transmit a data read request to the bus connection device 300. Since each signal from each channel control device 400 is wired-or on the data request bus 710, any one of the channel control devices 40 to be connected is connected.
If there is a request at 0, the fact is transmitted to the bus connection device 300.

The response bus 720 is used for informing the channel controller 400 from the bus connection device 300 of a signal indicating that valid data is output on the input / output bus 700.

Referring to FIG. 2, the bus connection device 300.
Is a data buffer 310 for storing pre-read data.
Data control circuit 3 for controlling data prefetching
20, an input / output bus arbitration circuit 330 that arbitrates an input / output bus use request from the channel controller 400, and an instruction control circuit 340 that controls the start and end of an input / output instruction.

The data buffer 310 is a buffer for storing the prefetched data from the main memory 200.

The input / output bus arbitration circuit 330 monitors the use request bus 730, and when the use of the input / output bus 700 is requested from the channel control device 400, arbitrates between the requests and performs an arbitration between the four transfer amounts. One of the use permission buses 740 is activated. The arbitration algorithm is
For example, it is possible to take measures such as giving priority to a transfer having a small transfer amount. Also, the input / output bus arbitration circuit 330
Transmits the amount of transfer data to be prefetched to the prefetch control circuit 320 via the signal line 335 as a result of the transfer amount arbitration.

The prefetch control circuit 320 outputs a memory read request from the main memory 200 to the system bus 600 according to the transfer data amount 335 from the input / output bus arbitration circuit 330. Further, the prefetch control circuit 320 uses the signal line 325 to capture the data on the signal line 301 read from the main memory 200.
Instruct 0. The prefetch control circuit 320 monitors a data request from the channel control device 400 via the data request bus 710. When a data request occurs, the signal line 325 is set to output data on the input / output bus 700.
To the data buffer 310. At the same timing as the data output, the prefetch control circuit 320 activates the response bus 720. In this way, the look-ahead control circuit 320 controls data transfer between the data buffer 310 and the channel control device permitted to use the input / output bus 700.

The instruction control circuit 340 is used by the central processing unit 10.
The input / output command is received from 0 and transmitted to each channel control device 400 via the input / output bus 700. Further, the instruction control circuit 340 receives the end report of the input / output instruction from the channel control device 400 and interrupts the central processing unit.

Referring to FIG. 4, the input / output instruction is an instruction,
It contains the I / O device number, transfer start address, and transfer data amount. The instruction represents a type such as reading or writing of data. The I / O device number represents a number for identifying an I / O device to be accessed. The transfer start address indicates an address on the first input / output device related to the transfer. The transfer data amount indicates the amount of data related to the transfer.

Referring to FIG. 1, the channel controller 40
0 is according to the input / output command from the central processing unit 100,
This is a device that controls data transfer between the input / output device 500 and the main storage device 200 that are connected under the device. When performing data transfer, the central processing unit 100 can specify, for example, several hundred bytes to several kilobytes. However, as described above, the transfer unit that the input / output device 500 can specify in one transfer is 4 bytes to 64 bytes. Must be specified. Therefore, when the amount of data specified by the central processing unit 100 exceeds the amount of transfer data specified by the input / output command, the data is divided and transferred several times. In this case, since a bus use request is transmitted for each transfer, another access can be entered between the transfers. However, from 4 bytes specified as the transfer unit to 6 bytes
In the middle of 4 bytes, even if a plurality of clocks are required, other accesses cannot be entered until the transfer is completed.

Referring to FIG. 3, each channel controller 4
00 is a channel control circuit 410 and a data control circuit 4
20. The channel control circuit 410 decodes the input / output instruction from the central processing unit 100, and the instruction is the input / output apparatus 500 under the control of the channel control apparatus 400.
Use request bus 730
The signal line corresponding to the amount of data transferred is activated.
Further, the channel control circuit 410 transmits the input / output device number designated by the input / output instruction to the data control circuit 420 via the signal line 441, and the transfer data amount designated by the input / output instruction via the signal line 442. 420
Tell.

The data control circuit 420 has a register for holding the input / output device number and a counter for storing and counting the amount of transfer data. When the use of the I / O bus 700 is permitted, the main memory 20 is used to transfer data between the I / O device held in the register and the bus connection device 300.
The address to 0 is output to the input / output bus 700 and the data request bus 710 is activated. When the bus control device 300 activates the response bus 720, the data on the input / output bus 700 is output to a predetermined input / output device 500. The transfer data amount set in the counter is decremented each time transfer is performed. When the value indicated by the counter becomes 0, the end of the transfer is notified to the bus connection device 3.
Report to 00.

Next, the operation of the above embodiment will be described with reference to the drawings.

Referring to FIGS. 1 and 5, first, when the central processing unit 100 issues an input / output instruction on the system bus 600 (step 901), the instruction control circuit 340 in the bus control unit 300 switches the input / output bus 700 to the input / output bus 700. The channel is transmitted to the channel control circuit 410 in the channel control device 400 via The channel control circuit 410 decodes the input / output command, and sets the input / output device number and the transfer data amount to the data control circuit 420 using the signal lines 441 and 442 (step 902). If the input / output command from the central processing unit 100 is a transfer command to the subordinate input / output device 500, the channel control circuit 410 activates the use request bus 730 to request the use of the input / output bus 700 ( Step 903).

The input / output bus arbitration circuit 330 arbitrates between data transfer amounts in response to the input / output bus use request from the channel control circuit 410 on the use request bus 730 (step 904), and the result is signal line 335. Is transmitted to the prefetch control circuit 320. The prefetch control circuit 320 holds this transfer data amount. Further, the input / output bus arbitration circuit 330 activates one signal line of the use permission bus 740 according to the arbitration result.

The use permission bus 740 connects each channel control device 400 by a daisy chain. As a result, of the channel control devices 400 that have issued the usage request for the transfer data amount, the one with the highest priority acquires the usage right of the input / output bus 700.

The data control circuit 420 in the channel control device 400 that has acquired the right to use the input / output bus 700 outputs an address to the main memory 200 to the input / output bus 700 and activates the data request bus 710 to transmit data. (Step 905). The address to the main memory is transmitted from the data buffer 310 to the prefetch control circuit 320 via the signal line 326.

In response, the look-ahead control circuit 320
Reads data from the main memory 200 in accordance with the held transfer data amount and the address received via the signal line 326 (step 912). Then, the data control circuit 320 uses the signal line 325 to instruct the data buffer 310 to fetch the data on the system bus 600 (step 913).

When the data is stored in the data buffer 301, the prefetch data control circuit 320 instructs the data buffer 310 to output the data on the input / output bus 700 using the signal line 325 (step 90).
6). Then, in accordance with this data output, the prefetch data control circuit 320 activates the response bus 720.

Recognizing that the response bus 720 has become active, the data control circuit 420 in the channel control device 400 transfers the data on the input / output bus 700 to the set input / output device 500 (step 907). ).
Then, the amount of transferred data is subtracted from the amount of transferred data set in the data control circuit 420 to set the remaining amount of transferred data. As a result, if the transfer of all data has been completed, the transfer processing ends (step 9).
08). In this case, the data control circuit 420 reports the transfer end to the instruction control circuit 340 in the bus connection device 300. In response, the instruction control circuit 340 interrupts the central processing unit 100 to notify the end of the transfer.

On the other hand, if there is untransferred data, the data control circuit 420 activates the use request bus 730 again and requests the use of the input / output bus 700 (step 9).
03).

As described above, according to the data transfer system of one embodiment of the present invention, the use request buses 730 are provided in correspondence with the transfer data amount and are configured to be wired-ORed, respectively. Since the 740 is configured by a daisy chain, the channel control device 40
It is not necessary to perform arbitration between 0 in particular, and it is possible to easily prefetch an appropriate amount of data for the data buffer 310. Further, the expansion of the input / output device 500 is facilitated, and a highly scalable data transfer system can be provided.

[0041]

As is apparent from the above description, according to the present invention, it becomes easy to recognize in advance the data transfer amount of the input / output command, and it is possible to prefetch an appropriate amount of data. Further, it becomes easy to add an input / output device, and it is possible to provide a highly expandable data transfer system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data transfer system of the present invention.

FIG. 2 is a diagram showing a configuration of a bus connection device in the data transfer system according to one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a channel control device in the data transfer system according to one embodiment of the present invention.

FIG. 4 is a diagram showing an input / output instruction format in the data transfer system according to one embodiment of the present invention.

FIG. 5 is a diagram showing an operation of the data transfer system according to the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 central processing unit 200 main memory 300 bus connection device 400 channel control device 500 input / output device 600 system bus 700 input / output bus 710 data request bus 720 response bus 730 use request bus 740 use permission bus

Claims (6)

[Claims] 1. A plurality of channel controllers request use of an input / output bus from a bus connecting device via a use request bus, and the bus connecting device sends a use permission bus to the plurality of channel controllers. In the data transfer processing system for permitting the use of the input / output bus via the use request bus, the use request bus comprises a plurality of signal lines corresponding to the amount of data to be transferred, and the use permit bus is the amount of data to be transferred. A data transfer system comprising a plurality of signal lines corresponding to, and connecting the plurality of channel control devices in a chain from the bus connection device. 2. An input / output bus connecting a plurality of channel control devices and a bus connection device, and a plurality of signal lines corresponding to the amount of data to be transferred, from the plurality of channel control devices to the bus connection device. The use request bus for requesting use of the input / output bus, and a plurality of signal lines corresponding to the amount of data to be transferred. A data transfer system comprising: a use permission bus for permitting the use of the input / output bus from a bus connection device. 3. A bus connecting device connected to a system bus connecting a central processing unit and a main memory, a plurality of channel control devices each controlling a plurality of input / output devices, the bus connecting device and the plurality of channels. In a data transfer system having an input / output bus for connecting to a control device, use of the input / output bus from the plurality of channel control devices to the bus connection device, which is composed of a plurality of signal lines corresponding to the data amount to be transferred And a plurality of signal lines corresponding to the amount of data to be transferred, and the plurality of channel control devices are connected in a chain from the bus connection device to the input device from the bus connection device. A data transfer system comprising: a use permission bus for permitting use of an output bus. 4. The use request bus, when receiving a request from at least one of the channel control devices for the same signal line, notifies the bus connection device of the request for the signal line. Item 3. The data transfer device according to Item 3. 5. The bus connection device selects any one of the use request buses requested to use the input / output bus from the channel control device and responds to the use permission bus. The data transfer system according to claim 4, wherein a permission signal is applied to the signal line. 6. The data transfer system according to claim 5, wherein said bus connection device includes a data buffer for pre-reading data from said main memory.