JPH08321543A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH08321543A JPH08321543A JP12666095A JP12666095A JPH08321543A JP H08321543 A JPH08321543 A JP H08321543A JP 12666095 A JP12666095 A JP 12666095A JP 12666095 A JP12666095 A JP 12666095A JP H08321543 A JPH08321543 A JP H08321543A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- polyimide
- semiconductor device
- wiring layer
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004642 Polyimide Substances 0.000 claims abstract description 54
- 229920001721 polyimide Polymers 0.000 claims abstract description 54
- 239000010410 layer Substances 0.000 claims abstract description 45
- 238000000576 coating method Methods 0.000 claims abstract description 34
- 239000011248 coating agent Substances 0.000 claims abstract description 33
- 239000002904 solvent Substances 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000007788 liquid Substances 0.000 claims description 32
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 239000010408 film Substances 0.000 description 65
- 230000000694 effects Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229920005575 poly(amic acid) Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006482 condensation reaction Methods 0.000 description 1
- 230000018044 dehydration Effects 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ポリイミド系絶縁膜で
層間絶縁とファイナルパッシベーションを行った半導体
装置の、配線層の微細化に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to miniaturization of wiring layers in a semiconductor device in which interlayer insulation and final passivation are performed with a polyimide-based insulation film.
【０００２】[0002]
【従来の技術】ポリイミド系絶縁膜は、保護膜を安価に
形成できることから、半導体装置の分野、特に多層配線
の層間絶縁膜として広く使われており、ウェハ上にポリ
イミド原液をスピンオン塗布し、これを焼成することに
よって得ることができる。一方、近年の集積回路は、更
なる高集積化、高密度化により、配線層の線幅および配
線層間の距離が狭められ、その値がサブミクロン（１．
０μ以下）の設計ルールが実用化されている。2. Description of the Related Art A polyimide-based insulating film is widely used in the field of semiconductor devices, especially as an interlayer insulating film for multi-layer wiring because a protective film can be formed at low cost. Can be obtained by firing. On the other hand, in recent integrated circuits, the line width of the wiring layers and the distance between the wiring layers are narrowed due to higher integration and higher density, and the values are submicron (1.
The design rule of 0 μ or less) has been put to practical use.
【０００３】また、配線層間の距離が２．０μ程度のも
のでも、本願出願人において出願された特開平０２ー１
０９１０２号に記載したように、第１層目配線層の上を
シリコン窒化膜で被覆したものでは、配線層間の間隔が
シリコン窒化膜の膜厚の分だけ狭まるので、上記サブミ
クロンルールの間隔と同様、極めて狭いものになる。図
３は前記特開平０２ー１０９１０２号に記載されている
Ｂｉ−ＣＭＯＳ集積回路を示す断面図である。同図には
Ｐ型半導体基板１上のＮ型エピタキシャル層に集積化し
たＮＰＮトランジスタ２とＮチャンネル型ＭＯＳＦＥＴ
３が示されており、４はＰ＋型分離領域、５はＮ＋型埋
め込み層、６はＰ型ベース領域、７はＮ＋型エミッタ領
域、８はＰ＋型埋め込み層、９はＰ型ウェル領域、１０
はＮ＋型ソース・ドレイン領域、１１はゲート電極、１
２は第１層目の配線層、１３はシリコン窒化膜、１４は
ポリイミド絶縁膜、１５は第２層目の配線層、１６は最
終パッシベーションとしてのポリイミド絶縁膜である。Further, even if the distance between the wiring layers is about 2.0 μ, Japanese Patent Application Laid-Open No. 02-1 filed by the applicant of the present application.
As described in No. 09102, in the case where the first wiring layer is covered with the silicon nitride film, the distance between the wiring layers is narrowed by the film thickness of the silicon nitride film. Similarly, it will be extremely narrow. FIG. 3 is a sectional view showing a Bi-CMOS integrated circuit described in the above-mentioned Japanese Patent Laid-Open No. 02-109102. The figure shows an NPN transistor 2 and an N-channel MOSFET integrated in an N-type epitaxial layer on a P-type semiconductor substrate 1.
3 is shown, 4 is a P + type isolation region, 5 is an N + type buried layer, 6 is a P type base region, 7 is an N + type emitter region, 8 is a P + type buried layer, 9 is a P type well region, 10
Is an N + type source / drain region, 11 is a gate electrode, 1
Reference numeral 2 is a first wiring layer, 13 is a silicon nitride film, 14 is a polyimide insulating film, 15 is a second wiring layer, and 16 is a polyimide insulating film as a final passivation.
【０００４】前記シリコン窒化膜１３は、ポリイミド絶
縁膜１４、１６のパッシベーション効果に加えて更に強
固なパッシベーション効果を得る目的で設けたものであ
る。シリコン窒化膜１３を第１層目配線層１２の上に配
置することにより、これをポリイミド絶縁膜１４の上に
配置した場合のポリイミドが発生するガスによる膨れ不
良と製造の困難さを防止し、第１層目配線層１２の下に
配置した場合のコンタクトホール形成時のエッチングの
困難さを回避している。これにより、シリコン窒化膜１
３のパッシベーション効果を得ると共に、ポリイミド絶
縁膜を層間絶縁膜に用いたことに依る表面平坦化の効果
を同時に得ることができる かかる装置においては、図４に示すように、第１層目配
線層１２と第１層目配線層１２との間隔が２．０μ程度
であっても、膜厚０．６μ程度のシリコン窒化膜１３を
形成することにより両者の間隔（図示Ｘ）は０．８μ程
度となり、サブミクロンルールのものと同様、１．０μ
以下の狭い空間が発生することになる。The silicon nitride film 13 is provided for the purpose of obtaining a stronger passivation effect in addition to the passivation effect of the polyimide insulating films 14 and 16. By disposing the silicon nitride film 13 on the first wiring layer 12, it is possible to prevent swelling defects and manufacturing difficulty due to the gas generated by polyimide when the silicon nitride film 13 is arranged on the polyimide insulating film 14. The difficulty of etching at the time of forming a contact hole when the wiring layer is arranged below the first wiring layer 12 is avoided. As a result, the silicon nitride film 1
In addition to obtaining the passivation effect of No. 3 and the effect of planarizing the surface due to the use of the polyimide insulating film as the interlayer insulating film at the same time, in such a device, as shown in FIG. Even if the distance between the first wiring layer 12 and the first wiring layer 12 is about 2.0 μ, the distance (X) between them is about 0.8 μ by forming the silicon nitride film 13 having a thickness of about 0.6 μ. Is the same as the submicron rule, 1.0μ
The following narrow spaces will occur.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、ポリイ
ミド絶縁膜は、先ずポリイミド塗布液をウェハ上にスピ
ンオフ法により塗布し、３００乃至４００℃の熱処理を
加えることによって形成するものであるが、前記ポリイ
ミド塗布液が比較的粘性の高い（１０Ｐｏｉｓｅ程度）
液体であるため、上記のような狭い空間があるとその空
間全てを充満することが困難になり、図４に示すように
狭い空間内に気泡１７を生じてしまうことが明らかにな
った。この様な気泡１７が生じると、後工程での熱処理
により気泡１７内部の空気が膨張して、外観不良や配線
の断線不良を多発するという欠点を有していた。However, the polyimide insulating film is formed by first applying a polyimide coating solution on a wafer by a spin-off method and then applying a heat treatment at 300 to 400 ° C. Liquid is relatively viscous (about 10 Poise)
Since it is a liquid, it becomes difficult to fill the entire space if there is such a narrow space, and it becomes clear that bubbles 17 are generated in the narrow space as shown in FIG. When such bubbles 17 are generated, the air inside the bubbles 17 expands due to the heat treatment in the subsequent process, and there is a drawback that appearance defects and wiring disconnection defects frequently occur.
【０００６】また、比較的粘性の低いオリイミド塗布液
を用いることで解決することも可能ではあるが、自ずと
限度があるし、層間絶縁膜として必要になるほどの厚い
膜厚を得ることが困難になる。Although it is possible to solve the problem by using an oriimide coating solution having a relatively low viscosity, there is a limit naturally, and it becomes difficult to obtain a film thickness as thick as an interlayer insulating film. .
【０００７】[0007]
【課題を解決するための手段】本発明は上記従来の欠点
に鑑みなされたもので、ポリイミド塗布液を塗布する前
工程として、粘性の低いポリイミド塗布液の主溶媒のみ
をウェハ上に塗布し、次いでポリイミド塗布液を塗布す
ることにより、気泡を生じることのない層間絶縁膜の製
造方法を提供するものである。Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks. As a pre-process of applying a polyimide coating liquid, only a main solvent of a low-viscosity polyimide coating liquid is applied onto a wafer, Then, a polyimide coating solution is applied to provide a method for producing an interlayer insulating film that does not generate bubbles.
【０００８】[0008]
【作用】本発明によれば、主溶媒自体の粘性は低いの
で、濡れ性が高く狭い空間内部にも容易に塗布すること
ができる。そして、ポリイミド塗布液は主溶媒を含むも
のであるから、塗布時の接触角核が下がり、主溶媒を介
して狭い空間内部にもポリイミド塗布液を充満させるこ
とができる。According to the present invention, since the viscosity of the main solvent itself is low, it has high wettability and can be easily applied even in a narrow space. Since the polyimide coating liquid contains the main solvent, the contact angle nucleus during coating is lowered, and the polyimide coating liquid can be filled in the narrow space through the main solvent.
【０００９】[0009]
【実 施 例】以下に本発明の一実施例を図１と図２を参
照しながら、工程順に詳細に説明する。 （１）ＢＩＰ素子、ＭＯＳ素子等を形成した集積回路基
板を形成する。集積回路は、ＢＩＰ型、ＭＯＳ型、ある
いは図３に示したようなＢｉ−ＣＭＯＳ型がある。各素
子は、イオン注入や熱拡散など、周知の手法により形成
される。[Embodiment] An embodiment of the present invention will be described in detail below in the order of steps with reference to FIGS. 1 and 2. (1) An integrated circuit substrate having a BIP element, a MOS element, etc. is formed. The integrated circuit is of a BIP type, a MOS type, or a Bi-CMOS type as shown in FIG. Each element is formed by a known method such as ion implantation or thermal diffusion.
【００１０】（２）図１Ａを参照して、基板を被覆する
シリコン酸化膜２０の上に、膜厚０．８〜１．２μのア
ルミニウムまたはアルミニウム・シリコンを蒸着あるい
はスパッタ法により被着せしめ、これをＲＩＥ等の手法
でパターニングすることにより第１層目の配線層２１を
形成する。シリコン酸化膜２０の所望の領域にはコンタ
クトホールが設けられ、第１層目の配線層２１は前記コ
ンタクトホールを介して上記回路素子を形成する拡散領
域とコンタクトし、シリコン酸化膜２０の上を延在して
各回路素子の電気的接続を行う。この実施例では、第１
の配線層２１の線幅を２．０μ、第１の配線層２１と第
１の配線層２１との間隔（最小設計ルール）を２．０μ
とする。第１の配線層２１の側壁はほぼ垂直である。(2) Referring to FIG. 1A, aluminum or aluminum-silicon having a film thickness of 0.8 to 1.2 μ is deposited on the silicon oxide film 20 covering the substrate by vapor deposition or sputtering, By patterning this by a method such as RIE, the first wiring layer 21 is formed. A contact hole is provided in a desired region of the silicon oxide film 20, and the first wiring layer 21 makes contact with the diffusion region forming the circuit element through the contact hole, and the silicon oxide film 20 is covered with the contact hole. It extends and electrically connects each circuit element. In this embodiment, the first
The wiring width of the wiring layer 21 is 2.0 μ, and the distance between the first wiring layer 21 and the first wiring layer 21 (minimum design rule) is 2.0 μ.
And The side wall of the first wiring layer 21 is almost vertical.
【００１１】（２）図１Ｂを参照して、全面に膜厚０．
５〜０．７μのシリコン窒化膜２２を形成する。融点の
低いアルミを形成した後であるので、シリコン窒化膜２
２は低温形成が可能なプラズマＣＶＤ法によって形成す
る。シリコン窒化膜２２はステップカバレイジがそれ程
高くないので、第１の配線層２１の側壁には図示するよ
うに若干オーバーハングした状態で被着される。また、
シリコン窒化膜２２の膜厚の２倍の分だけ、第１の配線
層２２間の距離（図示Ｘ）が狭まり、ここに幅狭の空間
を形成することになる。この例では、シリコン窒化膜の
膜厚を０．６μとすれば、間隔Ｘは０．８μとなる。深
さは０．８〜１．２μである。(2) Referring to FIG. 1B, a film thickness of 0.
A silicon nitride film 22 of 5 to 0.7 μm is formed. Since the aluminum having a low melting point is formed, the silicon nitride film 2
2 is formed by the plasma CVD method which can be formed at a low temperature. Since the step coverage of the silicon nitride film 22 is not so high, the silicon nitride film 22 is deposited on the side wall of the first wiring layer 21 in a slightly overhung state as shown in the drawing. Also,
The distance (X in the figure) between the first wiring layers 22 is reduced by twice the thickness of the silicon nitride film 22, and a narrow space is formed here. In this example, if the thickness of the silicon nitride film is 0.6 μ, the interval X is 0.8 μ. The depth is 0.8 to 1.2μ.
【００１２】（３）図１Ｃを参照して、シリコン窒化膜
２２の表面に、ポリイミド塗布液の主溶媒２３を塗布す
る。ポリイミド塗布液は、主溶媒としのＮＭＰ（Ｎ・メ
チル・ピロリドン）に高分子ポリマーであるポリアミド
酸を５０重量％以上含む溶液であるので、主溶媒２３と
してはポリアミド酸を含まない純粋な前記ＮＭＰ液を使
用する。ＮＭＰ液自体は粘性が極めて低く、水と同程度
のさらっとした液体であるから、シリコン窒化膜２２の
表面には極めて薄い膜厚で、表面が濡れる程度の状態で
塗布される。(3) Referring to FIG. 1C, the main solvent 23 of the polyimide coating liquid is applied to the surface of the silicon nitride film 22. Since the polyimide coating solution is a solution containing 50% by weight or more of polyamic acid, which is a high-molecular polymer, in NMP (N.methylpyrrolidone) as the main solvent, the pure NMP containing no polyamic acid as the main solvent 23 is used. Use liquid. Since the NMP liquid itself has an extremely low viscosity and is a liquid that is as dry as water, it is applied to the surface of the silicon nitride film 22 with an extremely thin film thickness in such a condition that the surface is wet.
【００１３】（４）図２を参照して、シリコン窒化膜２
２の表面が主溶媒２３液で濡れている状態で、表面にポ
リイミド塗布液を塗布する。ポリイミド塗布液自体の粘
性は高いものの、シリコン窒化膜２２表面が主溶媒２３
液で濡れているので、主溶媒２３液の作用により、極め
て狭い空間である第１の配線層２１間の空間も確実にポ
リイミド塗布液で充満できる。(4) Referring to FIG. 2, silicon nitride film 2
While the surface of No. 2 is wet with the main solvent 23 liquid, the polyimide coating liquid is applied to the surface. Although the polyimide coating solution itself has a high viscosity, the surface of the silicon nitride film 22 is the main solvent 23.
Since it is wet with the liquid, the space between the first wiring layers 21, which is an extremely narrow space, can be surely filled with the polyimide coating liquid by the action of the main solvent 23 liquid.
【００１４】そして、ウェハ全体に３００乃至４００
℃、数十分の熱処理を与えることにより、ポリイミド塗
布液中のポリアミド酸を脱水縮合反応させてイミド結合
させることにより、膜厚１．５〜３．０μのポリイミド
絶縁膜２４を形成する。上記主溶媒の塗布とポリイミド
塗布液の塗布はスピンオン塗布法により行う。例えばス
ピンオン塗布装置に主溶媒２３用の第１のノズルとポリ
イミド塗布液用の第２のノズルとの２種類のノズルを用
意し、先ず第１のノズルから主溶媒２３液をウェハ上に
供給し、ウェハを回転させてスピンオン塗布し、次いで
回転を止めた後第２のノズルからポリイミド塗布液を供
給し、ウェハを再度回転させてスピンオン塗布する。こ
の様に２種類のノズルを用意すれば、主溶媒２３液の塗
布とポリイミド塗布液の塗布との間に時間的な空きがな
いので、特に製造工程を煩雑にすることがなく、主溶媒
２３液が乾燥するというような不都合も回避できる。も
ちろん、主溶媒２３液を入れた槽にウェハを浸漬するよ
うな手法でもかまわない。Then, 300 to 400 is applied to the entire wafer.
By subjecting the polyamic acid in the polyimide coating solution to a dehydration condensation reaction to form an imide bond by heat treatment at a temperature of several tens of minutes, a polyimide insulating film 24 having a thickness of 1.5 to 3.0 μm is formed. The application of the main solvent and the application of the polyimide coating solution are performed by the spin-on coating method. For example, a spin-on coating apparatus is provided with two types of nozzles, a first nozzle for the main solvent 23 and a second nozzle for the polyimide coating liquid. First, the main solvent 23 liquid is supplied onto the wafer from the first nozzle. Then, the wafer is rotated for spin-on coating, then the rotation is stopped, and then the polyimide coating solution is supplied from the second nozzle, and the wafer is rotated again for spin-on coating. If two types of nozzles are prepared in this manner, there is no time gap between the application of the main solvent 23 liquid and the application of the polyimide coating liquid, so that the main solvent 23 is not particularly complicated. The inconvenience that the liquid dries can be avoided. Of course, a method of immersing the wafer in a bath containing the main solvent solution 23 may be used.
【００１５】このポリイミド絶縁膜２４上に多層配線層
を形成する場合は、図４と同様に、先ずポリイミド絶縁
膜２４に層間接続用のスルーホールを形成し、アルミ材
料の堆積とパターニングにより第２層目の配線層を形成
し、その上に再度ポリイミド絶縁膜（線間が狭くないの
で、主溶媒による前処理は不要である）を形成してパッ
シベーション皮膜とする。層間絶縁膜としてのポリイミ
ド絶縁膜２４より上の絶縁膜は、最終パッシベーション
皮膜までを全てポリイミド系の絶縁膜とする。これで、
有機系絶縁膜（ポリイミド絶縁膜）の上に無機系絶縁膜
（シリコン酸化膜など）を形成することの、製造の困難
さを回避する。In the case of forming a multi-layer wiring layer on the polyimide insulating film 24, first, through holes for interlayer connection are first formed in the polyimide insulating film 24 as in FIG. A wiring layer of a layer is formed, and a polyimide insulating film (pre-treatment with a main solvent is not necessary because the distance between lines is not narrow) is formed thereon again to form a passivation film. The insulating film above the polyimide insulating film 24 serving as an interlayer insulating film is a polyimide insulating film up to the final passivation film. with this,
Avoid the manufacturing difficulty of forming an inorganic insulating film (such as a silicon oxide film) on an organic insulating film (polyimide insulating film).
【００１６】以上に説明した本発明に依れば、配線層間
に狭い空間を形成する装置においても、主溶媒２３液の
前処理を行うことによってポリイミド絶縁膜２４の気泡
を防止することができるものである。尚、上記実施例は
配線の上にシリコン窒化膜２２を形成した結果、狭い空
間が生じたものであるが、シリコン窒化膜２２を具備せ
ず、例えば配線層２１と配線層２１との間隔が１．０μ
以下のサブミクロンルールの半導体装置においても有用
な技術である。この場合は、第１の配線層２１形成後、
主溶媒２３液の前処理とポリイミド絶縁膜２４の形成を
行うので、主溶媒２３液はアルミ表面を被覆することに
なる。According to the present invention described above, even in a device for forming a narrow space between wiring layers, it is possible to prevent bubbles in the polyimide insulating film 24 by pretreatment with the main solvent 23 liquid. Is. It should be noted that in the above-mentioned embodiment, a narrow space is generated as a result of forming the silicon nitride film 22 on the wiring, but the silicon nitride film 22 is not provided, and for example, the distance between the wiring layers 21 and 21 is 1.0μ
This technique is also useful in the following semiconductor devices of the submicron rule. In this case, after forming the first wiring layer 21,
Since the pretreatment of the main solvent 23 liquid and the formation of the polyimide insulating film 24 are performed, the main solvent 23 liquid covers the aluminum surface.
【００１７】[0017]
【発明の効果】以上に説明したとおり、本発明に依れ
ば、配線層間に極めて狭い空間を形成する装置において
も、主溶媒２３液の前処理によってポリイミド絶縁膜２
４の気泡を防止し、前記狭い空間をポリイミド絶縁膜２
４で充満することが可能な半導体装置の製造方法を提供
するものである。これにより、気泡内部の空気が膨張す
ることに起因する、膨れ不良等を防止でき、半導体装置
の歩留まり向上に寄与できるものである。As described above, according to the present invention, even in a device for forming an extremely narrow space between wiring layers, the polyimide insulating film 2 is pretreated by the pretreatment of the main solvent 23 liquid.
4 air bubbles are prevented, and the narrow space is filled with the polyimide insulating film 2
The present invention provides a method for manufacturing a semiconductor device that can be filled with the method described in item 4. As a result, it is possible to prevent a swollen defect and the like due to the expansion of the air inside the bubbles, which can contribute to the improvement of the yield of the semiconductor device.
【００１８】さらに、本発明によりポリイミド絶縁膜２
４を用いつつ配線層間の微細化を更に押し進めることが
できる。従って、ＢＩ−ＣＭＯＳのような、ポリイミド
絶縁膜だけではブロッキング効果が不足するＭＯＳ素子
を具備した半導体装置においても、シリコン窒化膜で補
強することにより、ＣＶＤ絶縁膜やＳＯＧなどの完全無
機絶縁膜を用いるまでもなくポリイミド絶縁膜により安
価に製造できるという利点を持つものである。Further, according to the present invention, the polyimide insulating film 2
4 can be used to further promote miniaturization between wiring layers. Therefore, even in a semiconductor device including a MOS element such as BI-CMOS which is insufficient in blocking effect only with a polyimide insulating film, a completely inorganic insulating film such as a CVD insulating film or SOG can be formed by reinforcing it with a silicon nitride film. It has the advantage that it can be manufactured inexpensively by using a polyimide insulating film without using it.
【００１９】さらに、粘性の低い溶液を用いる手法に比
べて、絶縁膜の膜厚を大にできるという効果をも有する
ものである。Further, it has an effect that the thickness of the insulating film can be increased as compared with the method using a solution having a low viscosity.
【図１】本発明の製造方法を説明する断面図である。FIG. 1 is a cross-sectional view illustrating a manufacturing method of the present invention.
【図２】本発明の製造方法を説明する断面図である。FIG. 2 is a cross-sectional view illustrating the manufacturing method of the present invention.
【図３】従来例を説明する断面図である。FIG. 3 is a sectional view illustrating a conventional example.
【図４】従来例を説明する断面図である。FIG. 4 is a sectional view illustrating a conventional example.
Claims (6)
パターニングして配線層を形成する工程と、 前記配線層および前記絶縁膜の上にポリイミド塗布液を
塗布し、これを焼成してポリイミド絶縁膜を形成する工
程を具備する半導体装置の製造方法において、 前記ポリイミド塗布液の塗布前に、前記ポリイミド塗布
液の主溶媒液で前処理を行う工程を具備することを特徴
とする半導体装置の製造方法。1. A step of forming an electrode material on an insulating film and patterning the electrode material to form a wiring layer; and a step of applying a polyimide coating liquid on the wiring layer and the insulating film and baking the same. In a method for manufacturing a semiconductor device, which comprises a step of forming a polyimide insulating film by using a semiconductor device, the method includes a step of performing a pretreatment with a main solvent liquid of the polyimide coating liquid before the coating of the polyimide coating liquid. Device manufacturing method.
クロン以下であることを特徴とする請求項１記載の半導
体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the distance between the adjacent wiring layers is 1.0 micron or less.
パターニングして配線層を形成する工程と、 前記電極配線層の表面および前記絶縁膜の表面を被覆す
るシリコン窒化膜を形成する工程と、 前記シリコン窒化膜の表面にポリイミド塗布液を塗布
し、これを焼成してポリイミド絶縁膜を形成する工程と
を具備する半導体装置の製造方法において、 前記ポリイミド塗布液の塗布前に、前記ポリイミド塗布
液の主溶媒液で前処理を行う工程を具備することを特徴
とする半導体装置の製造方法。3. A step of forming an electrode material on an insulating film and patterning the same to form a wiring layer, and forming a silicon nitride film covering the surface of the electrode wiring layer and the surface of the insulating film. In a method for manufacturing a semiconductor device, which comprises a step, a step of applying a polyimide coating solution to the surface of the silicon nitride film, and forming a polyimide insulating film by baking the same, before applying the polyimide coating solution, A method of manufacturing a semiconductor device, comprising a step of performing a pretreatment with a main solvent liquid of a polyimide coating liquid.
窒化膜とシリコン窒化膜との間隔が１．０ミクロン以下
であることを特徴とする請求項３記載の半導体装置の製
造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein the distance between the silicon nitride film and the silicon nitride film between adjacent wiring layers is 1.0 micron or less.
ヌ・メチル・ピロリドンであることを特徴とする請求項
１または請求項３記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the main solvent liquid of the polysilicon coating liquid is N-methylpyrrolidone.
前記ポリイミド絶縁膜は層間絶縁膜であり、且つ、層間
絶縁膜からファイナルパッシベーション膜までの全ての
絶縁膜をポリイミド系の絶縁膜で構成することを特徴と
する請求項３記載の半導体装置の製造方法。6. The wiring layer is a first wiring layer,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the polyimide insulating film is an interlayer insulating film, and all the insulating films from the interlayer insulating film to the final passivation film are made of a polyimide insulating film. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12666095A JPH08321543A (en) | 1995-05-25 | 1995-05-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12666095A JPH08321543A (en) | 1995-05-25 | 1995-05-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08321543A true JPH08321543A (en) | 1996-12-03 |
Family
ID=14940722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12666095A Pending JPH08321543A (en) | 1995-05-25 | 1995-05-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08321543A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008120348A1 (en) * | 2007-03-29 | 2008-10-09 | Fujitsu Microelectronics Limited | Process for producing semiconductor device |
-
1995
- 1995-05-25 JP JP12666095A patent/JPH08321543A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008120348A1 (en) * | 2007-03-29 | 2008-10-09 | Fujitsu Microelectronics Limited | Process for producing semiconductor device |
| US20100009544A1 (en) * | 2007-03-29 | 2010-01-14 | Fujitsu Microelectronics Limited | Manufacturing method of semiconductor device |
| JP5375601B2 (en) * | 2007-03-29 | 2013-12-25 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| US8629055B2 (en) | 2007-03-29 | 2014-01-14 | Fujitsu Semiconductor Limited | Manufacturing method of semiconductor device |
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