JPH08335680A - Method and equipment for forming internal electrode in high-density and high-permittivity memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the formation of ear by a method wherein an obliquely gradient inner electrode is formed on a flat plate with the inner electrode evaporated thereon. SOLUTION: Elements 10 and 12 are evaporated outside the active region 16 of a substrate 14. The element 10 contains a conductive plug 20 and a barrier layer 22. Likewise, the element 12 contains another conductive plug 26 and another barrier layer 28. An inner level insulating layer 24, separating the active region 16 from a layer 30 made of a material stable with respect to oxygen, is used for the formation of the elements 10 and 12. The ear formation can be avoided by the formation of mask bodies 50 and 52, making an oblique angle with the other surface of the layer 30. The sidewall angle of the mask bodies 50 and 52 is transferred to the shape of the inner electrode formed of the layer 30. In such a constitution, the ear formation can be prevented by the sidewall making the oblique angle, thereby enabling homogeneous evaporation of outer layer to be enhanced further efficiently and effectively.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to the field of electronic devices, and more particularly to an improved method for forming internal electrodes in high density memory devices using high dielectric constant materials. .

[0002]

BACKGROUND OF THE INVENTION There is an increasing need for high density device construction, especially in memory systems, and is addressed by the use of high dielectric constant materials, particularly to form capacitive storage elements in memory cells. In the direction. The storage capacity of individual memory cells in a memory array is related to the dielectric constant of the high-k capacitor dielectric and the surface area of the interface between the dielectric and the internal and external electrodes of the capacitor.

Various new materials are currently used as high dielectric constant materials. Since many of these materials are deposited in an oxygen atmosphere, materials that do not oxidize as internal electrodes,
For example platinum, ruthenium or other noble metals are required. As previously mentioned, in view of the storage capacity of a given memory cell, it is advantageous to have an internal electrode with a large surface area in contact with the dielectric of the capacitor. Therefore, the shape of the internal electrode often forms a platinum electrode body having an extremely large geometrical aspect ratio. The aspect ratio required for the structure, combined with the characteristics of the material that must necessarily be used for the internal electrodes, creates processing problems that are of a type never experienced in the formation of integrated circuits. . One of the most difficult problems to solve is the formation of "ears" in the outer corners of the inner electrodes during the etching operation used to form the inner electrodes. As mentioned herein, an ear is an extension of the material to be etched that is built up during the etching process. The formation of ears can contaminate adjacent structures, making homogeneous deposition of dielectric material after forming the internal electrodes virtually impossible. In addition, it is desirable to produce the bottom electrode with sloping sidewalls instead of vertical sidewalls because of the problems associated with performing the high dielectric constant material deposition process homogeneously. The process used to remove the "ears" is suitable for forming beveled sidewalls.

Accordingly, there is an increasing need for processing techniques that eliminate the formation of ears during the processing procedure used to create the internal electrode structure of high dielectric constant capacitive storage elements of memory cells.

[0005]

SUMMARY OF THE INVENTION The teachings of the present invention provide a processing method for the generation of memory cells, which essentially reduces or eliminates the drawbacks associated with conventional processing techniques. It is a thing.

[0006]

According to one embodiment of the present invention, there is provided a method of forming a memory cell, the internal electrode having an oblique inclination with respect to a flat plate on which the internal electrode is deposited. Including the step of forming. According to one embodiment of the present invention, the internal electrodes having an oblique inclination are formed by depositing a layer of a material that is difficult to oxidize, then depositing a photoresist layer, and patterning to form a layer of a material that is difficult to oxidize. Formed by producing a photomask body having oblique sidewalls with respect to the outer surface of the.

[0007]

A more complete understanding of the features of the present invention may be gained by reference to the accompanying drawings, wherein like numerals indicate like items.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIGS. 1A-1C illustrate the resulting problematic sequence of "ears" formed on the internal electrodes of a high dielectric constant capacitive element of a memory device. In FIG. 1A, two memory storage elements, shown generally at 10 and 12, are in the process of being formed on the outside of a substrate 14, which substrate has an active region 16 proximate an outer surface 18. The substrate 14 is made of, for example, silicon. Alternatively, the substrate 14 may be composed of another single component semiconductor, such as germanium or diamond. In addition to this, the substrate 14 may be made of a synthetic semiconductor such as gallium arsenide, indium phosphide, silicon germanium, or silicon carbide.

Active region 16 comprises the diffused and non-diffused regions of a conventional integrated circuit formed in substrate 14. For example, active region 16 comprises transistors, conductive interconnects, and resistors formed of a suitable doping material diffused through outer surface 18 of substrate 14.

The element 10 includes a conductive plug 20 and a barrier layer 2.
2, which is formed in an opening through the inner level insulating layer 24. Similarly, element 12 is a conductive plug 2 formed in a second opening through an inner level insulating layer 24.
6 and barrier layer 28.

The inner level insulating layer 24 is made of, for example, silicon dioxide, boron phosphide silicide glass, or spin-on glass. The inner level insulating layer 24 may also be composed of a plurality of layers including a diffusion barrier composed of, for example, silicon nitride. Diffusion barriers are particularly useful when the layer is formed from an inner level insulating layer 24 containing a compound, which may migrate through the inner level insulating layer 24 and diffuse into the active region 16. Because. For example, if the outer layer contains a lead compound, the barrier in the inner level insulating layer 24 may prevent such lead compound from diffusing into the active region 16.

The conductive plugs 20 and 26 are made of a material that easily oxidizes, for example, polycrystalline silicon, which is doped to have conductivity. The conductive plug 20 also
It may be composed of titanium nitride, titanium silicide, or other reactive metal compounds such as zirconium nitride, tantalum silicide, tungsten silicide, molybdenum silicide, nickel silicide, or titanium boride. Further, the conductive plug 20 may be made of a reactive metal such as tungsten, tantalum, titanium, or molybdenum.
The conductive plug 20 may also be composed of a conductive carbide or boride such as boron carbide. Conductive plug 20
May also be composed of doped synthetic semiconductors such as gallium arsenide, indium phosphide, a combination of silicon and germanium, or silicon carbide. The conductive plug 20 may also be a combination of various materials shown above.

The barrier layers 22 and 28 may be made of titanium nitride, for example. Further, the barrier layer 22 is a ternary compound or a large amorphous nitride, such as Ta-Si-.
It may be made of N, Ta-BN, or Ti-BN. Barrier layer 22 also includes various new types of conductive nitrides such as zirconium nitride, hafnium nitride, yttrium nitride, scandium nitride, lanthanum nitride, and other rare earth nitrides such as Ti-Al-N, N-deficient aluminum nitride, Al-doped aluminum nitride. , Magnesium nitride, calcium nitride, strontium nitride, and barium nitride. Furthermore,
The barrier layer 22 may be made of an alloy of the above-mentioned new-type conductive nitride and a general silicon processing material such as titanium nitride, gallium nitride, nickel nitride, cobalt nitride, tantalum nitride, and tungsten nitride. Further, the barrier layer 22 is made of various noble metal insulating alloys such as Pt-Si-.
N, Pd-Si-O, Pd-B- (O, N), Pd-A
1-N, Ru-Si- (O, N), Ir-Si-O, R
It may be composed of e-Si-N, Rh-Al-O, Au-Si-N, or Ag-Si-N. Furthermore,
The barrier layer 22 may be composed of a heterogeneous structure including multiple layers and a combination of the above materials.

In general, device 10 is electrically coupled to barrier layer 22.
And a capacitor formed on the outside of the capacitor. As well
And the device 12 is electrically connected to the barrier layer 28 and
Including formed capacitors. The internal electrode of the capacitor is
Formed from a single layer 30 of oxygen stable material
This material contains, for example, platinum or ruthenium oxide.
Mu. Oxygen stable layer 30 and formed from it
The internal electrodes are also made of other precious metals or platinum group or
Their alloys, such as palladium, iridium, Reniu
May consist of aluminum, rhodium, gold or silver
Yes. Further, the inner level insulating layer 24 is a conductive metal compound,
For example, ruthenium oxide, tin oxide, indium oxide, oxide
Rhenium, osmium oxide, rhodium oxide, iridium oxide
Um, or doped tin, indium, or
It may be made of zinc oxide. In addition, the internal level
The insulating layer 24 is a conductive perovskite-like material, such as Y
Ba ₂Cu₃O_7-X, (La, Sr) CoO₃Composed of
It doesn't matter. Further, the inner level insulating layer 24 is on top.
Composed of a heterogeneous structure consisting of a combination of the listed materials
It doesn't matter.

As explained above, FIGS. 1A-1C illustrate the problems encountered in forming internal electrodes from layer 30 using conventional photolithographic techniques. Returning to FIG. 1A,
A layer of photoresist material is deposited on the exterior surface of layer 30 and developed so that mask bodies 32 and 34 are formed. The mask body 32 is deposited outward from the barrier layer 22, and similarly the mask body 34 is formed outward from the barrier layer 28. In FIG. 1B, layer 30 has been etched to expose portions of the outer surface of inner level insulating layer 24. A material is formed on the sides of the mask bodies 32 and 34 as a result of the etching process used to etch the layer 30 of oxygen stable material. FIG.
As shown at B, this forms ears 36 and 38 on the sidewalls of the mask body 32 and extending outwardly from the internal electrode body 40 formed from the layer 30 previously described. Similarly,
Ears 42 and 44 are formed on the sidewalls of mask body 34 and extend outwardly from internal electrode bodies 46 formed from layer 30.

FIG. 1C illustrates the structure described above after removing the mask bodies 32 and 34.
In order to complete the shape of the devices 10 and 12, a uniform vapor deposition of high dielectric constant material must be performed from the inner electrode bodies 40 and 46 to the outside. In addition, a uniform vapor deposition of the external electrode material must be carried out from the layer of high dielectric constant material. Performing the uniform vapor deposition of these internal electrode bodies 40
Impossible because of the ears 36, 38, 42 and 44 formed in making Besides preventing efficient and uniform deposition of the outer layers, the ears 36, 38, 42 and 44 are extremely brittle and prone to flaking, which also contributes to free particle contamination during subsequent processing procedures. In summary, the ears 36, 38, 42 and 44 are formed during the formation of the internal electrode bodies 40 and 46.
It is very important to prevent the formation of

2A-2C illustrate the treatment method of the present invention, which results in efficient formation of internal electrode bodies and prevents the formation of ears 36, 38, 42 and 44 as described above. . In FIG. 2A, the construction of the internal regions of elements 10 and 12 is the same as that described with reference to FIGS. 1A-1C. That is, devices 10 and 12 are deposited outward from active region 16 of substrate 14. The device 10 includes a conductive plug 20 and a barrier layer 22. Similarly, device 12 includes a conductive plug 26 and a barrier layer 28. Inner level insulation layer 2
4 separates the active region 16 from a layer 30 of a material which is stable to oxygen, which layer is used to form the internal electrodes of the devices 10 and 12.

The formation of ears 36, 38, 42 and 44 is prevented by forming mask bodies 50 and 52. The mask bodies 50 and 52 have sidewalls that have an oblique angle to the outer surface of layer 30. As shown here, the sidewall angles of mask bodies 50 and 52 are transferred to the shape of the internal electrodes formed from layer 30. The oblique angle of the sidewalls prevents the formation of ears 36, 38, 42 and 44 and allows for more efficient and effective progress in the uniform deposition of the outer layer.

After the etching process is used to produce the inner electrodes 54 and 56, a small amount of silicon or other material may be deposited on the sloping sidewalls of the electrodes 54 and 56. This silicon is the result of over-etching into the outer surface of the inner level insulating layer 24. This substance is a structure
It can be removed by exposure to hydrogen fluoride vapor etching prior to subsequent processing. Hydrogen fluoride vapor etching removes unwanted material from the sidewalls of electrodes 54 and 56, while leaving electrodes 54 and 56 of oxygen stable materials intact.

FIG. 2B illustrates the structure of the devices 10 and 12 after the anisotropic etching process, except for the portion of the inner electrode 54 associated with device 10 and the inner electrode 56 associated with device 12. Remove all of layer 30. As explained above, the internal electrodes 54 and 56 are composed of, for example, platinum or other oxygen-stable material described above.

As shown in FIG. 2B, the shape of the mask bodies 50 and 52 is transferred to the shape of the inner electrode bodies 54 and 56 during the etching process used to form the inner electrode bodies 54 and 56. Be done. Therefore, the inner electrode bodies 54 and 56 have obliquely inclined side walls on the outer surface of the inner level insulating layer 24.

The sloped sidewalls of mask bodies 50 and 52 can be made in a variety of ways. The mask bodies 50 and 52 can be formed with sidewalls perpendicular to the outer surface of layer 30. The mask body is then put into an etching process, where the sharp edges on the outside are effectively shaved off, creating sloping sidewalls of the mask bodies 50 and 52. Alternatively, mask bodies 50 and 52 with sloping sidewalls can be created using a photoresist material that does not maintain a sharp geometry. Thus, the sharp outer corners of the mask bodies 50 and 52 are removed during development and during processing of the photoresist layer used to create the mask bodies 50 and 52. Alternatively, a photolithographic technique may be used to define the mask bodies 50 and 52 to intentionally defocus. The mask body 5 exposed by defocusing the mask body 5
The boundaries of 0 and 52 are dimly defined, producing sloping sidewalls.

FIG. 2C illustrates the completed structure of devices 10 and 12. The device is completed by uniformly depositing a layer 58 of high dielectric constant material on the outside of the inner electrodes 54 and 56.

Layer 58 is, for example, barium strontium titanate or other perovskite, pyroelectric material, ferroelectric, or other high dielectric constant oxide, such as (Ba, Sr, Ca, Pb) (Ti, Zr). ) O ₃ ,
(Pb, La) (Zr, Ti) O ₃ , bismuth titanate, lead niobate, potassium niobate, lead zinc niobate, lead magnesium niobate, tantalum pentoxide, or yttrium oxide. The high dielectric constant layer 58 may also be a combination of the above materials or multiple layers of the above materials.

The outer electrode layer 60 is then uniformly deposited on the outside of the high dielectric constant layer 58. The outer electrode layer 60 is composed of platinum or other noble metal or platinum group metal, such as palladium, ruthenium, rhodium, gold, iridium, or silver. In addition, the outer electrode 60 is a conductive metal compound such as titanium nitride, ruthenium nitride, tin nitride, zirconium nitride, tungsten nitride, ruthenium dioxide, tin oxide, zinc oxide, doped zinc oxide, iridium oxide,
It may be made of titanium silicide, tantalum silicide, tungsten silicide, molybdenum silicide, nickel silicide, tantalum carbide, or titanium boride. Further, the external electrode 60 may be made of a reactive metal such as tantalum, titanium, molybdenum, or tungsten. Furthermore, the outer electrode 60 may be composed of typical conductive materials used in semiconductor processing as well as metallization, such as aluminum, doped silicon, or germanium. The external electrode 60 may be configured as a combination of the above substances or as a multi-layer of the above substances.

The elements 10 and 12 are insulated from the external environment or other external active circuitry using an external insulating layer 62, which is homogeneously deposited over the outer electrode layer 60. Layer 62 comprises, for example, silicon oxide, borophosphorus silicide glass, or spin-on glass.

As described above, the vapor deposition of the high dielectric constant layer 58 and the external electrode layer 60 is performed by forming the sidewalls of the internal electrodes 54 and 56 at an angle with respect to the external surface of the internal level insulating layer 24. Helped by being Internal electrode 5
The angled sidewalls of 4 and 56 make it easier to keep the thickness of layers 58 and 60 constant. The constant thickness of the high-k layer 58 helps maintain constant device characteristics for different storage elements in an array of memory devices formed using the process of the present invention. So it's very important.

It is important to control the corner and sidewall thickness of the patterned, oxygen stable inner electrode. For example sputtering, sol-gel or other liquid deposition techniques, as well as plasma enhanced CV
Some vapor deposition techniques such as D technique have poor sidewall coverage. Therefore, it is useful to have neatly sloped sidewalls. If the inner electrode is rather large, controlling the size of the inner electrode is not a major issue due to the sloped sidewalls. If the side wall angle is defined as 90 degrees when the side wall is completely vertical, the more inclined the side wall, the more beneficial it is to maintain a uniform thickness. In one embodiment, Pt internal electrodes are patterned and etched to have 30 degree sidewalls. Big (2
Micron or larger) Pt internal electrode, 50 to 100 nanometers thick, is pre-annealed in O ₂ for 5 minutes, followed by N ₂ for 5 minutes at 50 to 100 ° C.
Annealed at the BST deposition temperature of. Next, high dielectric constant material (B
ST) is sputter deposited at 450 ° C. Chemical cleaning using either wet or dry HF vapor is
Also performed after t-etching, photoresist removal, and before pre-annealing. 50 ° -60 °, 40 ° -50 °, 30 ° -40 ° and 20 using the same or similar techniques
It is possible to form inner electrodes with sidewall angles of -30 degrees, these angles being each appropriate depending on the particular application or operating environment.

Although the present invention has been described in detail, various changes, modifications and substitutions can be made using the methods and systems described herein without departing from the spirit and scope of the invention. It is to be understood that the spirit and scope of the present invention are defined only by the appended claims. The following items are further disclosed with respect to the above description.

(1) A method for forming a memory device proximate to an active region deposited in an outer surface of a semiconductor substrate; forming a conductive plug electrically connected to the active region; Forming a partially exposed inner electrode on the outer surface of the inner level insulating layer that is conductively coupled with the conductive plug and surrounds the conductive plug, the inner electrode being relative to the outer surface of the inner level insulating layer. A side wall having an obliquely inclined angle; a high dielectric constant layer is uniformly vapor-deposited so as to cover the outside of the internal electrode; an external electrode layer is vapor-deposited uniformly so as to cover the outside of the high dielectric constant layer, Such a method comprising a procedure.

(2) The method of claim 1 further comprises: forming a barrier layer between the inner electrode and the conductive plug, the barrier layer being arranged to electrically connect the inner electrode to the conductive plug. Including the method.

(3) In the method of claim 1, the procedure for forming the internal electrodes further comprises: depositing a layer of oxygen stable material outwardly from the inner level insulating layer and the conductive plug; Forming a mask body having side walls at an oblique angle to the outer surface of the layer of oxygen-stable material; and etching the mask body and the layer of oxygen-stable material Forming an internal electrode having side walls at an angle oblique to the outer surface of the inner level insulating layer.

(4) In the method according to the third aspect, the procedure for forming the mask body is: having sidewalls that are essentially perpendicular to the outer surface of the layer of oxygen stable material. Forming a mask body; and etching the mask body such that the sidewalls of the mask body are inclined at an angle to the outer surface of the layer of oxygen stable material.
The method.

(5) In the method of claim 3, the procedure for forming the mask body further comprises: depositing a photoresist layer on the outside of the layer of oxygen stable material; And exposing the radiant energy in focus to leave a mask body with obliquely sloping sidewalls with respect to the layer of oxygen stable material when the photoresist is developed. The method comprising:

(6) In the method according to the first aspect, the procedure for forming the internal electrode is such that the internal electrode has a sidewall having an angle of 50 to 60 degrees with respect to the outer surface of the inner level insulating layer. Said method comprising the step of forming a.

(7) In the method described in the first item, the procedure for forming the internal electrode is such that the internal electrode has a sidewall having an angle of 40 to 50 degrees with respect to the outer surface of the inner level insulating layer. Said method comprising the step of forming a.

(8) In the method according to the first aspect, the procedure for forming the internal electrode is such that the internal electrode has a sidewall having an angle of 30 to 40 degrees with respect to the outer surface of the inner level insulating layer. Said method comprising the step of forming a.

(9) In the method according to the first aspect, the procedure for forming the internal electrode is such that the internal electrode has a sidewall having an angle of 20 to 30 degrees with respect to the outer surface of the inner level insulating layer. Said method comprising the step of forming a.

(10) A method for forming a memory device proximate to an active region deposited in an outer surface of a semiconductor substrate; forming a conductive plug electrically connected to the active region; Forming a barrier layer electrically connected to the conductive plug; depositing a layer of oxygen stable material outward from the inner level insulating layer and the conductive plug; of oxygen stable material Forming a mask body having side walls at an angle oblique to the outer surface of the layer; and etching a layer of the mask body and an oxygen stable material on the outer surface of the inner level insulating layer. Forming an inner electrode having obliquely inclined side walls with respect to it and electrically connected to the conductive plug through a barrier layer; uniformly depositing a high dielectric constant layer so as to cover the outside of the inner electrode; And covers the outside of the high-k layer Homogeneously depositing urchin outer electrode layer,
The method including the above steps.

(11) In the method according to the sixth aspect, the procedure for forming the mask body is: a mask body having sidewalls that are basically perpendicular to the outer surface of the layer made of an oxygen stable material. And etching the mask body such that the sidewalls of the mask body are inclined at an angle to the outer surface of the layer of oxygen stable material.

(12) In the method of claim 6, the procedure for forming the mask body further comprises: evaporating a photoresist layer outside a layer of oxygen stable material; And exposing the radiant energy in focus to leave a mask body with obliquely sloping sidewalls with respect to the layer of oxygen stable material when the photoresist is developed. including,
The method.

(13) A memory device in contact with an active region disposed in an outer surface of a semiconductor substrate; a conductive plug electrically connected to the active region; and conductively coupled to the conductive plug. An inner electrode partially disposed on the outer surface of the inner level insulating layer surrounding the conductive plug and having a sidewall having an oblique angle with respect to the outer surface of the inner level insulating layer; A memory device having a high dielectric constant layer disposed on the outer side thereof; and an external electrode layer disposed on the outer side thereof so as to cover the high dielectric constant layer.

(14) The memory device according to item 9, further comprising: a barrier layer disposed between the internal electrode and the conductive plug so as to electrically connect the internal electrode and the conductive plug. The memory device, including:

(15) Memory devices (10) and (1
2) is presented, which comprises inner electrode bodies (54) and (5) having sidewalls inclined at an oblique angle to the outer surface of the inner level insulating layer (24).
6) is included. The sloping sidewalls of the inner electrode bodies (54) and (56) allow the high dielectric constant layer (58) and the outer electrode layer (60) to be more evenly deposited to allow the devices (10) and (12) to be more uniformly deposited. It is possible to complete the formation.

RELATED SPECIFICATIONS This specification contains US patent specification serial no.
, Filed June 6, 1995, entitled "Semiconductor Structure Using High Dielectric Constant Material and Adhesive Layer and Method for Forming It", (Attorney's Schedule No. TI-19508), and
US Patent Specification Serial No. 19,
Submitted June 6, 1995, Name "Method of high dielectric constant material",
(Representative Inquiry Schedule Number TI-19509).
The following previously filed specifications relate to the currently pending specification. U.S. Patent Specification Serial No. 08 / 283,8
81, Invented by the name "Improving High Dielectric Constant Material Electrodes Including Thin Platinum Layers" (Scheduled Attorney's Trial No. TI-17950), Summerfeld, Beratan, Carlin, and Gnade; U.S. Patent Serial No. 08 / 283, 46
8, name "improved electrode containing conductive perovskite nuclear layer for perovskite dielectric", (attorney trial schedule number T
I-17952), invented by Summerfelt and Beratan; U.S. Pat. No. 08 / 283,44
2, name "improved high dielectric constant material electrode containing thin ruthenium oxide layer", (attorney's scheduled trial number TI-1915
3), invented by Summerfelt, Bellatan, Carlin and Gnade; U.S. Patent Specification Serial No. 08/2
83, 467, name "preoxidized high dielectric constant material electrode", (Scheduled attorney trial number TI-19189), invented by Nishioka, Summerfelt, Park and Patachalaya; U.S. Pat. No. 08 / 283,871, name"
High-permittivity material electrode including sidewall gap plate ", (Scheduled Attorney's Trial No. TI-19272), invented by Nishioka, Park, Patachalaya and Summerfelt; US Patent Specification Serial No. 08 / 283,441, Name" High Conductive Amorphous Nitride Barrier Layer for Permittivity Material Electrodes, "(Attorney Schedule No. TI-19554), invented by Summerfeld; US Patent Serial No. 08 / 283,87.
3, name "conductive new type nitrided barrier layer for high dielectric constant material electrode", (Scheduled trial attorney no. TI-19555), invented by Summerfelt; US Patent Serial No. 08
/ 276, 191, name "Electrode lightly doped with donor for high dielectric constant material electrode", (Attorney trial plan number T
I-17660.1), invented by Summerfelt, Beratan and Gnade; U.S. Patent Specification Serial No. 08
/ 009,521, "improved electrical connection to dielectric material", (attorney attentive number TI-17339), invented by Gnedo and Summerfeld; U.S. patent specification serial number 08 / 260,149, title "Lightly doped donor electrode for high dielectric constant material electrodes", (Scheduled Attorney's Trial No. TI-17339.1), invented by Summerfelt, Beratan and Gneed; US Patent Serial No. 08 / 040,946 , Name "Lightly Doped Donor Electrode for High Dielectric Material Electrodes", (Attorney Scheduled TI-17660), Summerfelt,
Invented by Beratan and Gnade; and U.S. Patent Specification Serial No. 08 / 041,025, entitled "Improved Electrode Interface for High Permittivity Material Electrodes", (Attorney's Schedule No. TI-17661), Summerfelt and Invented by Beratan.

[Brief description of drawings]

FIG. 1 illustrates a sequence of processing steps for forming ears on internal electrodes of a high dielectric constant capacitive element of a memory device.

FIG. 2 illustrates the processing method of the present invention, which eliminates the formation of ears on the internal electrodes of a high dielectric constant capacitive element of a memory device.

[Description of Reference Signs] 10, 12 Memory Device 14 Semiconductor Substrate 16 Active Region 18 External Surface of Active Region 20, 26 Conductive Plug 22, 28 Barrier Layer 24 Inner Level Insulating Layer 30 Oxygen Stable Layer 32, 34, 50 , 52 mask body 36, 38, 42, 44 ear 40, 46, 54, 56 internal electrode body 58 high dielectric constant layer 60 external electrode layer 62 external insulating layer

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 27/04 21/822 (72) Inventor Paul Jay. Square Square Star Circle, Boise, Idaho, USA 2835

Claims (2)

[Claims] 1. A method for forming a memory device proximate to an active region deposited in an outer surface of a semiconductor substrate; forming a conductive plug electrically connected to the active region; Conductively coupled to the conductive plug and forming a partially exposed inner electrode on the outer surface of the inner level insulating layer surrounding the conductive plug, the inner electrode being oblique to the outer surface of the inner level insulating layer. The step of uniformly depositing the high dielectric constant layer so as to cover the outer side of the internal electrode; and uniformly depositing the outer electrode layer so as to cover the outer side of the high dielectric constant layer. The method comprising: 2. A memory device in contact with an active region disposed within an outer surface of a semiconductor substrate; a conductive plug electrically connected to the active region; conductively coupled to the conductive plug; An inner electrode partially disposed on the outer surface of the inner level insulating layer surrounding the conductive plug and having sidewalls with an oblique angle to the outer surface of the inner level insulating layer; The memory device according to claim 1, further comprising: a high dielectric constant layer disposed on the outer side of the high dielectric constant layer; and an external electrode layer disposed on the outer side of the high dielectric constant layer so as to cover the high dielectric constant layer.