JPH08330438A - Complementary mosfet and its manufacture - Google Patents

Abstract

PURPOSE: To increase the operation speed of a complementary MOSFET and reduce its parasitic resistance, by making the junction width of the shallow junction source/drain of its N-channel MOSFET suitable. CONSTITUTION: In a complementary MOSFET, a P-channel MOSFET wherein first and second sidewalls 45, 46 are formed and an N-channel MOSFET wherein only the second sidewall 46 is formed are provided, and the sidewall width of the P-channel MOSFET is made larger by the first sidewall width than the sidewall width of the N-channel MOSFET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (M) having a fine gate length, which can operate at high speed and is highly reliable.
OSFET), especially complementary MOSFET (CMOSF
ET) structure and manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the high integration of LSIs, MO
The gate length of SFET has been reduced to about 0.1 μm. Due to the miniaturization of the gate length of such a MOSFET, the mutual conductance (gm) increases,
The delay time of signal propagation is shortened, and high speed operation becomes possible. In order to operate such a fine MOSFET at high speed, there are some points to be improved over the conventional technique.

One of them is the source / drain (S / D).
It is possible to reduce the amount of overlap between the region and the gate electrode or the amount of offset. This is to reduce the gate overlap capacitance or the S / D parasitic resistance, which is an obstacle to speeding up. CMOS devices include N-channel MOSFETs (NMOSFE).
T) and P-channel MOSFET (PMOSFET) exist, but the diffusion speed of P-type impurities (B etc.) in the silicon (Si) substrate is faster than the diffusion speed of N-type impurities (As etc.). , S / D region and gate electrode overlap amount or offset amount is set to NMOSFET and P
It is difficult to control with MOSFET simultaneously.

As a method for controlling this, "K.
F. Lee et al, IEDM Tech. Dig.
(1993) p. 131 ”. FIG. 4 is a sectional view showing the structure of such a conventional CMOSFET,
FIG. 5 and FIG. 6 are views for explaining the explanation, and are process diagrams schematically shown with sectional views. The left side is NMOS
FET, the right side represents PMOSFET.

(1) First, as shown in FIG. 5A, a recessed LOCO is formed on a silicon substrate 21 by a known technique.
S (Local Oxidation of Sili)
(con) 22 is formed at 750 nm, and then the P-well 23a and the N-well 2 are formed by using a high-energy ion implanter.
3b is formed. Boron (B) is 400 KeV at 1 × 10 ¹³ cm ^{−2 to} form the P well 23a, and phosphorus (P) is 900 KeV at 1 × 1 to form the N well 23b.
0 ¹³ cm ^{-2 is} introduced.

(2) Next, a resist pattern (not shown) serving as a mask for limiting the ion implantation region is formed. Using this resist pattern as a mask, FIG.
, The region 24a under the gate of the P well 23a and the region 24 under the gate of the N well 23b.
Only in b, punch-through suppression implantation for suppressing the short channel effect and channel implantation for controlling the threshold voltage are performed by the ion implantation method.

The punch-through suppression implanter and the channel implanter for the P-well 23a are formed in the region 2 respectively.
B is introduced into 4a at 45 KeV at 4 × 10 ¹² cm ⁻² and boron fluoride (BF ₂ ) at 90 KeV at 1 × 10 ¹³ cm ⁻² . Further, the punch-through suppression implanter and the channel implanter for the N well 23b are respectively formed in the region 24.
b to P at 120 KeV, 4 × 10 ¹² cm ^-2 , arsenic (A
s) is introduced at 100 KeV and 1 × 10 ¹³ cm ⁻² .

(3) Next, as shown in FIG.
The gate oxide film 25 is formed to a thickness of 4 nm at 800 ° C. in an oxidation furnace.
Form. Then, a polysilicon film 26 having a thickness of 200 nm and a silicon nitride film 27 having a thickness of 100 n are formed thereon by LPCVD.
After forming m, a resist pattern (not shown) serving as a mask for patterning the gate electrode is formed. Using this resist pattern as a mask, unnecessary portions of the polysilicon film 26 and the silicon nitride film 27 are etched to form a gate electrode (polysilicon film) 26 of a polysilicon film having a gate length of about 0.1 μm.

(4) Next, as shown in FIG.
Ions are implanted into the P well 23a, and As ₂ is introduced at 10 KeV at 5 × 10 ¹⁴ cm ⁻² to form a shallow junction S / D (shallow junction S / D) 28a of the NMOSFET. (5) Next, as shown in FIG. 5 (E), TEOS (T
A 50 nm SiO ₂ film is formed by a CVD method using an Etra Etyl Ortho Silicate), and then etched back by reactive ion etching (RIE) to form the first sidewall 29. After that, BF is implanted into the N well 23b by ion implantation.
₂ was introduced at 1 × 10 ¹⁵ cm ^{-2 at} 10 KeV, and PMOSF
A shallow junction S / D 28b of ET is formed.

(6) Next, as shown in FIG.
200 nm SiO 2 by EOS and CVD method
_{After the two} films are formed, reactive ion etching (RI
Etch back according to E), and the second sidewall 3
Form 0. (7) Next, as shown in FIG.
D (deep junction S / D) 31a and 31b are formed by ion implantation. Deep junction S / D 31a of the NMOSFET
Introduces As at 5 × 10 ¹⁵ cm ^-2 at 20 KeV, PM
The deep junction S / D 31b of the OSFET uses BF ₂ of 10 Ke
It is formed by introducing 5 × 10 ¹⁵ cm ^{−2 of} V.

The reason why the deep junction S / D is formed in this way is that platinum (P
This is to prevent the junction from being lost due to the consumption of Si in the reaction at the time of salicide of t). Even if salicide is not used, the S / D is reduced in order to reduce the S / D resistance.
Needs to be deep. (8) After that, as shown in FIG. 6C, annealing (drive-in) was performed using a rapid heating device (RTA) at 1050 ° C. for 10 seconds, and then using a furnace at 800 ° C. for 20 minutes.
Then, a CMOSFET having a fine gate length is formed. This heat treatment causes activation and diffusion of impurities to deepen the junction and eliminates the offset between the gate and the shallow junction S / D in the PMOSFET.

In this way, the CMOSFET is formed. FIG. 4 shows the CMOSFET as an NMOSFET and a PMOSFET.
FIG. 4 is a sectional view showing the MOSFET separately.
4A is a cross-sectional view of the NMOSFET before annealing, FIG.
4B is a cross-sectional view of the PMOSFET before annealing, FIG.
4C is a cross-sectional view of the NMOSFET after annealing, FIG.
(D) is a cross-sectional view of the PMOSFET after annealing.

As is apparent from these figures, the NMOS
Width d of S / D 28a, 28a 'of the shallow junction of FET
_{1 + 2} is the width of the first sidewall 29 + the width of the second sidewall 30, whereas the PMOSFET is
The width d ₂ of the S / Ds 28b and 28b 'of the shallow junction is only the width of the second sidewall 30. Thus, N
In MOSFET, after gate etching, PMOSFET
Then, by performing the ion implantation for forming the shallow junction S / D after the formation of the first sidewall, it is possible to almost eliminate the overlap amount of the gate and the S / D or the offset amount in both the NMOSFET and the PMOSFET, and to operate at high speed. C with high reliability and fine gate length
It can be a MOSFET.

[0014]

However, in the conventional CMOSFET, the gate / shallow junction S / D overlap amount or offset amount can be almost eliminated. However, as shown in FIG. The length of D is PMOSFE in NMOSFET even after drive-in.
There is a problem that the parasitic resistance becomes large due to the influence of the junction of the shallow junction S / D portion because the width becomes longer than that of T by approximately the first sidewall width on one side, which causes a decrease in operating speed.

Since the thickness of the shallow junction S / D is very thin (several tens nm) before the drive-in, if the etching selection ratio of SiO ₂ / Si is not so large, there is a problem as shown in FIG. Occurs. That is, FIG. 7B and FIG.
As shown in (c), at the time of etching for forming the first sidewall, the shallow junction S / D portion of the NMOSFET is cut under the second sidewall so that it does not operate. Alternatively, as shown in FIGS. 7D and 7E, even if the surface layer is slightly etched, the surface layer having a high concentration disappears, so that the concentration of the shallow junction S / D decreases and the resistance increases. Therefore, there is a problem that high speed operation cannot be expected.

The present invention eliminates the above problems and provides an NMOS
It is an object of the present invention to provide a complementary MOSFET and a method for manufacturing the same that can make the junction width of the shallow junction source / drain of the FET appropriate, reduce the parasitic resistance, and increase the operating speed.

[0017]

In order to achieve the above object, the present invention provides: (1) In a complementary MOSFET, a P-channel MOSFET in which first and second sidewalls are formed and a second sidewall. N-channel MOSF only formed
ET is provided, and the sidewall width of the P-channel MOSFET is made larger than the sidewall width of the N-channel MOSFET by the first sidewall width.

(2) In a method of manufacturing a complementary MOSFET, a step of patterning a gate electrode and LSCV
After the glass precursor resist solution is atomized by the method D and then applied on the substrate, a negative resist is spin-coated, and then radiant light is emitted to form a resist and a glass in the P-channel MOSFET region. After exposing the precursor resist film, it is heated to convert the glass precursor resist film into a silicon oxide film, while the N-channel MO film is used.
Developing and removing the resist in the SFET region and the glass precursor resist film, and the N-channel MOSFE
A step of performing ion implantation for forming a source / drain of a shallow junction of T, and after removing the resist on the glass precursor resist film, using the resist to form the N channel MO
After masking the SFET region, a step of etching back by reactive ion etching to form a first sidewall and a step of performing ion implantation for forming a source / drain of the shallow junction of the P-channel MOSFET are performed. It is something that is applied.

(3) Complementary MOSFE according to the above (2)
In the manufacturing method of T, the glass precursor resist solution is dissolved in an atomizable solvent in the LSCVD method.

[0020]

[Action]

(1) According to the complementary MOSFET of claim 1, a P-channel MO in which the first and second sidewalls are formed.
An SFET and an N-channel MOSFET in which only the second sidewall is formed, and the P-channel MOSF
The sidewall width of ET is the same as the N-channel MOSFE
Since it is made larger than the sidewall width of T by the first sidewall width, the width of the junction of the shallow junction source / drain of the NMOSFET can be made appropriate, the parasitic resistance can be reduced, and the operating speed can be reduced. The speed can be increased.

(2) A complementary MOSFET according to claim 2.
According to the manufacturing method of (1), since the GPR film is used, the SiO ₂ film to be the first sidewall film can be formed only in the PMOSFET region by photolithography, and as shown in FIG. The length of / D is almost equal to the width of the second sidewall in both NMOSFET and PMOSFET before and after drive-in, and the length of the shallow junction S / D is N.
It becomes long only in the MOSFET, so that the operating speed is not lowered due to the influence of the parasitic resistance.

Further, after the ion implantation of the shallow junction S / D is performed, the etching back of the first sidewall in the region is not performed, so that the S / D of the shallow junction is cut off under the second sidewall, or It is possible to prevent the S / D concentration of the shallow junction from decreasing and becoming high resistance. Further, although the GPR film of the radiation-sensitive resist is used, the batch exposure is performed by forming a laminated structure with the resist for the excimer. Therefore, there is no increase in the photolithography process. There is also the advantage that there is no difference.

(3) Complementary MOSFET according to claim 3
According to the glass precursor resist solution, LSCV
In the method D, since the solvent is dissolved in the atomizable solvent, even a raw material having a low vapor pressure can be gasified to form a film. Further, in the CVD method, the introduced gas reacts on the substrate to form a thin film, so the introduced gas and the film-formed substance are different, but since the LSCVD method deposits at room temperature, the introduced substance is the same as the thin film. can do.

The thin film formed by the LSCVD method is
The step coverage becomes good like the thin film formed by the CVD method.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a complementary type M showing an embodiment of the present invention.
FIG. 1 is a sectional view showing an OSFET separated into an NMOSFET and a PMOSFET, and FIG.
Cross-sectional view of OSFET, Figure 1 (b) shows PMO before annealing
Cross-sectional view of SFET, Figure 1 (c) shows an NMOS after annealing
A cross-sectional view of the FET, FIG. 1D shows the PMOSF after annealing.
It is sectional drawing of ET.

The difference between the complementary MOSFET of the present invention and the CMOSFET formed by the prior art is that the NMOSFET does not have the first sidewall as shown in FIGS. 1 (a) and 1 (b), and The length of shallow junction S / D is NM
Both the OSFET and the PMOSFET have the second sidewall width d ₂ and have substantially equal dimensions.

FIG. 2 shows a complementary MOS showing an embodiment of the present invention.
It is a manufacturing process sectional view of FET (CMOSFET), and the left side shows NMOSFET and the right side shows PMOSFET. Further, the steps up to the step of forming the gate electrode are the same as those in the conventional technique, and thus the description thereof is omitted here. Before explaining the manufacturing method, Liquid Source Chemical
al Vapor Deposition (LSCV
The method D) and the glass precursor resist (GPR) will be described.

LSCVD method [Reference: Hayashi e
t al. : VLSI Symp. Tech. Dig.
(1994) p. 153] is a method of depositing a desired film by atomizing a liquid material by ultrasonic waves and introducing argon (Ar) as a carrier gas into a depressurized (about 500 Torr) chamber. The advantage of this technique is that by dissolving the raw material in an atomizable solvent, even a raw material having a low vapor pressure can be gasified to form a film. Further, in the CVD method, the introduced gas reacts on the substrate to form a thin film, so the introduced gas and the film-formed substance are different, but since the LSCVD method deposits at room temperature, the introduced substance is the same as the thin film. can do.
As a matter of course, the thin film formed by the LSCVD method is
Similar to the thin film formed by the CVD method, there is an advantage that the step coverage becomes good.

[0029]

Embedded image

[0030]

Embedded image

GRP is a silicone resin represented by the above formulas (1) and (2), and a minute amount of acid that decomposes to generate an acid by the action of radiation such as light, electron beam, X-ray, or ion beam. It is a radiation-sensitive resin (resist) composed of an agent and converted into an oxide film (SiO ₂ film) by irradiation with radiation. After irradiating this composition with radiation, a heat treatment is carried out to cause an elimination reaction for cleaving the C—O bond as shown in the following formula (3). Furthermore, Si-O
The H group causes a dehydration reaction with the Si-OH group of another poly (siloxane) to form a Si-O-Si bond. A chain structure is formed by the chain reaction of these reactions to form a SiO ₂ film.

[0032]

Embedded image

The GPR solution contains C--O-- for each monomer.
As a silicone resin composed of poly (siloxane) on a line having a Si bond, 1.0 g of poly (siloxane) represented by the following formula (4) and an acid generator which decomposes by the action of radiation to generate an acid, 10 mg of triphenyltrifluoromethanesulfonate was added to 9.0 m of methyl ethyl ketone (or methyl isobutyl ketone, xylene, etc.).
Dissolve it in 1 and filter it with a 0.2 μm filter to prepare.

[0034]

[Chemical 4]

Hereinafter, a CMOSFE showing an embodiment of the present invention will be described.
A method of manufacturing T will be described with reference to FIGS. 2 and 3. (1) As shown in FIG. 2A, after forming the gate electrode,
Liquid Source Chemical Va
After forming a glass precursor resist (GPR) with a thickness of 50 nm using a por deposition (LSCVD) method, it is baked at 80 ° C. for 1 minute. Normally, GPR is spin coated, so the surface is flattened.
By using the VD method, the GPR film 40 with good step coverage is formed.

(2) Next, as shown in FIG. 2B, a negative type KrF excimer resist film 41 is applied thereon, and then a KrF excimer laser stepper is used to apply light of a wavelength of 249 nm. Excimer resist film 41 and GPR
The laminated film of the film 40 is selectively exposed only in the region of the PMOSFET. Then, the exposed sample is baked at 120 ° C. for 2 minutes to expose the exposed portion of the GPR film 40 to SiO ₂
Convert to membrane 42. Next, the unexposed portion of the excimer resist film 41 is removed with a developing solution. After removing the resist film, the unexposed portion of the GPR film 40 is removed in isoamyl acetate. Rinse with cyclohexane to remove the GPR film which is not the SiO film.

(3) After that, as shown in FIG.
10 KeV of As ₂ by ion implantation into the P well 23a
5 × 10 ¹⁴ cm ^{-2 was} introduced at the shallow junction S of NMOSFET.
/ D43a is formed. At this time, as a matter of course, the resist film 41 serves as a mask for ion implantation. (4) Next, as shown in FIG.
Then, a resist pattern 44 serving as a mask for ion implantation into the PMOSFET is formed. Next, RIE
The SiO ₂ film 42 formed from the GPR film 40 is etched back by using the
It is formed only on the FET.

(5) Next, as shown in FIG. 3A, using the resist pattern 44 as a mask, ions are implanted into the P-well 23b, BF ₂ is introduced at 1 × 10 ¹⁵ cm ^{-2 at} 10 KeV, and PMOSFET is formed. The shallow junction S / D 43b is formed. (6) Next, as shown in FIG. 3B, after removing the resist pattern 44, a 200 nm SiO ₂ film 42 is formed by a CVD method using TEOS, and then RIE is performed.
Etching back is performed to form the second sidewall 46.

(7) Next, as shown in FIG.
NMOSFET deep junction S / D 47a, PMOSFET
The deep junction S / D 47b is formed by ion implantation. N
The deep junction S / D 47a of the MOSFET has As of 20 Ke.
Introduced at 5 × 10 ¹⁵ cm ⁻² at V, the deep junction S / D 47b of the PMOSFET has BF ₂ at 5 × 10 ¹⁵ cm at 10 KeV.
^-2 Introduce and form.

(8) Thereafter, as shown in FIG.
A drive-in is performed using RTA at 1050 ° C. for 10 seconds and then using a furnace at 800 ° C. for 20 minutes to form a CMOSFET having a fine gate length. It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0041]

As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the invention of claim 1, a P-channel MOSFET in which the first and second sidewalls are formed and an N-channel MOSF in which only the second sidewall is formed.
Since the sidewall width of the P-channel MOSFET is made larger than the sidewall of the N-channel MOSFET by the first sidewall width, the width of the junction of the shallow junction source / drain of the NMOSFET is increased. This can be made appropriate, the parasitic resistance can be reduced, and the operating speed can be increased.

(2) According to the invention of claim 2, GP
Since the R film is used, PMOSFE
The SiO ₂ film to be the first sidewall film can be formed only in the T region, and as shown in FIG. 1, the shallow junction S /
The length of D is NMOSFET, PM before and after drive-in.
The OSFETs have almost the same second sidewall width, the shallow junction S / D has a long length only in the NMOSFET, and the operating speed is not reduced due to the influence of parasitic resistance.

Further, after the ion implantation of the shallow junction S / D is performed, the etching back of the first sidewall in the region is not performed, so that the S / D of the shallow junction is cut off under the second sidewall, or It is possible to prevent the S / D concentration of the shallow junction from decreasing and becoming high resistance. Further, although the GPR film of the radiation-sensitive resist is used, the batch exposure is performed by forming a laminated structure with the resist for the excimer. Therefore, there is no increase in the photolithography process. There is also the advantage that there is no difference.

(3) According to the invention of claim 3, the glass precursor resist solution is used in the LSCVD method.
Since it is dissolved in the atomizable solvent, it is possible to gasify even a raw material having a low vapor pressure to form a film. Also, C
In the VD method, the gas to be introduced reacts on the substrate to form a thin film, so the gas to be introduced and the film-formed substance are different, but in the LSCVD method, since the material is deposited at room temperature, the substance to be introduced should be a thin film as it is. You can

The thin film formed by the LSCVD method is
The step coverage becomes good like the thin film formed by the CVD method.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a CMOSFET showing an embodiment of the present invention.

FIG. 2 is a sectional view (No. 1) of a manufacturing process of the CMOSFET showing the embodiment of the present invention.

FIG. 3 is a cross-sectional view (No. 2) of the manufacturing process of the CMOSFET showing the embodiment of the present invention.

FIG. 4 is a cross-sectional view of a conventional CMOSFET.

FIG. 5 is a cross-sectional view (1) of a manufacturing process of a conventional CMOSFET.

FIG. 6 is a manufacturing process sectional view of a conventional CMOSFET (No. 2).

FIG. 7 is a diagram illustrating a problem of a conventional CMOSFET.

[Explanation of symbols]

21 Silicon Substrate 22 Recessed LOCOS 23a P Well 23b N Well 25 Oxide Film 26 Polysilicon Film 27 Silicon Nitride Film 40 GPR Film 41 KrF Eximer Resist Film 42 SiO ₂ Film 43a NMOSFET Shallow Junction S / D 43b PMOSFET Shallow Junction S / D 44 Resist pattern 45 First sidewall 46 Second sidewall 47a, 47b Deep junction S / D

Claims (3)

[Claims] 1. In a complementary MOSFET, (a) a P channel MO in which first and second sidewalls are formed.
SFET and (b) an N-channel MOSFET in which only the second sidewall is formed, and (c) a sidewall width of the P-channel MOSFET is larger than a sidewall width of the N-channel MOSFET as a first sidewall width. Complementary MO characterized by increasing by the amount
SFET. 2. A method of manufacturing a complementary MOSFET, comprising: (a) patterning a gate electrode;
(B) A step of atomizing a glass precursor resist solution by the LSCVD method and then applying the solution on a substrate, and then spin-coating a negative resist, and (c) then radiating radiant light to form a P channel. After exposing the resist in the MOSFET region and the glass precursor resist film, they are heated to convert the glass precursor resist film into a silicon oxide film,
On the other hand, a step of developing and removing the resist in the N-channel MOSFET region and the glass precursor resist film,
(D) a step of performing ion implantation for forming a source / drain of a shallow junction of the N-channel MOSFET,
(E) a step of removing the resist on the glass precursor resist film, masking the N-channel MOSFET region with the resist, and performing etchback by reactive ion etching to form a first sidewall;
(F) a step of performing ion implantation for forming a source / drain of a shallow junction of the P-channel MOSFET, and a method for manufacturing a complementary MOSFET. 3. The method of manufacturing a complementary MOSFET according to claim 2, wherein the glass precursor resist solution is L.
A method of manufacturing a complementary MOSFET, characterized by being dissolved in an atomizable solvent in the SCVD method.