JPH0836442A - Reset circuit - Google Patents

Abstract

PURPOSE:To provide a reset circuit, which generates a reset signal not affected by chattering caused by operating a reset switch, without increasing the cost. CONSTITUTION:When a reset switch 4 is opened for the purpose of releasing a body to be controlled from the reset, a first capacitor 2 repeats charging and discharging based on chattering of the reset switch 4, and a second capacitor 6 repeats charging and discharging also in accordance with this charging and discharging of the capacitor 2. However, the terminal voltage of the second capacitor 6 doesn't reach a lower threshold voltage Vth1 of a Schmitt inverter 2, and consequently, a sure reset signal RST is generated from the Schmitt inverter 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a reset circuit,
In particular, the present invention relates to a reset circuit that can perform an initial reset when the power is turned on and a forced reset based on the operation of a reset switch.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a conventional reset circuit. In FIG. 4, (1) is a resistor and (2) is a capacitor, which are connected in series between the power supply Vdd and the ground. When the power supply Vdd is turned on, the capacitor (2) is charged according to the time constant determined by the resistance value of the resistor (1) and the capacitance of the capacitor (2). (3) is two different threshold voltages Vthh and Vthl (Vth
Schmitt inverter having h> Vthl), that is, having a hysteresis. The resistor (1), the capacitor (2), and the Schmitt inverter (3) described above are built in, for example, an integrated circuit such as a microcomputer, and a reset signal output from the Schmitt inverter (3) causes the internal circuit of the microcomputer or the like to be changed. The operation of the controlled object is reset. Specifically, when the power supply Vdd is turned on and rises, the terminal voltage of the capacitor (2) gradually rises according to the time constant. Threshold voltage Vt on the side where the terminal voltage of this capacitor (2) is high
Until reaching hh, the output of the Schmitt inverter (3), that is, the reset signal is at a high level, and the controlled object is initialized by the reset signal at the high level. After that, when the terminal voltage of the capacitor (2) exceeds the threshold voltage Vthh on the high side, the reset signal becomes low level, and the controlled object is released from reset. The reason for using the Schmitt inverter (3) is as follows. That is, since the terminal voltage of the capacitor (2) rises relatively gently in accordance with the time constant, an ordinary inverter having only one threshold voltage responds to a slight fluctuation of the terminal voltage of the capacitor (2). This is because a reliable reset signal cannot be generated.

Further, (4) is a mechanical reset switch connected between the connection point of the resistor (1) and the capacitor (2) and the ground, and, of course, is connected to the outside of the integrated circuit and used by the user. It is opened or closed based on the will. The operation of the controlled object can be reset only while the reset switch (4) is closed. However, the reset operation based on the operation of the reset switch (4) has the following problems.

[0004]

The operation of generating a reset signal by closing the reset switch (4) while the power source Vdd is rising will be described below with reference to the waveform diagram of FIG. It demonstrates using. First, time t0
When the reset switch (4) is closed, the terminal voltage a of the capacitor (2) is instantly discharged to 0 volt, and the output RST of the Schmitt inverter (3) rises instantaneously to operate the controlled object. Resets. Then, at time t1, when the reset switch (4) is opened to release the reset of the controlled object, ideally the capacitor (2) should be charged according to the time constant and be in a fully charged state. However, due to the structure of the reset switch (4), even if the reset switch (4) is opened, chattering that repeats closing and opening occurs for a short time. Therefore, the capacitor (2) is repeatedly charged and discharged according to the opening and closing of the reset switch (4), and the Schmitt inverter (3) only during the period when the terminal voltage a of the capacitor (2) exceeds the high side threshold voltage Vthh. There is a problem that an unstable reset signal in which the output RST becomes low level is applied to the controlled object, and the microcomputer or the like cannot be reliably reset. In order to prevent an unstable reset operation based on the chattering, the resistance value of the resistor (1) and the capacitance of the capacitor (2) are increased to increase the time constant, and the charging voltage of the capacitor (2) is high. The threshold voltage Vthh on the side should not be reached, but if this is done, the capacitor (2) cannot be integrated and must be externally connected to the integrated circuit, resulting in an increase in the cost of the reset circuit. There was a problem.

Therefore, an object of the present invention is to provide a reset circuit which can generate a reset signal which is not affected by chattering generated when a reset switch is operated without increasing the cost.

[0006]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it is charged with a first time constant by a power supply voltage and the charging voltage is A first charging / discharging circuit that discharges through a discharge path formed when the reset switch is closed; and, when the reset switch is opened, the power supply voltage charges the battery with a second time constant to reset the reset voltage. When the switch is closed, a second charge / discharge circuit that discharges with a third time constant is connected to the first and second charge / discharge circuits when the reset switch is opened, When the reset switch is closed, the connection circuit that shuts off the first and second charge / discharge circuits and the output of the second charge / discharge circuit are applied, and a reset signal for the controlled object is applied. Equipped with an output inverter circuit Initially resetting the controlled body when the power supply voltage is turned on with the reset switch opened, and resetting the controlled body only during the period when the reset switch is closed from the state in which the power supply voltage is applied. However, a reset signal that is not affected by chattering generated by operating the reset switch is generated.

[0007]

According to the present invention, when the reset switch is opened to release the controlled body from the reset state, the first charging / discharging circuit repeats charging / discharging based on the chattering of the reset switch. The charge and discharge circuit of is also repeatedly charged and discharged. However, the terminal voltage of the second capacitor forming the second charge / discharge circuit does not reach the threshold voltage of the inverter circuit, and therefore the inverter circuit can generate a reliable reset signal.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a reset circuit of the present invention. still,
In FIG. 1, the same elements as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted. Also, the first resistor (1)
The first capacitor (2) constitutes a first charge / discharge circuit, and the Schmitt inverter (3) corresponds to an inverter circuit.

In FIG. 1, (5) is a diode (connection circuit), the anode of which is connected to the connection point of the first resistor (1) and the first capacitor (2). (6) is a second capacitor, which is connected between the cathode of the diode (5) and the ground. (7) is a second resistor, which is connected in parallel with the second capacitor (6).
Here, the second capacitor (6) and the second resistor (7)
The second charging / discharging circuit is configured. Also, the first time constant is determined based on the resistance value of the first resistor (1) and the capacitance of the first capacitor (2), and the resistance value of the first resistor (1) and the second capacitor (6 ), The second time constant is determined, and further, the resistance value of the second resistor (7) and the capacitance of the second capacitor (6) determine the third time constant. The second resistor (7) has a larger resistance value than the first resistor (1), and the second capacitor (6) has a larger capacitance than the first capacitor (2). Is small.

The operation of FIG. 1 will be individually described below for the case of an initial reset when the power is turned on and a forced reset when the reset switch (4) is closed. First, a case where the controlled object is initially reset will be described with reference to the waveform diagram of FIG. First, at time t0, when the power supply Vdd is turned on with the reset switch (4) opened, the first capacitor (2) starts charging with the first time constant, and the first capacitor (2) starts charging. The terminal voltage A of the capacitor (2) gradually rises and stabilizes at a constant voltage (specifically, a value obtained by subtracting the voltage across the first resistor (1) from the power supply Vdd). At the same time, the second capacitor (6) starts charging with the second time constant, and the terminal voltage B of the second capacitor (6)
Gradually rises and stabilizes at a constant voltage. The terminal voltage B of the second capacitor (6) is the same as that of the first capacitor (2).
Can only rise to a value obtained by further subtracting the forward voltage of the diode (5) from the terminal voltage A of. Therefore, the power supply voltage V
In the steady state after the addition of dd, the diode (5) is in a conducting state. And the second capacitor (6)
Is applied to the Schmitt inverter (3), the reset signal RST output from the Schmitt inverter (3) becomes high level at time t0, and the second capacitor (6) The terminal voltage B becomes low level at time t1 when it exceeds the high side threshold voltage Vthh. That is, the controlled object such as a microcomputer is initially reset only during a period from time t0 to time t1.

Next, the case where the reset switch (4) is closed to forcibly reset the controlled object will be described with reference to FIG. First, at time T0, the power supply Vdd
When the reset switch (4) is closed from the state in which is applied, the terminal voltage A of the first capacitor (2) is instantaneously discharged through the closed circuit of the reset switch (4),
Fall sharply. At this time, since the anode of the diode (5) drops to 0 volt, the diode (5) is turned off and the points A and B are cut off. Then, the terminal voltage B of the second capacitor (6) is discharged with the third time constant through the second resistor (7) and gradually drops. And
At time T1, when the terminal voltage B of the second capacitor (6) reaches the lower threshold voltage Vthl of the Schmitt inverter (3), the reset signal RST output from the Schmitt inverter (3) is at a high level. Becomes After that, at time T2, when the reset switch (4) is opened in an attempt to cancel the reset of the controlled object, the first capacitor (2) starts charging again with the first time constant. Ideally, the first capacitor (2) should be continuously charged until it is fully charged. However, due to the mechanical structure of the reset switch (4), it is assumed that the reset switch (4) is opened. However, so-called chattering that repeats closing and opening occurs only for a short time thereafter. Therefore, the first capacitor (2) repeats charging and discharging after time T2. This point will be described in detail below.

At time T2, when the first capacitor (2) starts charging with the first time constant, the second capacitor (6) also restarts charging with the second time constant. Time T
In 3, when the terminal voltage B of the second capacitor (6) reaches the high side threshold voltage Vthh of the Schmitt inverter (3), the Schmitt inverter (3)
The reset signal RST output from the output terminal falls to the low level. Now, as described above, the reason why the capacitance of the second capacitor (6) is made small and the resistance value of the second resistor (7) is made large is that the terminal voltage B of the second capacitor (6) is at the time of charging. This is because the upper limit value is quickly reached, and it is difficult to reach the low threshold voltage Vthl of the Schmitt inverter (3) even if discharging is performed. After that, time T4
At this time, when the first capacitor (2) discharges instantaneously based on the chattering of the reset switch (4), the second capacitor (6) discharges with the third time constant. Here, since the resistance value of the second resistor (7) is large, the discharging operation of the second capacitor (6) is performed gently and never falls to the threshold voltage Vthl on the low side of the Schmitt inverter (3). There is no such thing. Even at times T5 and T6, the first and second capacitors (2) and (6) are repeatedly charged and discharged based on chattering. However, similarly to the above description, the terminal voltage of the second capacitor (6). B never reaches the low side threshold voltage Vthl of the Schmitt inverter (3). Then, at time T7, when the chattering settles down, the first and second capacitors (2) and (6) are charged together, and the respective terminal voltages A and B become stable at a constant voltage. From the above,
Even if chattering occurs when the reset switch (4) is opened from the closed state, the reset signal RST can be reliably generated from the time T1 to T3, and the controlled object can be surely forcibly reset. In addition, in the applied state of the power source Vdd,
Since the diode (5) is always in the conducting state, current always flows in the series path of the first resistor (1), the diode (5) and the second resistor (7),
Since the resistance value of the resistor (7) is set to be large, the current consumption can be suppressed. Further, it is not necessary to unnecessarily increase the capacities of the first and second capacitors (2) and (6), and these capacitors can be incorporated in the integrated circuit together with the reset circuit.

[0013]

According to the present invention, it is possible to reliably generate a reset signal that is not affected by chattering generated by operating the reset switch. In addition, since the capacitance of the capacitors forming the first and second charge / discharge circuits can be small, these capacitors can be incorporated in the integrated circuit together with the reset circuit, and advantages such as a cost reduction can be obtained. .

[Brief description of drawings]

FIG. 1 is a diagram showing a reset circuit of the present invention.

FIG. 2 is a waveform diagram showing the initial reset operation of FIG.

FIG. 3 is a waveform diagram showing the forced reset operation of FIG.

FIG. 4 is a diagram showing a conventional reset circuit.

FIG. 5 is a waveform diagram showing the reset operation of FIG.

[Explanation of symbols]

 (1) First resistance (2) First capacitor (3) Schmidt inverter (4) Reset switch (5) Diode (6) Second capacitor (7) Second resistance

Claims (3)

[Claims] 1. A first charging / discharging circuit, which is charged with a first time constant by a power supply voltage and discharges the charging voltage through a discharge path formed when a reset switch is closed, and the reset switch is opened. The second time constant is charged by the power supply voltage when the reset switch is closed, and the second time constant is discharged when the reset switch is closed.
Charging / discharging circuit and the first and second charging / discharging circuits are connected when the reset switch is opened, and the first and second charging / discharging circuits are connected when the reset switch is closed. A connection circuit for shutting off the circuit; and an inverter circuit to which the output of the second charge / discharge circuit is applied and which outputs a reset signal for the controlled object, wherein the reset switch is opened. The controlled body is initially reset when the power supply voltage is turned on, and the controlled body is reset only during the period when the reset switch is closed from the state in which the power supply voltage is applied, and the influence of chattering caused by the operation of the reset switch. A reset circuit characterized by generating a reset signal that does not receive the reset signal. 2. The first charging / discharging circuit includes a first resistor and a first capacitor, and the second charging / discharging circuit is a second capacitor.
And a second capacitor, the second resistor having a resistance value larger than that of the first resistor, and the second capacitor having a capacitance smaller than that of the first capacitor. The reset circuit according to claim 1, wherein: 3. The first time constant is determined by the resistance value of the first resistor and the capacitance of the first capacitor, and the second time constant is the resistance value of the first resistor and the second resistor. Is determined by the capacitance of the capacitor, and the third time constant is the second time constant.
3. The reset circuit according to claim 2, wherein the reset circuit is determined by the resistance value of the resistor and the capacitance of the second capacitor.