JPH084130B2 - Photoelectric conversion device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a photoelectric conversion device of a type in which carriers excited by light are accumulated in a control electrode region of a transistor, and particularly, the potential of the control electrode region is constant. The present invention relates to a photoelectric conversion device having switch means for setting a value.

[Prior Art] FIG. 7 (A) is a schematic plan view of the photoelectric conversion device described in Japanese Patent Application No. 58-120755, and FIG. 7 (B) is its AA 'and FIG. (C) is an equivalent circuit diagram thereof.

In each figure, photoelectric conversion cells are arranged on an n-silicon substrate 101, and each cell is electrically insulated from an adjacent cell by an element isolation region 102 made of SiO ₂ , Si ₃ N ₄ , or polysilicon. ing.

 Each cell has the following configuration.

Low impurity concentration formed by epitaxial technology
A p base region 104 and ap region 105 are formed on the n ⁻ region 103 by doping a p type impurity (for example, boron), and an n ⁺ emitter region 106 is formed in the p base region 104.

The p base region 104 and the p region 105 are the p channel described later.
It also serves as the source and drain of the MOS transistor.

An oxide film 107 is formed on the n ⁻ region 103 in which each region is formed in this way, and a gate electrode 108 of the MOS transistor and a capacitor electrode 109 are formed on the oxide film 107. The capacitor electrode 109 faces the p base region 104 with the oxide film 107 in between, and constitutes a capacitor for controlling the base potential.

In addition, the emitter electrode 110 connected to the n ⁺ emitter region 106, the electrode 111 connected to the p region 105, and the substrate 101.
Collector electrode with an ohmic contact layer on the back side of the
112 are formed respectively.

 Next, the operation of the photoelectric conversion cell will be described.

Light enters from the p base region 104 side, and carriers (here, holes) corresponding to the amount of light are accumulated in the p base region 104 (accumulation operation).

The base potential changes due to the accumulated carriers, and by reading the potential change from the emitter electrode 110, an electric signal corresponding to the amount of incident light can be obtained (reading operation).

Next, a refresh operation for removing holes accumulated in the p base region 104 will be described.

FIGS. 8A and 8B are voltage waveform diagrams for explaining the refresh operation.

As shown in FIG. 7A, the MOS transistor is turned on only when a negative voltage above the threshold is applied to the gate electrode 108.
N state.

To perform the refresh operation in FIG.
The emitter electrode 110 is grounded and the electrode 111 is kept at ground potential. Then, first, a negative voltage is applied to the gate electrode 108 to turn on the p-channel MOS transistor. As a result, the potential of the p base region 104 becomes a constant value regardless of the level of the accumulated potential. Then, by turning off the MOS transistor and applying a refreshing positive voltage pulse to the capacitor electrode 109, the p base region 104 is forward biased with respect to the n ⁺ emitter region 106, and the accumulated holes are grounded. Removed through the formed emitter electrode 110. Then, when the refresh pulse to the capacitor electrode 109 falls, the p base region 104 returns to the initial state of negative potential (refresh operation).

In this way, after the potential of the p base region 104 is set to a constant potential by the MOS transistor, a refresh pulse is applied to erase the residual charge, so that a new storage operation is started without depending on the previous storage voltage. It is possible to improve the photoelectric conversion characteristics and the afterimage characteristics. In addition, the residual charge can be quickly extinguished, and high-speed operation becomes possible.

[Problems to be Solved by the Invention] However, in the above-described conventional photoelectric conversion device, as shown in FIG. 7 (A), since the refresh transistor is formed on the light-receiving surface, the cell size is reduced accordingly. This has been a problem in achieving high integration and high resolution, especially when an area sensor is constructed.

The present invention is intended to solve the above conventional problems, and an object of the present invention is to provide a photoelectric conversion device which can obtain good photoelectric conversion characteristics and afterimage characteristics without increasing the cell size.

[Means for Solving Problems] A photoelectric conversion device according to the present invention comprises a first conductivity type semiconductor for forming a control electrode region, a first region for accumulating carriers generated by photoexcitation, and Second and third semiconductors of opposite conductivity type for forming main electrode regions arranged so as to sandwich the first region above and below, respectively.
And a fourth region formed under the third region and formed of one conductivity type semiconductor, and the first region and the fourth region as main electrode regions. And an insulated gate electrode for controlling the region 3.

[Operation] With this configuration, a transistor controlled by an insulated gate electrode can be formed in the vertical direction using the first region and the fourth region as main electrode regions, and the size of the photoelectric conversion device can be increased. Can be miniaturized.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic sectional view of a first embodiment of a photoelectric conversion device according to the present invention.

In the figure, an n ⁺ buried layer 202 and an n ⁻ collector region 203 are formed on a p-type silicon substrate 201, and each cell is electrically isolated from an adjacent cell by an element isolation region 204.

The element isolation region 204 is composed of an oxide film 205 and a capacitor electrode 206 made of polysilicon. As an example of the method of forming the element isolation region 204, first, on the p substrate 201,
After epitaxially growing the n ⁺ buried layer 202 and the n ⁻ region to be the collector region 203, a groove is formed in a portion where the element isolation region 204 is to be formed by anisotropic etching or the like.
Then, an oxide film 205 is formed in the groove by thermal oxidation, and then polysilicon is embedded to form a capacitor electrode 206.

The bipolar transistor in each cell has an n ^- collector region
It is composed of a p base region 207 on 203 and an n ⁺ emitter region 208.

The p ⁺ region 209 is joined to the p base region 207 to form the p ⁺ region 209.
Forms a capacitor Cox for controlling the potential of the p base region 207, facing the capacitor electrode 206 with the oxide film 205 interposed therebetween.

Further, the lower p ⁺ region 209 has not been n ⁺ buried layer 202 is formed, the p ⁺ region 209 and the p substrate 201 is formed at a distance of about 4 to 5 [mu] m, the source of the refresh transistor Qt
It constitutes the drain region. The gate electrode of the transistor Qt is the capacitor electrode 2 formed by sandwiching the oxide film 205.
It is 06.

Further, the n ⁺ region 210 is joined to the n ⁻ collector region 203, and n ⁺
A collector electrode 210 '(not shown) is connected to the region 210.

An oxide film 211 is formed on the surface of each cell, and an emitter electrode 212 is connected to the n ⁺ emitter region 208. Also,
An electrode 213 is formed on the back surface of the p substrate 201 via an ohmic contact layer.

In this way, since the refresh transistor Qt is formed in the vertical direction with respect to the light receiving surface, it is possible to avoid an increase in cell size.

Further, since each cell is separated by the element isolation region 204 and the n collector region 203 is formed on the p substrate 201, the element isolation effect can be improved.

Further, even if strong light is incident, excess carriers accumulated in the p base region 207 are removed through the p substrate 201, so that outflow to adjacent cells can be prevented, and smear and blooming can be prevented. .

FIG. 2 is a schematic sectional view of a second embodiment of the present invention. Although the structure is almost the same as that of the first embodiment, the upper portion of the capacitor electrode 206 extends above the p base region 207 to increase the capacitance.

FIG. 3 is an equivalent circuit diagram of one cell in the above embodiment.

The basic operation of the above embodiment is the same as that of the conventional example. First, a positive voltage is applied to the collector electrode 210 'and a constant voltage is applied to the electrode 213. Then, a ground voltage is applied to the capacitor electrode 206 to turn off the transistor Qt to bring the p base region 207 into a floating state. Then, carriers corresponding to the illuminance of incident light are accumulated in this p base region 207 (accumulation operation).

Subsequently, the emitter electrode 212 is brought into a floating state, and a positive voltage read pulse is applied to the capacitor electrode 206. At this time, the transistor Qt remains in the OFF state because it is a p-channel. By applying the read pulse,
The potential of the p base region 207 rises via the capacitor Cox, and the accumulated voltage is read to the floating emitter side (read operation).

Next, in order to erase the carriers accumulated in the p base region 207, first, a negative voltage pulse is applied to the capacitor electrode 206 to turn on the refresh transistor Qt. As a result, the p base region 207 is set to a constant voltage applied to the electrode 213 regardless of the level of the accumulated voltage due to the intensity of the incident light. Then, by applying a positive voltage refresh pulse to the capacitor electrode 206 and grounding the emitter electrode 212, the carriers remaining in the p base region 207 are removed to the grounded emitter side (refresh operation).

In this way, the p base region 207 is returned to the initial state, and thereafter, the accumulating, reading and refreshing operations are repeated in the same manner.

FIG. 4 is a circuit diagram of an embodiment of an area sensor using the photoelectric conversion cell.

In this embodiment, the photoelectric conversion cells S are arranged in m × n areas.

A constant positive voltage Vcc is applied to each collector electrode 210 ′ of the photoelectric conversion cell S, and a constant voltage Vrc is applied to each electrode 213.

The capacitor electrodes 206 of the cells S are commonly connected for each row, and the pulses φ _{1 to} φm for performing the read operation and the refresh operation are applied thereto. Also, each emitter electrode 212 are respectively connected to the vertical line L ₁ Ln for each column, the vertical line L ₁ Ln are connected respectively to the storage capacitor C ₁ to Cn.

The capacitors C _{1 to} Cn are connected to the output line 301 via the transistors Q _{1 to} Qn, respectively. Transistor Q
The gate electrodes of _{1 to} Qn are respectively connected to the parallel output terminals of the scanning circuit 302, and the pulses φh _{1 to} φhn are sequentially output from the parallel output terminals.

The output line 301 is grounded via the transistor Qrh for refreshing, and the pulse φr ₂ is applied to the gate electrode of the transistor Qrh. Further, the output line 301 is connected to the input terminal of the output amplifier 303, and the output signal Vout is output to the outside from the output terminal of the output amplifier 303.

The vertical lines L _{1 to} Ln are connected to the transistors Qr _{1 to} Qrn, respectively.
Grounded through. A pulse φr ₁ is applied to the gate electrode of each transistor.

FIG. 5 is a timing chart for explaining the operation of the area sensor.

First, it is assumed that the cells S _{11 to} S ₁ n in the first row start the accumulation operation and a certain time has elapsed.

In the figure, the low-level pulse φr ₁ turns off the transistors Qr _{1 to} Qrn and puts the vertical lines L _{1 to} Ln into a floating state. Then, a read pulse is applied to the capacitor electrode 206 of the first row by the high level pulse φ ₁ . As a result, the read signals of the cells S _{11 to} S ₁ n in the _first row are stored in the capacitors C _{1 to} Cn. Then, the scanning circuit 30
2 outputs pulses φh _{1 to} φhn, and transistors Q _{1 to} Q
The read signals of the first row accumulated in the capacitors C _{1 to} Cn are sequentially taken out to the output line 301 as n sequentially turns on,
Output from the output amplifier 303 to the outside. However, the transistors Qr each time it is output to the outside, by a pulse [phi] r ₂
The h is turned on, and the residual charge on the output line 301 is cleared.

When all the read signals of the first row are output, the pulse φ
The transistors Qr _{1 to} Qrn are turned on by r ₁ and the vertical lines L _{1 to} Ln are grounded. As a result, the emitter electrode 212 of each cell is grounded and the capacitors C _{1 to} Cn
The residual charge of is cleared.

Then, a negative voltage is first applied to the capacitor electrode 206 by the pulse φ ₁ , and the base potential of the cells S _{11 to} S ₁ n in the first row is set to the constant potential Vrc regardless of the storage voltage. Then, a positive voltage refresh pulse is applied to the capacitor electrode 206.
To eliminate the carriers in the base as described above.

When the read and refresh operations are completed in this way, the cells S _{11 to} S ₁ n in the first row start the accumulation operation. At the same time, the cells S _{21 to} S ₂ n in the second row perform the read operation by the pulse φ ₂ , and after the subsequent read signal output operation, the similar refresh operation is performed to start the storage operation.

Similarly, the same applies to the third row to the m-th row by the pulses φ _{3 to} φm.
The same operation is sequentially repeated up to the row, and the read signals of all cells are serially output from the output amplifier 303 to the outside. Moreover, in each row, since the refresh operation is performed after the read signal is output to the outside to start the accumulation operation, the accumulation time becomes the same in each row.

FIG. 6 is a schematic configuration diagram of an example of an imaging device using the photoelectric conversion device.

In the figure, the image pickup device 401 corresponds to the photoelectric conversion device shown in FIG. The output signal Vout of the image pickup device 401 is subjected to processing such as gain adjustment by the signal processing circuit 402,
It is output as a standard television signal such as a signal.

Further, each pulse for driving the image sensor 401 is supplied by the driver 403, and the driver 403 controls the controller 40.
Operates under the control of 4. The control unit 404 is an image sensor.
Based on the output of 401, the gain of the signal processing circuit 402 and the like are adjusted, and the exposure control means 405 is controlled to adjust the amount of light incident on the image sensor 401.

As described above, in this embodiment, since good photoelectric conversion characteristics and afterimage characteristics can be obtained without increasing the cell size, a high-resolution image sensor 401 can be configured, and a high-quality image signal without afterimage can be obtained. be able to.

[Effects of the Invention] As described in detail above, in the photoelectric conversion device according to the present invention, a transistor controlled by an insulated gate electrode is formed in the vertical direction using the first region and the fourth region as main electrode regions. Therefore, the good photoelectric conversion characteristics and the afterimage characteristics described above can be obtained without increasing the size of the photoelectric conversion cell.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a first embodiment of a photoelectric conversion device according to the present invention, FIG. 2 is a schematic sectional view of a second embodiment of the present invention, and FIG. FIG. 4 is an equivalent circuit diagram of the cell, FIG. 4 is a circuit diagram of an embodiment of an area sensor using the photoelectric conversion cell, FIG. 5 is a timing chart for explaining the operation of the area sensor, and FIG. FIG. 7 (A) is a schematic plan view of a photoelectric conversion device described in Japanese Patent Application No. 58-120755, FIG. 7 is a schematic configuration diagram of an example of an image pickup device using the photoelectric conversion device. (B) is the A
FIG. 7C is an equivalent circuit diagram thereof, and FIGS. 8A and 8B are voltage waveform diagrams for explaining the refresh operation. 201 …… p-type silicon substrate 203 …… n ^- collector region 204 …… element isolation region 205 …… oxide film 206 …… capacitor electrode 207 …… p base region 208 …… n ⁺ emitter region 209 …… p ⁺ region 210 ...... n ⁺ region 210 '…… collector electrode 212 …… emitter electrode 213 …… electrode 301 …… output line 302 …… scanning circuit 303 …… output amplifier

Claims (3)

[Claims] 1. A first region made of one conductive type semiconductor for forming a control electrode region, the first region for accumulating carriers generated by photoexcitation, and the first region arranged so as to sandwich the first region above and below, respectively. A semiconductor transistor formed of second and third regions of opposite conductivity type semiconductor for forming a main electrode region; a fourth region of one conductivity type semiconductor provided under the third region; An insulated gate electrode for controlling the third region such that the first region and the fourth region are main electrode regions, and a photoelectric conversion device. 2. The photoelectric conversion device according to claim 1, wherein the insulated gate electrode can control the potential of the first region through an insulating layer. 3. The photoelectric conversion device according to claim 2, wherein the gate electrode is formed in an element isolation region for electrically isolating the semiconductor transistor from other adjacent portions. Converter.