JPH0863977A - Semiconductor memory device and reading method - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor memory device and a reading method in which a reading operation is speeded up. [Configuration] A plurality of columns of bit lines forming a differential pair are arranged in parallel, and a plurality of memory cells are arranged in parallel for each column.
When performing reading in a semiconductor memory device that selects one memory cell from a plurality of memory cells by a row selection signal and selects one column from a plurality of bit line columns by a column selection signal and outputs data, level shift means Shifts the potentials of the bit lines B and / B forming a differential pair to a predetermined reference voltage V _S between the high power supply potential V _DD and the low side power supply potential GND, prior to the selection of the memory cell 1. The output means 3 and 4 may be the reference voltage V _S or the reference voltage V _S depending on the selection of the memory cell 1.
A difference in voltage amplitude or current amplitude between bit lines that changes symmetrically with respect to the reference current I _C corresponding to _S is detected and output. As a result, the speed can be increased to about twice that of the conventional one.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a so-called SRAM (St
atic Random Access Memory), and more particularly, to a circuit configuration of an SRAM having bit lines that operate as a differential pair.

With the recent demand for larger memory capacity,
Even in the technical field of SRAM, the number of memory cells arranged in parallel in a pair of bit lines is dramatically increasing. Therefore, the load capacitance per bit line becomes large, and a circuit configuration for speeding up the read operation is required. In order to perform high-speed reading in an element such as SRAM, it is necessary to obtain the amplitude of the bit line at the time of reading earlier, increase the current difference of the read current in the current sense method, and the like.

[0003]

2. Description of the Related Art SRAMs use memory cells consisting of flip-flops for holding data and include bipolar memories, NMOS memories, CMOS memories and the like. Particularly, a CMOS memory is preferable because it consumes less current. The basic structure of the SRAM is composed of a row and column address buffer, a row and column decoder, a sense amplifier, a data buffer, a control circuit, a timing circuit, etc., centering on a memory cell array provided with a large number of memory cells.

FIG. 5A shows, as a first example, a circuit of a memory cell array and its reading portion in the internal structure of the conventional semiconductor memory device (SRAM). As shown in FIG. 5A, in the first example of the conventional SRAM, a column of a plurality of differential pairs of bit lines B and / B ('/' indicates a negative logic signal) is provided in the memory cell array 15. It is provided. A plurality of memory cells are connected to each column.

The operation of the first example of the conventional semiconductor memory device is
Taking the column of the memory cells 10 as an example, description will be made with reference to the timing chart of FIG. When the word line W which is a row selection signal becomes H level (FIG. 5B), the memory cell 10 is selected. Amplitude b is generated in the voltage state on the bit lines B and / B in accordance with the stored contents held in the memory cell 10 (the same figure). When the bit line is selected by the column switch 12, the level shift circuit 13 lowers the reference potential of the bit lines B and / B by a predetermined voltage, and outputs the signal of the bit lines CB and / CB after the level shift. (The same figure). The sense amplifier 14 amplifies the voltage amplitude.

FIG. 6A shows a conventional semiconductor memory device (S
The partial circuit of the 2nd example of RAM) is shown. As shown in FIG. 6A, in the second example of the conventional semiconductor recording device, the level shift circuits 22, 2 are provided between the memory cell array 26 provided with the memory cells 20, 21, ... And the column switch 24.
3, ... are provided.

The operation of the second example of the conventional semiconductor memory device will be described below.
Taking the column of memory cells 20 as an example, description will be made with reference to the timing chart of FIG. In this circuit, the level shift circuit 22 operates by the control signal of the level shift switch line A before the word line W is selected (FIG. 6).
(B)). The level shift circuit 22 includes bit lines B, /
The level of B is changed from the power supply voltage V _DD to a predetermined voltage V _LS (see FIG. 6).
In (A), a shift is made by an amount corresponding to the total value of threshold voltages of p-channel transistors Q _{40 to} Q ₄₂ stacked in three stages (the same figure). Next, when the word line W is selected (FIG. 6 (B)), an amplitude is generated in the bit lines B and / B from the reference potential at the subsequent stage of the level shift circuit 22, so that the level shift circuit 13 of the first example is changed. It eliminates the need for such a circuit. Therefore, amplitude is generated in the level-shifted bit lines CB and / CB without delay from the signal states of the bit lines B and / B (FIG. 8).

An invention using such a memory cell is described in Japanese Patent Application Laid-Open No. 61-26994.

[0009]

However, in the above conventional semiconductor memory device, the read operation cannot be sufficiently speeded up. In other words, in order to speed up the read operation, it is necessary to transmit the amplitude generated on the bit line to the sense amplifier at high speed, but it takes time for the sense amplifier to detect a constant level amplitude value between the bit lines. Therefore, the whole reading time cannot be shortened.

In the first example of the conventional semiconductor memory device shown in FIG. 5, a delay occurs in the rising of the amplitude of the bit lines CB and / CB after the level shift due to the load capacitance of the level shift circuit 13 and the like (FIG. 5). (B)). However, since the time during which the word line W and the bit line are selected by the column switch 12 is limited, the selection of the word line W ends before a sufficient amplitude b ′ is obtained.

Further, in the second example of the conventional semiconductor memory device shown in FIG. 6, even if the position where the level shift circuit 22 or the like is inserted is changed, the time constant itself of the amplitude generated in the bit lines B and / B is not changed. There is no change. Therefore, although the effect of eliminating the delay in the amplitude after the level shift is achieved, the speed of increasing the amplitude of the bit line (for example, the inclination angles of / B and / CB in FIG. 6B) is the same as in the first embodiment. However, since there is no change in the time required to obtain a predetermined amplitude difference, it has not been a fundamental solution to speeding up the read operation.

Therefore, an object of the present invention is to provide a semiconductor memory device and a read method in which the read operation is speeded up.

[0013]

To achieve the above object, it is sufficient to shorten the time until a constant amplitude value is generated on the bit line after the memory cell is selected by the word line. That is, if the respective voltage amplitudes or current amplitudes of the bit lines forming a differential pair produce a symmetrical change around a predetermined reference voltage, a large amplitude can be obtained in a short time.

Therefore, the invention according to claim 1 is a method of reading a semiconductor memory device, wherein a plurality of columns of bit lines forming a differential pair are arranged in parallel, and a plurality of memory cells are arranged in parallel for each column. One memory cell is selected by a row selection signal from a plurality of memory cells arranged in parallel in a column of bit lines forming a differential pair, and one column is selected by a column selection signal from a column of a plurality of bit lines arranged in parallel. Select and shift each potential of the selected bit line to be the differential pair to a predetermined reference voltage between the high-potential side power source potential and the low-potential side power source potential, then select the memory cell, and then select the reference voltage. Alternatively, it is a semiconductor memory device reading method for amplifying and outputting a difference in voltage amplitude or current amplitude between the bit lines forming a differential pair that symmetrically changes with respect to a reference current corresponding to the reference voltage.

According to a second aspect of the present invention, a plurality of columns of bit lines forming a differential pair are arranged in parallel, a plurality of memory cells are arranged in parallel for each column, and one of the plurality of memory cells is selected by a row selection signal. In the semiconductor memory device which selects a memory cell of the above and selects one column from a plurality of columns of bit lines by a column selection signal and outputs data, each of the bit lines forming a differential pair is selected prior to the selection of the memory cell. Level shift means for shifting the potential to a predetermined reference voltage between the high-potential side power source potential and the low-potential side power source potential, and the reference voltage or the reference current corresponding to the reference voltage depending on the selection of the memory cell are symmetrical with respect to each other. Output means for detecting and outputting a difference in voltage amplitude or current amplitude between the bit lines which changes to 1.

According to a third aspect of the present invention, a plurality of columns of bit lines forming a differential pair are arranged in parallel, a plurality of memory cells are arranged in parallel for each column, and one of the memory cells is selected by a row selection signal. In a semiconductor memory device that selects one of the plurality of bit lines according to the column selection signal and outputs data by selecting one of the columns of bit lines, a control signal that is valid for a predetermined period is output prior to the selection of the memory cell. Control means,
The respective potentials of the bit lines that are provided in each of the bit line columns that form a differential pair and that form a differential pair are set to a predetermined reference voltage between the high potential side power source potential and the low potential side power source potential. The level shift means for shifting to one, the column selection means for selecting one column from the column of bit lines forming a differential pair arranged in parallel by the column selection signal, and the differential pair selected by the column selection means. And a sense amplifier unit for amplifying a difference in amplitude between bit lines.

According to a fourth aspect of the present invention, a plurality of columns of bit lines forming a differential pair are arranged in parallel, a plurality of memory cells are arranged in parallel for each column, and one of the memory cells is selected by a row selection signal. In a semiconductor memory device that selects one of the plurality of bit lines according to the column selection signal and outputs data by selecting one of the columns of bit lines, a control signal that is valid for a predetermined period is output prior to the selection of the memory cell. Control means,
The respective potentials of the bit lines that are provided in each of the bit line columns that form a differential pair and that form a differential pair are set to a predetermined reference voltage between the high potential side power source potential and the low potential side power source potential. A level shift means for shifting to a pair, a column selection means for selecting one column by a column selection signal from a plurality of bit line columns forming a differential pair, and a differential pair selected by the column selection means. A voltage-current conversion means for converting a voltage amplitude difference between bit lines into a current amplitude difference, and a current sense amplifier means for amplifying a current amplitude difference between bit lines forming a differential pair converted by the voltage-current conversion means. And a semiconductor memory device.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the third and fourth aspects, the level shift means is one of a reference voltage setting means for setting a reference voltage and one of bit lines forming a differential pair. Between the switch and the output of the reference voltage setting means, which is interposed between the switch and the output of the reference voltage setting means, and which conducts for a predetermined time before selecting the memory cell; And a second switch means which is interposed between the first switch means and the second switch means for conducting for a predetermined time.

[0019]

According to the first aspect of the present invention, since the potentials of the bit line columns forming a differential pair are set to a predetermined reference voltage in the middle of both power supply voltages in advance, the bit line forming a differential pair is formed. Of the voltage or current of the reference voltage or the reference current corresponding to the reference voltage are symmetrical with respect to each other (for example, in the case of voltage amplitude, the voltage amplitude or current amplitude is bidirectional between the high potential side and the low potential side). fluctuate. Data is read by amplifying the difference between the two amplitudes.

According to the second aspect of the present invention, the level shift means sets the potential of the bit line forming the differential pair between the high potential side power source potential and the low potential side power source potential before the memory cell is selected. The level is shifted to a predetermined reference voltage. As a result, the voltage or current between both bit lines is symmetrical with respect to the reference voltage or reference current output from the level shift means, that is, if the voltage or current of one bit line increases, the other bit line. Since the voltage or the current changes in the decreasing direction, the output means detects and outputs the difference in the voltage amplitude or the current amplitude between the bit lines.

According to the third aspect of the present invention, the level shift means shifts the potential of the bit line forming the differential pair in advance to the reference voltage according to the control signal supplied from the control means, prior to the selection of the memory cell. . The column selection means selects one column from a plurality of bit line columns by a column selection signal. Since a difference in voltage amplitude occurs between the bit lines according to the data of the selected memory cell, the sense amplifier means current-amplifies this.

According to the fourth aspect of the present invention, the level shift means shifts the potential of the bit line forming the differential pair in advance to the reference voltage according to the control signal supplied from the control means, prior to the selection of the memory cell. . The column selection means selects one column from a plurality of bit line columns by a column selection signal. Although a difference in voltage amplitude occurs between the bit lines according to the data of the selected memory cell, the voltage-current conversion means converts this voltage amplitude difference into a current amplitude difference. Finally, the current sense amplifier means amplifies and outputs the difference in current amplitude.

According to the fifth aspect of the invention, the reference voltage setting means sets the reference voltage, and the first switch means and the second switch means form a differential pair prior to the memory cell selection. The line and the reference voltage output from the reference voltage setting means are short-circuited. Therefore, the potentials of the two bit lines are set to the reference voltage.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor memory device reading method and a semiconductor memory device according to the present invention will be described with reference to the drawings. (I) First Embodiment A semiconductor memory device according to the first embodiment is an SRAM to which the inventions of claims 1 to 3 and 5 are applied.

Circuit Configuration FIG. 1 shows a partial circuit diagram of the semiconductor memory device of the first embodiment. FIG. 1 shows a part of the memory cell array in the internal structure of the SRAM and a part related to its read circuit.

Generally, in the memory cell array, memory cells are arranged in a plurality of rows and columns (for example, 256 rows × 64 columns). A plurality of columns (for example, 256
Memory cells are arranged. Then, by selecting by a row selection signal (word line) based on an address signal supplied from the outside, the data of the memory cell is read and the data is written in the memory cell.

To simplify the description, FIG. 1 shows a column of bit lines B ₀ , / B _{0 and} a column of bit lines B ₁ , / B ₁ as a representative. The column of bit lines B ₀ and / B ₀ includes a memory cell 1 and a level shift circuit 2. Bit line B
The columns ₁ and / B ₁ include memory cells 5 and level shift circuits 6. The column switch 3 selects and outputs one column from a plurality of bit line columns by a column selection signal or the like. The sense amplifier 4 amplifies the current amplitude of the column of the selected bit line. The control circuit 7 includes a level shift circuit 2,
A control signal is supplied to 3, ... Via the level shift switch line A. The control circuit 7 may be a dedicated circuit, but the SRA
A timing circuit that controls the overall timing of M may also have this function.

The memory cell 1 is a complete CMOS flip
Transistor Q forming a flop ₁~ Q_FourAnd INVA
Transistor Q that composes the data₁And Q₃Output and
Line B₀Transistor Q for switching_FiveWhen,
Transistor Q that constitutes another inverter₂And Q_Fourof
Output and bit line / B₀Transis for switching
Q₆And This circuit is a typical SRAM
6-transistor CMOS having a conventional memory cell structure
It constitutes a static memory cell circuit.

The level shift circuit 2 is composed of transistors Q _{7 to} Q ₉ and Q ₁₂ for setting a reference voltage, and a switch for adjusting the bit lines B ₀ , / B ₀ to this reference voltage by a control signal supplied from the control circuit 7. Some transistors Q ₁₀ and Q ₁₁
And

Description of Operation Next, the operation of the first embodiment will be described with reference to the timing chart of FIG.

Here, a process of reading data when the memory cell 1 is selected will be described as an example. The high-potential-side power source potential is V _DD , and the low-potential-side power source potential is ground level, that is, 0 [V]. The bit lines B ₀ and / B ₀ are
It has the power supply potential V _DD in a steady state where data is not read or written. The potential of the word line W is at the ground level in a steady state that is not selected by the column decoder or the like.

Now, when the control circuit 7 is just before selecting a row,
Tick t₀Control signal to the level shift switch line at
Output (Fig. 2). Transistor of level shift circuit 2
Q _TenAnd Q₁₁Is the signal on the level shift switch line A
When it rises, it is turned on (conductive state). On the other hand,
Langista Q₁₂Is also turned on, so transistor Q
₇~ Q₉Through current flows through the transistor Q₁₂Flow to
It Transistor Q₇~ Q₉Each gate terminal of
Since it is connected to the node terminal, one transistor
Rari threshold voltage V_thMinute voltage drop occurs. So
Therefore, transistor Q₉And Q₁₂At the junction with
Rank V_DDTo the voltage V due to the voltage drop of three transistors
_LS(= 3 × V_th) Lower potential is generated. Based on this potential
Sub-voltage V_S(= V_DD-V_LS). Bit line B₀, /
B₀Is in a high resistance state when the memory cell is in the unselected state
Therefore, the potential of both bit lines is the reference voltage V_sHeld in
Be done.

Then, at time t₂In, the control circuit 7
The control signal is lowered, and the word line W is continuously selected.
(Fig. 2) The word line W is slightly affected by the load capacitance.
When it stands up after a delay time (time t₃), Memory
Rule 1 is selected. In other words, the transition of memory cell 1
Star Q_FiveAnd Q₆Turns on and the transistor Q ₁
~ Q_FourComplete CMOS type flip flow
Logic level of the output is output to the bit line. At this time,
If the column switch 3 is selected by the column control signal, etc.
If so, current will flow. Bit line B₀From
Langista Q_Five, Q₁Through the current I_CFlowing to the ground
Be done. Also, the power source V_DDFrom the transistor Q_FourAnd Q
₆Current through_CFlows to the column switch 3 side.
Both currents have opposite directions, so
The voltage appearing on the input line is the reference voltage V_SSymmetric about
Will change. For example, memory cell 1
Transistor Q₁And Q_FourIs on, transistor Q
₂And Q₃Is off, the bit line B₀of
Voltage is time t₃Bit line / B₀Voltage is above
Rise.

Since the column switch 3 only controls conduction by the column control signal, the difference between the currents on both bit lines is
It is amplified by the sense amplifier 4 which performs a voltage differential operation.
The current amplitude corresponding to the amplitude value a in FIG. 2 is detected.

At time t ₄ , when the word line W falls and the selection of the row is completed, the memory cell 1 is also deselected, the current passing through the memory cell 1 stops flowing, and the bit lines B ₀ and / B ₀ The power supply potential V _DD is held again.

Effects As described above, according to the semiconductor memory device of the first embodiment, as the word line is selected, a large current amplitude in the bit line,
Since the change in voltage amplitude can be obtained, as a result, the logical state of data can be detected at high speed, and the speed of the read operation as a whole can be increased. In other words, conventionally, only one of the voltages or currents changed from the reference voltage, and the change in amplitude as shown in FIGS. 5B and 6B was obtained, but in the present embodiment of FIG. Since the amplitude of the bit line changes, the amplitude twice that of the conventional one can be obtained. This means that the read speed was half and the speed was doubled. (Ii) Second Embodiment A semiconductor memory device according to the second embodiment is an SRAM to which the inventions of claim 1, claim 2, claim 4 and claim 5 are applied.

Circuit Configuration FIG. 3 shows a partial circuit diagram of the semiconductor memory device of the second embodiment. In this embodiment as well, similar to the first embodiment, a part of the memory cell array in the internal structure of the SRAM and a part related to its read circuit will be described.

FIG. 3 exemplifies the columns related to the bit lines B ₀ and / B ₀ in the SRAM memory cell array. Memory cell 1, level shift circuit 2, column switch 3,
The control circuit 7 has the same configuration as that of the first embodiment, and is given the same reference numeral as that of the first embodiment and its description is omitted.

The VI converting circuit 8 includes transistors Q ₂₀ to
It has Q ₂₈ and an inverter INV and converts a change in voltage between the bit lines CB and / CB supplied from the column switch 3 into a change in current. The current sense amplifier 9 is V-
The current difference between the two bit lines CB, / CB, CB ', / CB' supplied by the differential current from the I conversion circuit 8 is differential current amplified and output.

Description of Operation Next, the operation of the second embodiment will be described with reference to the timing chart of FIG. The level shift circuit 2 is a memory cell 1
Before being selected by the word line W, the bit lines B ₀ , /
B ₀ is held at a predetermined reference voltage V _S. This hold operation is performed by a control signal or the like output from the control circuit 7 as in the first embodiment.

At time t ₁₀ , when the word line W rises, the transistors Q ₅ and Q _{6 of} the memory cell 1 are turned on and become conductive, so that the currents I _C and / I _C depending on the logic state of the memory cell 1. Begins to flow. For example,
Transistor Q ₁ and transistor Q _{4 of} memory cell 1
Is on and the transistors Q ₂ and Q ₃ are off, the bit line B ₀ side stores the L level and the bit line / B ₀ side stores the H level bit state.

By selecting the memory cell 1, the VI conversion time is changed.
Power supply V for path 8_DDTo transistor Q ₂₀, Q_{twenty one}Via
Then, the transistor Q of the memory cell 1_FiveAnd Q₁Through
Current to land I_CFlows. On the other hand, the memory cell 1
Register Q_FourAnd Q₆Via the V-I conversion circuit 8
Transistor Q₂₇And Q₂₈Current to ground via_C
Flows. In the VI conversion circuit 8, a trigger is supplied to the terminal T.
By being supplied, the transistor Q₂₀, Q_{twenty one}, Q_{twenty five}Over
And Q₂₆A through current I flows through. Also, under the same conditions,
Register Q_{twenty three}, Q_{twenty four}, Q₂₇And Q₂₈Through current I flows to
It Therefore, the signal supplied to the current sense amplifier 9 is
The bit lines B to the input lines CB and / CB.₀Voltage difference
It is converted into a kinetic current and flows. Also, the bit lines CB ', /
CB 'has a bit line / B₀Voltage change into differential current
It is exchanged and flows. Is the current sense amplifier 9 a double differential pair?
The amplitude is obtained from and output.

The voltage amplitude of the differential pair at this time is as shown in FIG. That is, the difference between the amplitude in the state where the memory cell 1 is not selected and the amplitude when the voltage change occurs in the bit destinations B ₀ and / B ₀ that are the differential pair when the memory cell 1 is selected is shown in FIG. It can be represented by a ₁ -a ₂ , which is the difference in the obtained amplitude values. In the circuit having the conventional current sense amplifier, only the signal amplitude of one of the bit lines CB, / CB or CB ', / CB', which is the differential pair supplied to the current sense amplifier, is obtained. In this embodiment, a double amplitude value can be obtained.

At time t ₁₁ , when the word line W falls and the memory cell 1 is in the non-selected state, the current flowing through the VI conversion circuit 8 is only the through current, so that the current sense amplifier 9 has the differential circuit. No current is supplied.

The VI converting circuit 8 of the present embodiment is not limited to the one illustrated in FIG. 3, but a known one can be applied. Effect As described above, according to the second embodiment, even when the current sense amplifier is used, the double amplitude value can be obtained by using the VI conversion circuit. As a result, the speed can be doubled as compared with the conventional one. Modifications of Other Embodiments Not limited to the above-described embodiments of the present invention, various modifications are possible.

First, as the applicable memory cell type, the present invention is applied to the SRAM having the CMOS type memory cell in each of the above embodiments, but as described in each claim, The present invention can be applied to any memory system in which data is written / read by a memory cell array having bit lines that operate as a differential pair. For this reason,
For example, in SRAM, the complete CMO as in the above embodiment is used.
In addition to S type memory cells, E / D type and E / E type NMOSs
Type memory cell, high resistance load (E
/ R) type memory cell or the like can be used.

Secondly, since it is necessary to have a memory cell having a differential pair, the present invention can be applied not only to the SRAM as long as it has the bit line of the differential pair. For example, a 4-transistor type DRAM (Dynamic Ra
ndom Access Memory), bipolar transistor RAM
Etc. can be applied. Other aspects of the invention In the semiconductor memory device according to claim 2,
The memory cell includes a flip-flop composed of four transistors, a first transistor which makes one input of the flip-flop and one bit line conductive by a row selection signal, and the other input of the flip-flop. And a second transistor for electrically connecting the other bit line to each other by the row selection signal, which is a static memory cell.

According to the above invention, since the memory cell constitutes a static memory cell with so-called 6 transistors, the potential of the bit line in the steady state is set to an intermediate potential between both power supply voltages by the level shift means,
A voltage amplitude or a current amplitude that changes symmetrically with respect to a reference voltage or a reference current corresponding to the reference voltage is generated between both bit lines.

As a result, in the memory cell type preferable as the SRAM cell, the characteristic of the amplitude change symmetrical between the bit lines with respect to the reference voltage or the reference current can be obtained, and the read operation can be speeded up.

[0050]

According to the first and second aspects of the present invention, the potential of each of the bit lines forming the differential pair is a predetermined reference voltage between the high potential side power source potential and the low potential side power source potential. Since the voltage amplitude or the current amplitude is shifted symmetrically with respect to the reference voltage or the reference current, the amplitude value twice as large as that in the conventional case can be taken out, and the entire read operation can be significantly speeded up.

According to the third aspect of the invention, since the voltage of the bit line changes symmetrically with respect to the reference voltage, the voltage amplitude can be detected at twice the speed of the conventional one, and the data can be read out at high speed. be able to.

According to the fourth aspect of the invention, the voltage-current conversion means can change the voltage change into the current change, so that the current sense amplifier means operating in the current mode is twice as fast as the conventional one. Can be realized.

According to the fifth aspect of the invention, the reference voltage setting means easily sets the reference voltage, and the first switch means and the second switch means are electrically connected for a predetermined time by the control signal. It is possible to easily hold the potentials of both bit lines forming a differential pair at the reference voltage.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is an operating characteristic diagram of the first embodiment.

FIG. 3 is a partial circuit diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is an operating characteristic diagram of the second embodiment.

FIG. 5 is a first example of a conventional semiconductor memory device, (A) is a partial circuit diagram, and (B) is an operating characteristic diagram.

FIG. 6 is a second example of a conventional semiconductor memory device, (A) is a partial circuit diagram, and (B) is an operating characteristic diagram.

[Explanation of symbols]

1, 5, 10, 11, 20, 21 ... Memory cell 2, 6, 13, 22, 23 ... Level shift circuit 3, 12, 24 ... Column switch 4, 14, 25 ... Sense amplifier 7 ... Control circuit 8 ... V -I conversion circuit 9 ... current sense amplifier 15, 26 ... memory cell array INV ... inverter A ... level shift switch line _{B, / B, B 0,} / B 0, B 1, / B 1 ... bit line CB, / CB, CB ₀ , / CB ₀ , CB ₁ , / CB ₁ ...
Bit line _{Q 1 ~Q 12, Q 20 ~Q} 28, Q 30 ~Q 34, Q 40 ~Q 45 ... transistor V _DD ... supply voltage V _LS ... level shift voltage V _Q ... transistor voltage drop W ... wordline

Claims (5)

[Claims] 1. A method of reading a semiconductor memory device, wherein a plurality of columns of bit lines forming a differential pair are arranged in parallel, and a plurality of memory cells are arranged in parallel for each column. One memory cell is selected by a row selection signal from a plurality of memory cells arranged in parallel in a column of
One column is selected from the column of a plurality of bit lines arranged in parallel by a column selection signal, and the respective potentials of the selected bit lines forming the differential pair are set to a high potential side power source potential and a low potential side power source potential. A bit line that becomes the differential pair that is symmetrically changed with respect to the reference voltage or a reference current corresponding to the reference voltage after selecting the memory cell after shifting to a predetermined reference voltage between the potential and the potential. A method of reading a semiconductor memory device, comprising amplifying and outputting a difference in voltage amplitude or current amplitude between them. 2. A plurality of columns of bit lines forming a differential pair are arranged in parallel, a plurality of memory cells are arranged in parallel for each column, and one memory cell is selected from the plurality of memory cells by a row selection signal. In a semiconductor memory device which selects one column from a plurality of columns of the bit lines by a column selection signal and outputs data, the potentials of the bit lines forming the differential pair are set prior to the selection of the memory cells. Level shift means for shifting to a predetermined reference voltage between a high-potential-side power source potential and a low-potential-side power source potential, and symmetry with respect to the reference voltage or a reference current corresponding to the reference voltage depending on the selection of the memory cell. A semiconductor memory device, comprising: an output unit that detects and outputs a difference in voltage amplitude or current amplitude between bit lines that changes dynamically. 3. A plurality of columns of bit lines forming a differential pair are arranged in parallel, a plurality of memory cells are arranged in parallel for each column, and one memory cell is selected from the plurality of memory cells by a row selection signal. In a semiconductor memory device that selects one column from a plurality of columns of the bit lines by a column selection signal and outputs data, a control unit that outputs a control signal that is valid for a predetermined period prior to the selection of the memory cell; , The potential of each of the bit lines that are provided in each of the bit line columns that form the differential pair and that form the differential pair is set between the high potential side power source potential and the low potential side power source potential based on the control signal. Level shift means for shifting to a predetermined reference voltage, column selecting means for selecting one of the columns of bit lines forming a differential pair arranged in parallel by a column selecting signal, and selected by the column selecting means. The semiconductor memory device characterized by comprising a sense amplifier means for amplifying the difference in amplitude between the bit lines becomes the differential pair. 4. A plurality of columns of bit lines forming a differential pair are arranged in parallel, a plurality of memory cells are arranged in parallel for each column, and one memory cell is selected from the plurality of memory cells by a row selection signal. In a semiconductor memory device that selects one column from a plurality of columns of the bit lines by a column selection signal and outputs data, a control unit that outputs a control signal that is valid for a predetermined period prior to the selection of the memory cell; , The potential of each of the bit lines that are provided in each of the bit line columns that form the differential pair and that form the differential pair is set between the high potential side power source potential and the low potential side power source potential based on the control signal. Level shift means for shifting to a predetermined reference voltage; column selection means for selecting one column by a column selection signal from the plurality of bit line columns forming a differential pair arranged in parallel; and selected by the column selection means. Was The difference between the voltage amplitudes of the bit lines forming the active pair and the difference between the current amplitudes of the bit lines forming the differential pair converted by the voltage-current converting means. A semiconductor memory device comprising: a current sense amplifier unit for amplifying. 5. The semiconductor memory device according to claim 3, wherein the level shift means includes a reference voltage setting means for setting a reference voltage, one of the bit lines forming the differential pair, and the reference voltage. Between first switch means interposed between the output of the setting means and conducting for a predetermined time before selecting the memory cell, and between the other of the bit lines forming the differential pair and the output of the reference voltage setting means. A semiconductor memory device comprising: a second switch means interposed between the first switch means and the second switch means for conducting for a predetermined time.