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JPH0883817A - Semiconductor integrated circuit and its manufacturing method - Google Patents

Semiconductor integrated circuit and its manufacturing method

Info

Publication number
JPH0883817A
JPH0883817A JP6216137A JP21613794A JPH0883817A JP H0883817 A JPH0883817 A JP H0883817A JP 6216137 A JP6216137 A JP 6216137A JP 21613794 A JP21613794 A JP 21613794A JP H0883817 A JPH0883817 A JP H0883817A
Authority
JP
Japan
Prior art keywords
metal
semiconductor device
integrated circuit
spherical body
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6216137A
Other languages
Japanese (ja)
Inventor
Hiroaki Yadokoro
博明 谷所
Tsunetaro Nose
恒太郎 能勢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP6216137A priority Critical patent/JPH0883817A/en
Publication of JPH0883817A publication Critical patent/JPH0883817A/en
Withdrawn legal-status Critical Current

Links

Classifications

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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To decrease the impedance of a metal wire with a simple process and to reduce packaging cost by providing a metal wire which is bonded to both a metal spherical body laid out on a metal rib and a metal pad. CONSTITUTION: A metal spherical body 14 is bonded to a metal rib 16 and at the same time the upper portion of the metal spherical body 14 and source electrode pads 18a and 18b are bonded by a short gold wire 13. The height dimension of the metal spherical body 14 is formed to be equal to the thickness of a semiconductor device 15. In terms of the manufacturing method, first the metal spherical body 14 is formed, the metal spherical body 14 is pressed against the metal rib 16 by a capillary 31 for first bonding. Also, at this time, the gold wire 13 is cut at the head part of the metal spherical body 14. Then, the gold wire 13 is pressed against the head part of the metal spherical body 14 and a source electrode pad 18b of the semiconductor device 15 with a wedge tool 32 which is a wire bonding tool of a wedge bonder for performing a second bonding.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、高周波帯域の信号を伝
送させるのに好適な半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit suitable for transmitting signals in a high frequency band.

【０００２】[0002]

【従来の技術】図４は、従来の半導体集積回路の組み立
てた状態を示す図である。この半導体集積回路には、Ｇ
ａＡｓ（ガリウム・ヒ素）基板上に形成された、ＨＥＭ
Ｔ（Ｈｉｇｈ Ｅｌｅｃｔｒｏｎ Ｍｏｂｉｌｉｔｙ
Ｔｒａｎｓｉｓｔｏｒ）を基本素子とした半導体デバイ
ス１５が備えられている。この半導体デバイス１５の厚
みは、およそ１００μｍであり、その表面にはグラウン
ドと接続される２つのソース電極パッド１８ａ，１８ｂ
と、伝送ラインと接続される４つの信号電極パッド１９
ａ，１９ｂ，１９ｃ，１９ｄとが備えられている。2. Description of the Related Art FIG. 4 is a diagram showing an assembled state of a conventional semiconductor integrated circuit. This semiconductor integrated circuit has G
HEM formed on aAs (gallium arsenide) substrate
T (High Electron Mobility)
A semiconductor device 15 including a transistor as a basic element is provided. The semiconductor device 15 has a thickness of about 100 μm, and has two source electrode pads 18a and 18b connected to the ground on the surface thereof.
And four signal electrode pads 19 connected to the transmission line
a, 19b, 19c and 19d are provided.

【０００３】また、半導体デバイス１５の長手方向の両
側には回路基板１１，１２が配置されており、これら回
路基板１１，１２に、高周波帯域の信号を伝送させるた
めの伝送ライン１１ａ，１２ａがそれぞれ形成されてい
る。ここで回路基板１１，１２の板厚は、半導体デバイ
ス１５の厚み１００μｍより大きくなっている。そこで
ソース電極パッド１８ａ，１８ｂ，信号電極パッド１９
ａ，１９ｂ，１９ｃ，１９ｄの高さ位置と、伝送ライン
１１ａ，１２ａの高さ位置とを一致させるため、半導体
デバイス１５が金属リブ１６に載置されている。また、
金属リブ１６と回路基板１１，１２は、グラウンド電位
に保持された金属キャリア１７に載置されている。Circuit boards 11 and 12 are arranged on both sides of the semiconductor device 15 in the longitudinal direction, and transmission lines 11a and 12a for transmitting signals in a high frequency band are respectively provided on the circuit boards 11 and 12. Has been formed. Here, the board thicknesses of the circuit boards 11 and 12 are larger than the thickness 100 μm of the semiconductor device 15. Therefore, the source electrode pads 18a and 18b, the signal electrode pad 19
In order to make the height positions of a, 19b, 19c and 19d coincide with the height positions of the transmission lines 11a and 12a, the semiconductor device 15 is mounted on the metal rib 16. Also,
The metal rib 16 and the circuit boards 11 and 12 are mounted on a metal carrier 17 held at the ground potential.

【０００４】また、外径寸法２０μｍφを有する金線１
３で、ソース電極パッド１８ａ，１８ｂが金属リブ１６
に、信号電極パッド１９ａ，１９ｂが伝送ライン１１ａ
に、信号電極パッド１９ｃ，１９ｄが伝送ライン１２ａ
にそれぞれボンディングされている。このようにして半
導体集積回路が組み立てられている。A gold wire 1 having an outer diameter of 20 μmφ
3, the source electrode pads 18a and 18b are metal ribs 16
In addition, the signal electrode pads 19a and 19b are connected to the transmission line 11a.
In addition, the signal electrode pads 19c and 19d are connected to the transmission line 12a.
Are bonded to each. In this way, the semiconductor integrated circuit is assembled.

【０００５】[0005]

【発明が解決しようとする課題】前述したように、半導
体デバイス１５は金属リブ１６に載置され、信号電極パ
ッド１９ａ，１９ｂ，１９ｃ，１９ｄの高さ位置と伝送
ライン１１ａ，１２ａの高さ位置とが一致しているた
め、信号電極パッド１９ａ，１９ｂ，１９ｃ，１９ｄと
伝送ライン１１ａ，１２ａは、金線１３で最も短くボン
ディングされている。As described above, the semiconductor device 15 is mounted on the metal rib 16, and the height positions of the signal electrode pads 19a, 19b, 19c and 19d and the height positions of the transmission lines 11a and 12a are set. Therefore, the signal electrode pads 19a, 19b, 19c, 19d and the transmission lines 11a, 12a are bonded by the gold wire 13 at the shortest.

【０００６】一方、ソース電極パッド１８ａ，１８ｂの
高さ位置は、金属リブ１６の、ボンディングされる部分
の高さ位置と比較し、半導体デバイス１５の厚み１００
μｍ分だけ高くなっており、ソース電極パッド１８ａ，
１８ｂと金属リブ１６は、その厚みが含まれた長さの金
線１３でボンディングされている。図５は、図４に示す
半導体集積回路のＡ−Ａ断面図である。On the other hand, the height position of the source electrode pads 18a and 18b is 100 mm thick compared to the height position of the portion of the metal rib 16 to be bonded.
.mu.m higher, and the source electrode pad 18a,
18b and the metal rib 16 are bonded by a gold wire 13 having a length including the thickness thereof. FIG. 5 is a cross-sectional view taken along the line AA of the semiconductor integrated circuit shown in FIG.

【０００７】半導体デバイス１５のソース電極パッド１
８ａ，１８ｂと金属リブ１６は外径寸法２０μｍφの金
線１３でボンディングされている。この金線１３の長さ
は、半導体デバイス１５の厚みｈ、即ち１００μｍを含
む少なくとも３００〜４００μｍ程度必要とされる。こ
こで、高周波帯域において、この金線１３の長さが３０
０μｍを超えると、金線１３の有する誘導成分の増加に
伴い、金線１３のインピーダンスも増加し、ソース電極
パッド１８ａ，１８ｂのグラウンド電位が上昇し、半導
体集積回路の伝送特性が低下し、半導体集積回路の動作
不良の要因とされ問題がある。Source electrode pad 1 of semiconductor device 15
8a, 18b and the metal rib 16 are bonded by a gold wire 13 having an outer diameter of 20 μmφ. The length of the gold wire 13 is required to be at least about 300 to 400 μm including the thickness h of the semiconductor device 15, that is, 100 μm. Here, in the high frequency band, the length of the gold wire 13 is 30
When it exceeds 0 μm, the impedance of the gold wire 13 increases with the increase of the inductive component of the gold wire 13, the ground potential of the source electrode pads 18a and 18b rises, and the transmission characteristic of the semiconductor integrated circuit deteriorates. This is a cause of malfunction of the integrated circuit, and there is a problem.

【０００８】そこでこの要因を取り除くために、金線１
３の長さが短くなるように工夫された半導体集積回路が
提案されている。図６は、金属リブ１６に設けられた凹
部に半導体デバイス１５が嵌め込まれた状態を示す断面
図である。このように半導体デバイス１５を金属リブ１
６に設けられた凹部に嵌め込むことにより、半導体デバ
イス１５のソース電極パッド１８ａ，１８ｂの高さ位置
と、金属リブ１６の、ボンディングされる部分の高さ位
置とを一致させ、金線１３の長さを短くすることによ
り、金線１３のインピーダンスが小さくなり、半導体集
積回路の伝送特性の向上が図られている。Therefore, in order to remove this factor, the gold wire 1
A semiconductor integrated circuit devised so that the length of 3 is shortened has been proposed. FIG. 6 is a cross-sectional view showing a state in which the semiconductor device 15 is fitted in the recess provided in the metal rib 16. In this way, the semiconductor device 15 is attached to the metal rib 1
By fitting in the recesses provided in 6, the height positions of the source electrode pads 18a, 18b of the semiconductor device 15 and the height positions of the metal ribs 16 to be bonded are made to coincide with each other, and the gold wire 13 By reducing the length, the impedance of the gold wire 13 is reduced, and the transmission characteristics of the semiconductor integrated circuit are improved.

【０００９】図７は、半導体デバイス１５と２つの金属
コラム７１ａ，７１ｂが金属リブ１６に載置された状態
を示す断面図である。このように半導体デバイス１５の
両側に、半導体デバイス１５の厚みと同じ厚みを有す
る、グラウンド電位に固定された２つの金属コラム７１
ａ，７１ｂを配置することにより、半導体デバイス１５
のソース電極パッド１８ａ，１８ｂの高さ位置と、金属
コラム７１ａ，７１ｂの、ボンディングされる部分の高
さ位置とを一致させ、金線１３の長さを短くしている。FIG. 7 is a sectional view showing a state in which the semiconductor device 15 and the two metal columns 71a and 71b are mounted on the metal rib 16. Thus, on both sides of the semiconductor device 15, two metal columns 71 having the same thickness as the semiconductor device 15 and fixed to the ground potential are provided.
By arranging a and 71b, the semiconductor device 15
The height positions of the source electrode pads 18a and 18b are matched with the height positions of the bonded portions of the metal columns 71a and 71b, and the length of the gold wire 13 is shortened.

【００１０】しかし、図６に示す半導体集積回路におい
ては、金属リブ１６に凹部を形成するための微細な金属
加工が必要とされる。この微細な金属加工は手間がかか
り、さらに加工された凹部に半導体デバイス１５を嵌め
込む手間も含め、実装コストが高くなるという問題があ
る。一方、図７に示す半導体集積回路においても２つの
金属コラム７１ａ，７１ｂを製作するための必要とされ
る。このため、これら部品の増加と、加工の手間との双
方について費用が発生し、やはり実装コストが高くなる
という問題がある。However, in the semiconductor integrated circuit shown in FIG. 6, fine metal working is required to form recesses in the metal ribs 16. This fine metal working requires a lot of labor, and there is a problem that the mounting cost becomes high including the labor of fitting the semiconductor device 15 into the worked recess. On the other hand, also in the semiconductor integrated circuit shown in FIG. 7, it is necessary to manufacture two metal columns 71a and 71b. For this reason, there is a problem in that costs are increased both for the increase in the number of these parts and the labor for processing, and the mounting cost is also high.

【００１１】本発明は、上記事情に鑑み、実装コストの
低減が図られた半導体集積回路およびその製造方法を提
供することを目的とする。In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit and a method for manufacturing the semiconductor integrated circuit, the mounting cost of which is reduced.

【００１２】[0012]

【課題を解決するための手段】上記目的を達成する本発
明の半導体集積回路は、グラウンドと接続される電極パ
ッドを有する半導体デバイスと、その半導体デバイスが
載置され、その半導体デバイスの電極パッドと接続され
る金属リブとを備えた半導体集積回路において、 （１）上記金属リブ上に配置された金属球体 （２）上記金属球体と上記電極パッドとの双方にボンデ
ィングされた金属ワイヤを備えたことを特徴とするもの
である。A semiconductor integrated circuit according to the present invention which achieves the above object, includes a semiconductor device having an electrode pad connected to the ground, the semiconductor device mounted thereon, and an electrode pad of the semiconductor device. A semiconductor integrated circuit having metal ribs to be connected, (1) a metal sphere arranged on the metal rib, (2) a metal wire bonded to both the metal sphere and the electrode pad. It is characterized by.

【００１３】また、上記半導体集積回路を製造する本発
明の製造方法は、グラウンドと接続される電極パッドを
有する半導体デバイスと、その半導体デバイスが載置さ
れ、その半導体デバイスの電極パッドと接続される金属
リブとを備えた半導体集積回路の製造方法において、ボ
ールボンダを用いて上記金属リブ上に金属球体をボンデ
ィングし、さらにその金属球体の上部と上記電極パッド
とを金属ワイヤでボンディングすることを特徴とするも
のである。Further, in the manufacturing method of the present invention for manufacturing the above semiconductor integrated circuit, a semiconductor device having an electrode pad connected to the ground, the semiconductor device is mounted, and connected to the electrode pad of the semiconductor device. In a method for manufacturing a semiconductor integrated circuit having a metal rib, a ball bonder is used to bond a metal sphere onto the metal rib, and the upper part of the metal sphere and the electrode pad are bonded with a metal wire. It is what

【００１４】[0014]

【作用】本発明の半導体集積回路は、金属リブ上に金属
球体がボンディングされており、その金属球体の体積は
金属ワイヤの体積よりも十分大きいため、高周波帯域に
おける金属球体のインピーダンスは小さく、その金属球
体は、金属リブのグラウンド電位と同等のグラウンド電
位を有する。したがって、従来技術のように金属リブに
凹部を形成するための微細な金属加工を行うこともな
く、また半導体デバイスの両側に金属コラムを配置する
こともなく、半導体デバイスの電極パッドの高さ位置と
同等な高さ位置にグラウンド電位の部分が、簡単な工程
で容易に得られ、実装コストが低減される。In the semiconductor integrated circuit of the present invention, the metal sphere is bonded on the metal rib, and the volume of the metal sphere is sufficiently larger than the volume of the metal wire. Therefore, the impedance of the metal sphere in the high frequency band is small. The metal sphere has a ground potential equivalent to that of the metal rib. Therefore, unlike the prior art, there is no need to perform fine metal processing for forming recesses in the metal rib, and neither metal columns are arranged on both sides of the semiconductor device, and the height position of the electrode pad of the semiconductor device is A ground potential portion can be easily obtained at a height position equivalent to that in a simple process, and the mounting cost can be reduced.

【００１５】さらに、半導体デバイスの電極パッドと、
その電極パッドと同等な高さ位置の、金属球体の部分と
が金属ワイヤでボンディングされているため、金属ワイ
ヤが短くて済み、金属ワイヤのインピーダンスが低減さ
れ、高周波帯域において、伝送特性の低下が少なく安定
した半導体集積回路が構成される。Further, an electrode pad of the semiconductor device,
Since the metal sphere at the same height position as the electrode pad is bonded with the metal wire, the metal wire can be short, the impedance of the metal wire is reduced, and the transmission characteristics are deteriorated in the high frequency band. A small and stable semiconductor integrated circuit is constructed.

【００１６】[0016]

【実施例】以下、本発明の実施例について説明する。図
１は、本発明の一実施例の半導体集積回路の、組み立て
た状態を示す斜視図、図２は、図１に示す半導体集積回
路のＡ−Ａ断面図である。図１、図２において、前述し
た従来例（図４）と同一の構成要素には同一の番号を付
して示し、相違点についてのみ説明する。Embodiments of the present invention will be described below. FIG. 1 is a perspective view showing an assembled state of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA of the semiconductor integrated circuit shown in FIG. 1 and 2, the same components as those of the conventional example (FIG. 4) described above are denoted by the same reference numerals, and only different points will be described.

【００１７】図１に示す半導体集積回路は、図４に示す
半導体回路と比較すると、図４に示すソース電極パッド
１８ａ，１８ｂと金属リブ１６とが金線１３で直接ボン
ディングされていることに代わり、金属リブ１６に金属
球体１４がボンディングされているとともに、その金属
球体１４の上部とソース電極パッド１８ａ，１８ｂと
が、図４に示す金線１３より短い金線１３でボンディン
グされている。The semiconductor integrated circuit shown in FIG. 1 is different from the semiconductor circuit shown in FIG. 4 in that the source electrode pads 18a and 18b and the metal rib 16 shown in FIG. The metal sphere 14 is bonded to the metal rib 16, and the upper part of the metal sphere 14 and the source electrode pads 18a and 18b are bonded by the gold wire 13 shorter than the gold wire 13 shown in FIG.

【００１８】図２に示すように、金属球体１４の高さ寸
法は、半導体デバイス１５の厚みと同等の寸法、即ちお
よそ１００μｍに形成されている。この金属球体１４の
体積は、図４に示す金線１３の体積と比較し十分大き
く、高周波帯域における金属球体１４のインピーダンス
は十分小さく、この金属球体１４は金属リブ１６のグラ
ウンド電位と同等のグラウンド電位を有する。As shown in FIG. 2, the height of the metal sphere 14 is equal to the thickness of the semiconductor device 15, that is, about 100 μm. The volume of the metal sphere 14 is sufficiently larger than that of the gold wire 13 shown in FIG. 4, the impedance of the metal sphere 14 in the high frequency band is sufficiently small, and the metal sphere 14 has a ground potential equal to the ground potential of the metal rib 16. It has an electric potential.

【００１９】また、金属球体１４の上部のボンディング
位置は、半導体デバイス１５のソース電極パッド１８
ａ，１８ｂの高さ位置と同じ高さのため、これらをボン
ディングしている金線１３は短くて済み、これに伴い金
線１３のインピーダンスも小さく、金属球体１４のイン
ピーダンスと相まって半導体デバイス１５のソース電極
パッド１８ａ，１８ｂと金属リブ１６との間のインピー
ダンスが小さくなっている。The bonding position above the metal sphere 14 is at the source electrode pad 18 of the semiconductor device 15.
Since the heights of the a and 18b are the same as those of the semiconductor device 15, the gold wire 13 bonding them is short, and the impedance of the gold wire 13 is small accordingly. The impedance between the source electrode pads 18a and 18b and the metal rib 16 is small.

【００２０】図３は、本発明の一実施例の半導体集積回
路の製造過程を示す図である。先ず、図３（ａ）に示す
ように、ボールボンダのワイヤボンディングツールであ
るキャピラリ３１の先端から押し出された金線１３を、
図示しない電気トーチで溶融し、半導体デバイス１５の
厚み１００μｍの約２倍の大きさの直径を有する金属球
体１４を形成した。FIG. 3 is a diagram showing a manufacturing process of a semiconductor integrated circuit according to an embodiment of the present invention. First, as shown in FIG. 3A, the gold wire 13 extruded from the tip of the capillary 31 which is the wire bonding tool of the ball bonder is
It was melted with an electric torch (not shown) to form metal spheres 14 having a diameter approximately twice the thickness of the semiconductor device 15 of 100 μm.

【００２１】次に、図３（ｂ）に示すように金属球体１
４をキャピラリ３１で金属リブ１６に押しつけ、金属球
体１４の高さがおよそ１００μｍとなるように第１ボン
ディングを行った。またこの時、金線１３は金属球体１
４の頭部で切断した。次に、図３（ｃ）に示すように、
ウェッジボンダのワイヤボンディングツールであるウェ
ッジツール３２で金属球体１４の頭部と半導体デバイス
１５のソース電極パッド１８ｂとに金線１３を押し付
け、第２ボンディングを行った。この金線１３の長さは
２００〜３００μｍの範囲に十分収まるものであった。
これにより、高周波帯域において、良好な伝送特性を有
する半導体集積回路が形成された。Next, as shown in FIG. 3B, the metal sphere 1
4 was pressed against the metal rib 16 by the capillary 31, and the first bonding was performed so that the height of the metal sphere 14 was about 100 μm. At this time, the gold wire 13 is the metal sphere 1.
It cut with the head of 4. Next, as shown in FIG.
The second bonding was performed by pressing the gold wire 13 against the head of the metal sphere 14 and the source electrode pad 18b of the semiconductor device 15 with the wedge tool 32 which is a wire bonding tool of the wedge bonder. The length of the gold wire 13 was well within the range of 200 to 300 μm.
As a result, a semiconductor integrated circuit having good transmission characteristics in the high frequency band was formed.

【００２２】尚、本実施例では、第２ボンディングをウ
ェッジボンダを使用して行ったが、これに限定されるも
のではなく、第２ボンディングもボールボンダを使用し
て行っても良い。In this embodiment, the second bonding is performed by using the wedge bonder, but the present invention is not limited to this, and the second bonding may be performed by using the ball bonder.

【００２３】[0023]

【発明の効果】以上説明したように、本発明の半導体集
積回路およびその製造方法は、金属リブ上に配置された
金属球体と半導体デバイスの電極パッドとに金属ワイヤ
がボンディングされたものであり、簡単な工程で金属ワ
イヤのインピーダンスを下げることができ、実装コスト
が低減されるとともに信頼性が向上する。As described above, the semiconductor integrated circuit and the method for manufacturing the same according to the present invention are those in which metal wires are bonded to the metal spheres arranged on the metal ribs and the electrode pads of the semiconductor device. The impedance of the metal wire can be lowered by a simple process, which reduces the mounting cost and improves the reliability.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例の半導体集積回路の、組み立
てた状態を示す斜視図である。FIG. 1 is a perspective view showing an assembled state of a semiconductor integrated circuit according to an embodiment of the present invention.

【図２】図１に示す半導体集積回路のＡ−Ａ断面図であ
る。2 is a cross-sectional view taken along the line AA of the semiconductor integrated circuit shown in FIG.

【図３】本発明の一実施例の半導体集積回路の製造過程
を示す図である。FIG. 3 is a diagram showing a manufacturing process of a semiconductor integrated circuit according to an embodiment of the present invention.

【図４】従来の半導体集積回路の組み立てた状態を示す
図である。FIG. 4 is a diagram showing an assembled state of a conventional semiconductor integrated circuit.

【図５】図４に示す半導体集積回路のＡ−Ａ断面図であ
る。5 is a cross-sectional view taken along the line AA of the semiconductor integrated circuit shown in FIG.

【図６】金属リブに設けられた凹部に半導体デバイスが
嵌め込まれた状態を示す断面図である。FIG. 6 is a cross-sectional view showing a state in which a semiconductor device is fitted in a recess provided in a metal rib.

【図７】半導体デバイスと２つの金属コラムが金属リブ
に載置された状態を示す断面図である。FIG. 7 is a cross-sectional view showing a state in which a semiconductor device and two metal columns are mounted on a metal rib.

【符号の説明】[Explanation of symbols]

１１，１２ 回路基板 １１ａ，１２ａ 伝送ライン １３ 金線 １４ 金属球体 １５ 半導体デバイス １６ 金属リブ １７ 金属キャリア １８ａ，１８ｂ ソース電極パッド １９ａ，１９ｂ，１９ｃ，１９ｄ 信号電極パッド ３１ キャピラリ ７１ａ，７１ｂ 金属コラム 11, 12 Circuit board 11a, 12a Transmission line 13 Gold wire 14 Metal sphere 15 Semiconductor device 16 Metal rib 17 Metal carrier 18a, 18b Source electrode pad 19a, 19b, 19c, 19d Signal electrode pad 31 Capillary 71a, 71b Metal column

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 グラウンドと接続される電極パッドを有
する半導体デバイスと、該半導体デバイスが載置され、
該半導体デバイスの電極パッドと接続される金属リブと
を備えた半導体集積回路において、 前記金属リブ上に配置された金属球体と、 前記金属球体と前記電極パッドとの双方にボンディング
された金属ワイヤとを備えたことを特徴とする半導体集
積回路。1. A semiconductor device having an electrode pad connected to the ground, and the semiconductor device mounted thereon.
In a semiconductor integrated circuit including a metal rib connected to an electrode pad of the semiconductor device, a metal sphere arranged on the metal rib, and a metal wire bonded to both the metal sphere and the electrode pad. A semiconductor integrated circuit comprising: 【請求項２】 グラウンドと接続される電極パッドを有
する半導体デバイスと、該半導体デバイスが載置され、
該半導体デバイスの電極パッドと接続される金属リブと
を備えた半導体集積回路の製造方法において、 ボールボンダを用いて前記金属リブ上に金属球体をボン
ディングし、さらに該金属球体の上部と前記電極パッド
とを金属ワイヤでボンディングすることを特徴とする半
導体集積回路の製造方法。2. A semiconductor device having an electrode pad connected to the ground, and the semiconductor device mounted on the semiconductor device.
In a method of manufacturing a semiconductor integrated circuit including a metal rib connected to an electrode pad of the semiconductor device, a metal sphere is bonded onto the metal rib by using a ball bonder, and the upper part of the metal sphere and the electrode pad are further bonded. A method for manufacturing a semiconductor integrated circuit, comprising: bonding a metal wire and a metal wire together.
JP6216137A 1994-09-09 1994-09-09 Semiconductor integrated circuit and its manufacturing method Withdrawn JPH0883817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6216137A JPH0883817A (en) 1994-09-09 1994-09-09 Semiconductor integrated circuit and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6216137A JPH0883817A (en) 1994-09-09 1994-09-09 Semiconductor integrated circuit and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH0883817A true JPH0883817A (en) 1996-03-26

Family

ID=16683853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6216137A Withdrawn JPH0883817A (en) 1994-09-09 1994-09-09 Semiconductor integrated circuit and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH0883817A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004529484A (en) * 2000-09-15 2004-09-24 ヘイ，インコーポレイテッド Connections for transmitting high-frequency signals between circuits and individual electrical components
CN116038049A (en) * 2022-12-22 2023-05-02 苏州卓昱光子科技有限公司 Gold wire bonding method and gold wire bonding system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004529484A (en) * 2000-09-15 2004-09-24 ヘイ，インコーポレイテッド Connections for transmitting high-frequency signals between circuits and individual electrical components
CN116038049A (en) * 2022-12-22 2023-05-02 苏州卓昱光子科技有限公司 Gold wire bonding method and gold wire bonding system

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