JPH0884063A - Cmos buffer circuit - Google Patents

Abstract

PURPOSE: To obtain a CMOS buffer circuit in which the operating speed is not lowered while simultaneously decreasing a switching noise when power supply voltage drops. CONSTITUTION: A first gate circuit 11 is provided with an NMOS transistor QN13 for clamp on the side of the source of an NMOS transistor QN12. This transistor QN13 is connected to an NMOS transistor QN14 for switch in parallel. A second gate circuit 12 is provided with a PMOS transistor QP23 for clamp on the side of the source of a PMOS transistor QP22. This transistor QP23 is connected to a PMOS transistor QP24 for switch in parallel. The PMOS transistor QP31 and the NMOS transistor QN31 composing an output circuit are driven by the outputs of first and second gate circuits 11 and 12, respectively. A switch control circuit 13 detects that power supply voltage becomes a prescribed level or below and performs on-drive for an NMOS transistor QN14 for switch and a PMOS transistor QP24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS buffer circuit used in an output circuit of a CMOS integrated circuit.

[0002]

2. Description of the Related Art FIG. 9 shows a block structure of a CMOS memory such as a mask ROM. Memory cell array 91 for storing data, row decoder 92 and column decoder 9 for selecting data in this memory cell array 91
3, a sense amplifier 94 for reading the selected memory cell data, an output buffer circuit 95 for taking the read data to an external output terminal, and the like.

With the increase in scale of CMOS memories of this kind, the influence of ground bounce due to simultaneous switching has become a serious problem recently. In the system of FIG. 9, when the sense amplifiers 94 of multiple systems such as 8-bit or 16-bit are simultaneously switched, the source potential of the PMOS transistor is lowered when the PMOS transistor is turned on due to the electromotive force generated in the inductor such as the wiring. , N when the NMOS transistor turns on
The source potential of the MOS transistor rises. These transient changes in the source potential bring about malfunctions in the system such as changing the output logic level and the input logic level.

In order to reduce the influence of noise due to the simultaneous switching as described above, for example, the output buffer circuit 9
A refinement of 5 is made. FIG. 10 shows an example of such an improved output buffer circuit. This output buffer circuit includes a first CMOS inverter 101 including a PMOS transistor QP1 and an NMOS transistor QN1.
And a second CMOS inverter 102 including a PMOS transistor QP2 and an NMOS transistor QN2, and an output stage PMOS transistor QP4 and an NMOS transistor QN4 driven by these inverters 101 and 102, respectively.

NMO of the first CMOS inverter 101
A diode-connected clamp NMOS transistor QN3 is inserted on the source side of the S transistor QN1,
Similarly, a diode-connected clamp PMOS transistor QP3 is inserted on the source side of the PMOS transistor QP2 of the second CMOS inverter 102. Such a configuration is disclosed in, for example, Japanese Patent Laid-Open No. 4-330822.

With this configuration, when the input terminal IN rises and the output of the first CMOS inverter 101 decreases, the clamping NMOS transistor QN3 functions to dull the change, and therefore the output stage PMOS transistor QP4. Rise is suppressed. Similarly, the input terminal IN falls and the second CMOS inverter 102
, The clamping NMOS transistor QP3 acts to dampen that change, and thus the output stage N
The rise of the MOS transistor QN4 is suppressed. By suppressing the rise of the output-stage MOS transistor in this way, it is possible to eliminate the influence of noise due to the simultaneous switching of the sense amplifier in the preceding stage.

[0007]

The circuit system shown in FIG.
It is effective in reducing simultaneous switching noise, but it is a result of sacrificing operating speed. This decrease in operating speed becomes a serious problem especially when the power supply voltage becomes low. For example, recently, a memory for sharing a 3V / 5V power source has been made, but when a low voltage power source of 3V is used, the circuit system of FIG.

The present invention has been made in consideration of the above circumstances, and is intended to reduce simultaneous switching noise and prevent an operating speed from decreasing when the power supply voltage decreases.
An object is to provide a MOS buffer circuit.

[0009]

A CMOS according to the present invention
The buffer circuit is a PMOS transistor or an NMOS
An input stage CMOS gate circuit in which a diode-connected clamp MOS transistor is provided on at least one source side of the transistor, and an output stage CMO in which an input terminal is connected to an output terminal of the input stage CMOS gate circuit
An S inverter, a switch MOS transistor connected in parallel to the clamp MOS transistor, and a switch control circuit that detects that the power supply voltage has dropped to a predetermined level or lower and turns on the switch MOS transistor are provided. It is characterized by that.

The CMOS buffer circuit according to the present invention also includes a first CMOS gate circuit provided with a diode-connected clamp NMOS transistor on the source side of the NMOS transistor, and a diode-connected clamp circuit on the source side of the PMOS transistor. Second CMOS gate circuit having a common PMOS transistor and having an input terminal commonly connected to the first CMOS gate circuit, an output stage PMOS transistor driven by an output of the first CMOS gate circuit, and the first CMOS gate circuit. 2 CMOS
An output circuit in which an output stage NMOS transistor driven by the output of the gate circuit is connected in series, and the first C
The switch NMOS transistor connected in parallel to the clamp NMOS transistor of the MOS gate circuit, the switch PMOS transistor connected in parallel to the clamp PMOS transistor of the second CMOS gate circuit, and the power supply voltage is below a predetermined level. And a switch control circuit for detecting the fact that the switching NMOS transistor and the switching PMOS transistor are turned on.

[0011]

According to the present invention, a clamp MOS transistor is inserted in the CMOS gate circuit of the input stage, and at the same time, a switch MOS transistor for selectively short-circuiting the clamp MOS transistor is provided in parallel with the clamp MOS transistor. . In a normal power supply voltage state, the switching MOS transistor is turned off, and the effect of the simultaneous switching noise can be reduced by the action of the clamping MOS transistor.

When the power supply voltage drops, the switch control circuit detects it and turns on the switching MOS transistor. As a result, the clamp MOS transistor is short-circuited, and the source of the CMOS gate circuit is directly connected to the ground terminal or the power supply terminal. By releasing the clamp function, the operation speed is not reduced due to the power supply voltage reduction, and the high speed performance of the buffer circuit is secured. Moreover, since the simultaneous switching noise also decreases when the power supply voltage decreases, there is no adverse effect of releasing the clamp function. As described above, the CMOS buffer circuit according to the present invention is effective in that it can achieve both noise resistance and high speed performance when applied to a CMOS integrated circuit of 3V / 5V power source sharing type.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a CMOS according to an embodiment of the present invention.
It is a configuration of an output buffer circuit. This CMOS output buffer circuit is used, for example, in a CMOS memory as shown in FIG. In the following description, unless otherwise specified, MOS transistors are enhancement type (E type).

This CMOS output buffer circuit comprises a first CMOS gate circuit 11 and a second CMOS gate circuit 1.
2 and an output stage PMOS transistor QP31 and NMOS transistor QN31 which are respectively driven by the outputs of these CMOS gate circuits 11 and 12. The PMOS transistor QP31 and the NMOS transistor QN31 in the output stage are connected in series between the power supply VDD and the ground, and their drains are commonly connected to the output terminal OUT.

The first CMOS gate circuit 11 is a two-input NAND gate in this embodiment, and has two NMOS transistors QN11 and QN12 connected in series and two PMOS transistors QP11 and QP12 connected in parallel. The gates of the NMOS transistor QN11 and the PMOS transistor QP11 are commonly connected to the input terminal IN, and the gates of the NMOS transistor QN12 and the PMOS transistor QP12 are commonly connected to the output enable terminal OEN.

The second CMOS gate circuit 12 is a two-input NOR gate, and has two PMOS transistors QP21 and QP22 connected in series and two N transistors connected in parallel.
It has MOS transistors QN21 and QN22. NMOS
The gates of the transistor QN21 and the PMOS transistor QP21 are commonly connected to the input terminal IN, and the signal of the output enable terminal OEN is inverted by the inverter I and supplied to the gates of the NMOS transistor QN22 and the PMOS transistor QP22.

A diode-connected clamp NMOS transistor QN13 is inserted between the source of the ground-side NMOS transistor QN12 of the first CMOS gate circuit 11 and the ground terminal. A diode-connected clamp PMOS transistor QP23, which is also diode-connected, is inserted between the source of the PMOS transistor QP22 on the power supply side of the second CMOS gate circuit 12 and the power supply VDD.

One clamp NMOS transistor Q
A switch NMOS transistor QN14 is connected in parallel with N13, and a switch PMOS transistor QP24 is connected in parallel with the other clamp PMOS transistor QP23. NMO for these switches
The S-transistor QN14 and the PMOS transistor QP24 are kept in the off state in a normal power supply state, for example, when VDD = 5V.

A switch control circuit 13 is provided for selectively turning on the switching NMOS transistor QN14 and the PMOS transistor QP24 when the power supply voltage becomes lower than a certain level. The switch control circuit 13 has a drain and a gate commonly connected to the power supply VDD and a source connected to the terminal A, and an NMOS transistor QN42, and the gate and the source are commonly connected between the terminal A and the ground terminal and inserted as a resistor. Depletion type (D
Type) NMOS transistor QN41 constitutes a power supply voltage sense circuit 131. That is, the potential of the terminal A is equal to the threshold of the NMOS transistor QN42 by VTH
, VDD-VTH, and an output that changes according to the power supply VDD is obtained.

The terminal A has an NMOS transistor QN43
And the input terminal of the CMOS inverter composed of the PMOS transistor QP41 and the output terminal B,
NMOS transistor QN44 and PMOS transistor Q
The input terminal of the CMOS inverter composed of P42 is connected. These CMOS inverters include a threshold circuit 1 for determining that the potential of the terminal A has dropped below a predetermined level.
32 are configured. The first inverter output terminal B is the switch N on the first CMOS gate circuit 11 side.
It is connected to the gate of the MOS transistor QN14, and the next inverter output terminal C is connected to the gate of the switching PMOS transistor QP24 on the second CMOS gate circuit 12 side.

The operation of the output buffer circuit thus configured will be described below. Output enable terminal OEN is "L"
When the level is PM in the first CMOS gate circuit 11,
The OS transistor QP12 is on, the output terminal N1 is kept at "H" level, and the second CMOS gate circuit 12
Then, the NMOS transistor QN22 is turned on, and the output terminal N2 is kept at "L" level. Therefore, PM of the output stage
OS transistor QP31 and NMOS transistor QN3
Both 1 are off, that is, the output terminal OUT is kept in a high impedance state.

When the output enable terminal OEN becomes "H" level, when the input terminal IN becomes "H" level,
In the first CMOS gate circuit 11, the NMOS transistors QN11 and QN12 are both on, and the output terminal N1 becomes "L" level. In addition, the second CMOS gate circuit 1
2, the output terminal N2 becomes "L" level because the NMOS transistor QN21 is turned on. As a result, the output stage PMOS transistor QP31 is turned on, the output stage NMOS transistor QN31 is turned off, and the "H" level output is obtained at the final output terminal OUT.

When the input terminal IN goes to "L" level while the output enable terminal OEN is at "H" level, the first CMOS gate circuit 11 causes the NMOS transistor QN1 to operate.
1 is turned off, the output terminal N1 goes to "H" level, and the second
The CMOS gate circuit 12 is a PMOS transistor QP2
Both 1 and QP22 are turned on, and the output terminal N2 becomes "H" level. As a result, the output stage PMOS transistor QP31 is turned off, the output stage NMOS transistor QN31 is turned on, and the "L" level output is obtained at the final output terminal OUT. The above is the basic operation of the output buffer circuit.

Depending on the magnitude of the power supply voltage VDD, the first C
Switching on / off of the switching NMOS transistor QN14 on the MOS gate circuit 11 side and the switching PMOS transistor QP24 on the second CMOS gate circuit 12 side is controlled. As a result, the clamping NMOS transistor QN13 on the side of the first CMOS gate circuit 11 and the second
The operation of the clamping PMOS transistor QP23 on the side of the CMOS gate circuit 12 is controlled. This operation will be described with reference to FIG.

FIG. 7 shows that when the power supply voltage VDD changes,
The relationship between the change in the potential of the terminal A of the switch control circuit 13 and the logic threshold value of the CMOS inverter controlled by the terminal A is shown. D type NM
Since the OS transistor QN41 operates almost constant resistance, the potential of the output terminal A of the sense circuit 131 becomes a value lower than the power supply voltage VDD by the threshold value VTH of the diode-connected NMOS transistor QN42 as shown in the figure. The inverter logic threshold is approximately proportional to the power supply voltage VDD.

Therefore, for example, when the power supply VDD is 5 V or higher, the potential of the terminal A is higher than the logic threshold value of the CMOS inverter, and at this time, the terminal B is at "L" level and the terminal C is at "H" level. As a result, the first CMOS gate circuit 1
The switching NMOS transistor QN14 on the first side and the switching PMOS transistor QP24 on the second CMOS gate circuit 12 side are both off.

In this state, in the output enable state, the input terminal IN rises and the first CMOS gate circuit 1
NMO for clamping when the output terminal N1 of 1 falls
Due to the function of the S transistor QN13, the falling speed of the output terminal N1, and accordingly the output stage PMOS transistor QP31
The turn-on speed of is suppressed. Similarly, input terminal IN
And the output terminal N2 of the second CMOS gate circuit 12 rises, the clamp PMOS transistor QP23 acts to suppress the rising speed of the output terminal N2, and thus the turn-on speed of the output stage NMOS transistor QN31. As a result, the influence of simultaneous switching noise is suppressed.

When the power supply voltage VDD becomes, for example, 3 V, the sense circuit 1 of the switch control circuit 13 as shown in FIG.
The potential of the output terminal A of 31 becomes lower than the logic threshold value of the CMOS inverter. At this time, the threshold circuit 132
The terminal B becomes "H" level and the terminal C becomes "L" level. Therefore, the switching NMOS transistor QN14 on the first CMOS gate circuit 11 side and the switching PMOS transistor QP24 on the second CMOS gate circuit 12 side.
Both are turned on. This allows the clamp NMOS
Both the transistor QN13 and the PMOS transistor QP23 are short-circuited to release the clamp function. By releasing the clamp function, the high-speed performance of the output buffer circuit is secured regardless of the decrease in the power supply voltage.

FIG. 2 shows an embodiment in which the embodiment of FIG. 1 is slightly modified. The difference from FIG. 1 is that the switch control circuit 13
The point is that a threshold circuit 132a in which one stage of a CMOS inverter including a PMOS transistor QP43 and an NMOS transistor QN45 is added is used. The gate of the switching NMOS transistor QN14 on the first CMOS gate circuit 11 side is driven by the final stage output terminal D instead of the terminal B.

In the circuit of FIG. 1, the switch control circuit 1
Assuming that the potential of the terminal A of 3 is slightly lower than the inverter logic threshold value, the terminal B does not become the "H" level sufficiently but remains at the intermediate level. Then, the switch NMOS transistor QN14 is not turned on sufficiently deeply, and the release of the clamp function remains halfway. Figure 2
According to the embodiment, even if the terminal B is not up to VDD,
Further, by passing the CMOS inverter of two stages, the terminal D becomes a value sufficiently close to VDD. Therefore, the switching NMOS transistor QN14 is clearly switched on / off.

FIG. 3 shows a modification of the embodiment of FIG. In the switch control circuit 13 of this embodiment, the E-type NMOS transistor QN42 and the D-type NMOS transistor QN41 are arranged as the sense circuit 131a in the opposite arrangement to that of FIG. That is, the E-type NMOS transistor QN42
The source is grounded, the gate and the drain are common, and the gate and the source are connected to the power source through a D-type NMOS transistor QN41 as a resistor. Along with this, the terminal C is connected to the gate of the switching NMOS transistor QN14 on the first CMOS gate circuit 11 side, and the terminal D is connected to the second CMOS gate circuit 1.
It is connected to the gate of the switching PMOS transistor QP24 on the second side.

As shown in FIG. 8, the power supply dependency of the terminal A of the switch control circuit 13 is opposite to that in the case of FIG. 7 of the previous embodiment. That is, in the sense circuit 131a of the switch control circuit 13, the terminal A is connected to the NMOS transistor QN42 when the power supply voltage VDD is higher than a certain level due to the constant resistance characteristic of the D-type NMOS transistor QN41 and the diode-connected E-type NMOS transistor QN42. Threshold V
It is a constant voltage determined by TH. The fact that the inverter logic threshold value changes according to the power supply voltage VDD is the same as in the previous embodiment.

Therefore, for example, when the power supply voltage VDD is 5V,
Contrary to the previous embodiment, the terminal C becomes "L" level and the terminal D becomes "H" level. At this time, the switching NMOS transistor QN14 on the first CMOS gate circuit 11 side,
PMOS for switch on the second CMOS gate circuit 12 side
Both transistors QP24 are off. When the power supply voltage VDD becomes, for example, 3 V, the terminal C becomes "H" level and the terminal D becomes "L" level, and the clamp function is released as in the previous embodiment.

FIG. 4 shows an output buffer circuit of the embodiment in which the output enable terminal OEN is eliminated. First CMOS
The gate circuit 11a is a CMOS inverter gate obtained by removing the PMOS transistor QP12 and the NMOS transistor QN12 controlled by the output enable terminal OEN from the first CMOS gate circuit 11 of the embodiment of FIG. Similarly, the second CMOS gate circuit 12 a outputs the output enable terminal OEN from the second CMOS gate circuit 12.
PMOS transistors QP22 and NM controlled by
CMOS inverter without OS transistor QN22
It is a gate.

Also in this embodiment, similarly to the previous embodiment, ON / OFF control of the clamp function is performed according to the power supply level, and therefore the same effect as in the previous embodiment can be obtained.
Needless to say, in the embodiment of FIG. 4, the switch control circuit 13 having the structure shown in the embodiment of FIG. 2 or 3 can be used for the switch control circuit 13.

FIG. 5 is a modification of the embodiment of FIG. 4 in which only the first CMOS gate circuit 11a is left in the input stage.
It is an example of a MOS buffer. The gates of the output stage MOS transistors QP31 and QN31 are commonly connected to the output terminal N1 of the input stage CMOS gate circuit 11a. According to this embodiment, it is possible to obtain a delay buffer in which a certain delay is provided when the input terminal IN rises, and the delay function of the clamp circuit can be turned on / off according to the power supply level.

FIG. 6 is also a modification of the embodiment of FIG.
This is an embodiment of a CMOS buffer in which only the second CMOS gate circuit 12a remains in the input stage. According to this embodiment, a constant delay is provided when the input terminal IN falls,
Further, it is possible to obtain a delay buffer in which the delay function of the clamp circuit can be turned on / off according to the power supply level.
In the embodiment of FIGS. 5 and 6, it is of course possible to use the switch control circuit 13 of the system used in the embodiment of FIG.

[0038]

As described above, according to the present invention, a clamping MOS transistor is inserted in the input-stage CMOS gate circuit, and a switching MOS transistor is provided in parallel with the clamping MOS transistor. In the power supply voltage state, the effect of simultaneous switching noise can be reduced by the action of the clamping MOS transistor. When the power supply voltage drops, the switching MO transistor can be used.
By turning on the S-transistor and releasing the clamp function, it is possible to obtain a CMOS buffer circuit capable of ensuring high-speed performance regardless of a decrease in the power supply voltage.

[Brief description of drawings]

FIG. 1 shows a CMOS output buffer circuit according to an embodiment of the present invention.

FIG. 2 shows a CMOS output buffer circuit according to another embodiment of the present invention.

FIG. 3 shows a CMOS output buffer circuit according to still another embodiment of the present invention.

FIG. 4 shows a CMOS output buffer circuit according to still another embodiment of the present invention.

FIG. 5 shows a CMOS buffer circuit according to another embodiment of the present invention.

FIG. 6 shows a CMOS buffer circuit according to another embodiment of the present invention.

FIG. 7 is a diagram for explaining the circuit operation of the embodiment of FIG.

FIG. 8 is a diagram for explaining the circuit operation of the embodiment of FIG.

FIG. 9 shows a block configuration of a CMOS memory.

FIG. 10 shows an output buffer circuit of a conventional CMOS memory.

[Explanation of symbols]

11 ... First CMOS gate circuit, 12 ... Second CMO
S gate circuit, 13 ... Switch control circuit, 131, 13
1a ... Power supply voltage sense circuit, 132, 132a ... Threshold circuit, QP31 ... Output stage PMOS transistor, QN31
… Output stage NMOS transistor, QN13… N for clamping
MOS transistor, QP23 ... Clamping PMOS transistor, QN14 ... Switch NMOS transistor,
QP24… PMOS transistor for switch.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/822 H03K 19/003 Z H01L 27/04 M

Claims (4)

[Claims] 1. An input-stage CMOS gate circuit provided with a diode-connected clamp MOS transistor on the source side of at least one of a PMOS transistor and an NMOS transistor, and an input terminal connected to an output terminal of this input-stage CMOS gate circuit. Output stage CMOS inverter, switching MOS transistor connected in parallel with the clamping MOS transistor, and a switch control circuit for detecting that the power supply voltage has dropped below a predetermined level and turning on the switching MOS transistor. A CMOS buffer circuit comprising: 2. A first CMOS gate circuit having a diode-connected clamp NMOS transistor provided on the source side of the NMOS transistor, and a diode-connected clamp PMOS transistor provided on the source side of the PMOS transistor. A second CMOS gate circuit having an input terminal commonly connected to the first CMOS gate circuit, an output stage PMOS transistor driven by the output of the first CMOS gate circuit, and an output of the second CMOS gate circuit. An output circuit in which a driven output stage NMOS transistor is connected in series, a switching NMOS transistor connected in parallel with the clamping NMOS transistor of the first CMOS gate circuit, and a clamping of the second CMOS gate circuit PMOS transistor Connected in parallel with PMOS transistor switch, detects and PMO NMOS transistor and the switch for the switch that the power supply voltage falls below a predetermined level
A CMOS buffer circuit comprising: a switch control circuit for turning on an S transistor. 3. The switch control circuit comprises an enhancement type NMOS transistor having a threshold value of VTH, whose gate and drain are commonly connected to a power source, and a resistor connected between the source of this transistor and ground. And a threshold circuit for determining the output voltage of the sense circuit by a predetermined logic threshold value. The sense circuit outputs a voltage VDD-VTH with respect to the power supply voltage VDD.
Alternatively, the CMOS buffer circuit described in 2. 4. The switch control circuit comprises an enhancement type NMOS transistor having a threshold value of VTH, a source of which is grounded, and a gate and a drain of which are commonly connected to a power source through a resistor, and a variation of the power source voltage. 3. A sense circuit which outputs a voltage VTH within a range, and a threshold circuit which determines an output voltage of the sense circuit by a predetermined logic threshold value.
Alternatively, the CMOS buffer circuit described in 2.