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JPH09106994A - Microwave transistor - Google Patents

Microwave transistor

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Publication number
JPH09106994A
JPH09106994A JP26509095A JP26509095A JPH09106994A JP H09106994 A JPH09106994 A JP H09106994A JP 26509095 A JP26509095 A JP 26509095A JP 26509095 A JP26509095 A JP 26509095A JP H09106994 A JPH09106994 A JP H09106994A
Authority
JP
Japan
Prior art keywords
gate
input point
phase difference
finger
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26509095A
Other languages
Japanese (ja)
Other versions
JP2739851B2 (en
Inventor
Takaharu Matsunaga
高治 松永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7265090A priority Critical patent/JP2739851B2/en
Publication of JPH09106994A publication Critical patent/JPH09106994A/en
Application granted granted Critical
Publication of JP2739851B2 publication Critical patent/JP2739851B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a power feeding method that enables unit microwave transistors of comb-shaped structure to be set zero in phase difference between them, prevents deteriorating in gain, and keeps high output. SOLUTION: Provided that the m-th gate finger 5 from an input point is Zum in length, and a gate pitch is represented by GP, an electric length difference ΔL2 between a gate (first) nearest to the input point and a farthest gate (m-th) from the input point is represented by a formula, ΔL2=2(m-1)GP +2(Zum-Zu1), where M is an integer above 1. Therefore, the gate fingers 5 are varied in length Zum, whereby ΔL2 can be reduced to zero. By this setup, signals can be set identical to each other in phase from an input point, so that a problem of phase difference can be solved. Moreover, a gate bus line 4 and bypass wire 7 are provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、櫛形構造のマイク
ロ波トランジスタにおいて、単位トランジスタの間の位
相差をなくすと同時に、高出力を維持しつつ、さらに利
得の低下を防止する給電方法を提供することに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a power supply method for a microwave transistor having a comb structure, which eliminates a phase difference between unit transistors, maintains a high output, and prevents a decrease in gain. About things.

【0002】[0002]

【従来の技術】高周波電力用を目的とした高出力トラン
ジスタにおいては、大出力を得るために、多くのセルを
横方向に結合させる方法をとっている。しかしながら、
多くのセルを有する素子においては、入力点から最も近
いセルと最も遠いセル間での位相差の問題が生じ、素子
特性が劣化することがある。この問題を解決するため
に、図4の従来例にあるようにゲート3の方向にバイパ
ス線を伸ばし、極力横方向にセル6が拡大しないように
した構造がある。このような方法により、同ゲート3の
幅で横方向のみにセル6を拡大したものよりも位相差を
低減でき、合成効率の大きな素子を構成することができ
る。
2. Description of the Related Art In a high-output transistor intended for high-frequency power, in order to obtain a large output, a method of connecting many cells in a lateral direction is employed. However,
In a device having many cells, a problem of a phase difference between a cell closest to the input point and a cell farthest from the input point may occur, and the device characteristics may be degraded. To solve this problem, there is a structure in which the bypass line is extended in the direction of the gate 3 so that the cell 6 is prevented from expanding in the lateral direction as much as possible, as in the conventional example of FIG. According to such a method, the phase difference can be reduced as compared with the case where the cell 6 is expanded only in the horizontal direction by the width of the gate 3, and an element having a high synthesis efficiency can be configured.

【0003】なお、1はドレイン、2はソース、8は入
力点、9は出力点である。
[0003] 1 is a drain, 2 is a source, 8 is an input point, and 9 is an output point.

【0004】なお、この種の従来の技術として、次のも
のを挙げることができる。
Incidentally, the following can be cited as this kind of conventional technology.

【0005】(1)高周波用電界効果トランジスタにお
いて、チップの短辺方向に複数本のゲートバスラインと
ドレインバスラインを延設し、かつ、各バスラインから
それぞれチップの長辺方向に延びるフィンガーを突出さ
せることで、FETチップ長に対するゲートバスライン
の長さを短くし、FETチップにおける位相差による出
力の低下を抑えることができる。又、各セルにおいて
は、ゲート電極とドレイン電極との間の経路を均一化
し、位相差による出力の合成損失を低減させることがで
きる(特開平5−251479号公報)。
(1) In a high frequency field effect transistor, a plurality of gate bus lines and drain bus lines are extended in the short side direction of the chip, and fingers extending from the respective bus lines in the long side direction of the chip are provided. By projecting, the length of the gate bus line with respect to the length of the FET chip can be shortened, and a decrease in output due to the phase difference in the FET chip can be suppressed. Further, in each cell, the path between the gate electrode and the drain electrode can be made uniform, and the combined loss of the output due to the phase difference can be reduced (JP-A-5-251479).

【0006】(2)電界効果トランジスタの構造におい
て、入力端子をゲート・インピーダンス変換部の一端
に、出力端子を該ゲート・インピーダンス変換部の一端
から最も遠くなる、該ドレイン・インピーダンス変換部
の他端に設け、該入力端子から異なる経路を通って出力
端子に到着した信号の位相が同相となるように構成する
(特開平6−151471号公報)。
(2) In the structure of the field-effect transistor, the input terminal is connected to one end of the gate-impedance converter, and the output terminal is connected to the other end of the drain-impedance converter which is farthest from one end of the gate-impedance converter. (See Japanese Patent Laid-Open No. 6-151471).

【0007】(3)ドレイン、ゲート、ソースの各電極
が交互に配置され、かつ配線により接続されたフィンガ
ー構造のマイクロ波集積回路の能動素子であって、前記
能動素子は、信号伝播方向に対し、垂直に配置されたフ
ィンガーを複数本形成してなるマイクロ波集積回路素子
(特開平3−289143号公報)。
(3) An active element of a microwave integrated circuit having a finger structure in which electrodes of a drain, a gate and a source are alternately arranged and connected by wiring, wherein the active element is in the signal propagation direction. , A microwave integrated circuit element formed by forming a plurality of vertically arranged fingers (Japanese Patent Laid-Open No. 3-289143).

【0008】[0008]

【発明が解決しようとする課題】この方法をとると、図
5に示すように、同じゲート幅を有する時、横方向の広
がりを通常の半分に抑えられる。入力点から最も遠い1
段目、2段目のゲートを通る信号の出力点より見た電気
長(位相)は同相となる。しかしながら、1段目におい
て入力点から最も近いゲート(1番目)と、最も遠いゲ
ート(m番目)の電気長差ΔL1は、ゲートピッチをG
pとすると、 ΔL1=2(m−1)Gp、 m>1、整数(フィンガ
ー数) となるため、常にΔL1≠0となり、位相差の問題は解
決できていないという課題があった。
According to this method, as shown in FIG. 5, when the gate width is the same, the lateral spread can be suppressed to half of the normal width. 1 farthest from the input point
The electrical lengths (phases) viewed from the output points of the signals passing through the gates at the second and the second stages are in phase. However, in the first stage, the electrical length difference ΔL1 between the gate closest to the input point (first) and the farthest gate (mth) is represented by the gate pitch G
Assuming that p, ΔL1 = 2 (m−1) Gp, m> 1, and an integer (number of fingers), so that ΔL1 ≠ 0 always holds, and the problem of the phase difference cannot be solved.

【0009】さらに、図6にあるように、基本セル構造
より、高出力化をねらってマルチセル化した場合におい
ても、セル間における位相差も顕著になるという問題が
あった。
Further, as shown in FIG. 6, there is a problem that the phase difference between cells becomes more remarkable even when multi-cells are formed for higher output than the basic cell structure.

【0010】そこで、本発明は、前記従来の技術の欠点
を改良し、単位トランジスタの間の位相差をなくすと同
時に、高出力を維持しつつ、さらに利得の低下を防止す
るマイクロ波トランジスタを提供しようとするものであ
る。
Accordingly, the present invention provides a microwave transistor which improves the drawbacks of the prior art, eliminates the phase difference between unit transistors, and maintains a high output while preventing a decrease in gain. What you want to do.

【0011】[0011]

【課題を解決するための手段】本発明は、大出力を発生
する櫛形構造のマイクロ波トランジスタにおいて、セル
6の横方向の広がりを抑えるために、ゲート3方向にバ
イパス線7を伸ばし2段構成にすると同時に、各段にお
いて隣同士のゲートフィンガー5長を変化させることを
特徴としたトランジスタ構造を提供するものである。
According to the present invention, in a microwave transistor having a comb structure which generates a large output, a bypass line 7 is extended in the direction of the gate 3 in order to suppress the lateral expansion of the cell 6, and a two-stage structure is provided. At the same time, there is provided a transistor structure characterized in that the length of adjacent gate fingers 5 is changed in each stage.

【0012】[0012]

【作用】次に、本発明の作用について述べる。上述した
手段によれば、まず、ゲート3のバスライン4をゲート
フィンガー5方向に2本平行に配置するために、同じ総
ゲートを有する通常の横方向に拡大した構造よりも、最
も遠いフィンガーにおける位相差を小さくできる。さら
に各ゲートフィンガー5のフィンガー長を中心よりゲー
トピッチの長さに相当する量だけ順番に短く配置するこ
とにより、全フィンガーにおける位相差を完全にゼロに
することができる。従って、素子の高周波特性などが著
しく向上する。
Next, the operation of the present invention will be described. According to the above-described means, firstly, in order to arrange two bus lines 4 of the gate 3 in the direction of the gate finger 5, the bus line 4 at the farthest finger is larger than the usual laterally enlarged structure having the same total gate. The phase difference can be reduced. Further, by arranging the finger lengths of the respective gate fingers 5 shorter than the center by an amount corresponding to the length of the gate pitch in order, the phase difference between all the fingers can be made completely zero. Therefore, the high-frequency characteristics and the like of the element are significantly improved.

【0013】[0013]

【発明の実施の形態】図1に本発明のマイクロ波トラン
ジスタの構造の一実施形態を示す。図2は、本発明のマ
イクロ波トランジスタのゲート構造の一実施形態の外観
を現した図である。入力点8よりm番目のゲートフィン
ガー長をZumとすると、入力点から最も近いゲート
(1番目)と、最も遠いゲート(m番目)の電気長差Δ
L2は、ゲートピッチをGpとすると、 ΔL2=2(m−1)Gp+2(Zum−Zu1)、
m>1、整数 となる。従って、各ゲートフィンガー長Zumを変化さ
せることにより、完全にΔL2を0にすることが可能と
なる。また、図3にあるように、基本セル構造より、高
出力化をねらってマルチセル化した場合においても、位
相差を完全にゼロにすることが可能になる。
FIG. 1 shows an embodiment of the structure of a microwave transistor according to the present invention. FIG. 2 is a diagram showing the appearance of an embodiment of the gate structure of the microwave transistor of the present invention. Assuming that the m-th gate finger length from the input point 8 is Zum, the electrical length difference Δ between the gate closest to the input point (first) and the gate farthest (m-th) is Δ
L2 is: ΔL2 = 2 (m−1) Gp + 2 (Zum−Zu1), where Gp is the gate pitch.
m> 1, an integer. Therefore, by changing each gate finger length Zum, ΔL2 can be completely set to zero. In addition, as shown in FIG. 3, even when a multi-cell configuration is used for higher output than the basic cell structure, the phase difference can be made completely zero.

【0014】[0014]

【発明の効果】以上の説明から明らかなように、本発明
によれば、入力点から見た信号の位相が各フィンガーで
同相になることを示しており、位相差の問題は解決され
る。さらにゲートの横方向の広がりを2段構成にするこ
とにより抑えているために、総ゲート幅を大きく保った
まま、位相差に起因する出力の低下、利得の劣化さらに
合成損失の低下を著しく低減している。本構造は、マイ
クロ波トランジスタにおいて利得を劣化させないで、大
出力を得るところに寄与すること大である。この方法
は、特にマイクロ波トランジスタの大出力化において効
果のある方法である。
As is apparent from the above description, according to the present invention, it is shown that the phase of the signal as viewed from the input point becomes the same in each finger, and the problem of the phase difference is solved. Further, since the lateral spread of the gate is suppressed by using a two-stage configuration, a reduction in output, a deterioration in gain, and a reduction in combined loss due to a phase difference are significantly reduced while maintaining a large total gate width. doing. This structure largely contributes to obtaining a large output without deteriorating the gain of the microwave transistor. This method is particularly effective in increasing the output of a microwave transistor.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のマイクロ波トランジスタの一実施形態
の平面図である。
FIG. 1 is a plan view of one embodiment of a microwave transistor of the present invention.

【図2】本発明のマイクロ波トランジスタの一実施形態
におけるゲート構造の平面図である。
FIG. 2 is a plan view of a gate structure in one embodiment of the microwave transistor of the present invention.

【図3】本発明のマイクロ波トランジスタのマルチセル
構造の一実施形態の平面図である。
FIG. 3 is a plan view of an embodiment of the multi-cell structure of the microwave transistor of the present invention.

【図4】従来のマイクロ波トランジスタの平面図であ
る。
FIG. 4 is a plan view of a conventional microwave transistor.

【図5】従来のマイクロ波トランジスタのゲート構造の
平面図である。
FIG. 5 is a plan view of a gate structure of a conventional microwave transistor.

【図6】従来のマイクロ波トランジスタのマルチセル構
造の平面図である。
FIG. 6 is a plan view of a multi-cell structure of a conventional microwave transistor.

【符号の説明】[Explanation of symbols]

1 ドレイン 2 ソース 3 ゲート 4 ゲートのバスライン 5 ゲートフィンガー 6 セル 7 バイパス線 8 入力点 9 出力点 DESCRIPTION OF SYMBOLS 1 Drain 2 Source 3 Gate 4 Gate bus line 5 Gate finger 6 Cell 7 Bypass line 8 Input point 9 Output point

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 ドレイン、ソース、ゲートの各電極が交
互に配置され、かつ、配線により接続されたフィンガー
構造のトランジスタにおいて、前記トランジスタは、ゲ
ートのバスラインをゲートフィンガー方向に2本平行に
つけ、かつ、中心部分よりバスラインの端までの各フィ
ンガーのフィンガー長を順番にゲートピッチだけ短くし
た構造を有することを特徴とするマイクロ波トランジス
タ。
1. A finger structure transistor in which electrodes of a drain, a source, and a gate are alternately arranged and connected by wiring, wherein the transistor has two bus lines of the gate arranged in parallel with each other in a gate finger direction. A microwave transistor having a structure in which a finger length of each finger from a central portion to an end of a bus line is sequentially shortened by a gate pitch.
【請求項2】 ゲートのバスラインを2段構成としたこ
とを特徴とする請求項1記載のマイクロ波トランジス
タ。
2. The microwave transistor according to claim 1, wherein the gate bus line has a two-stage structure.
【請求項3】 セルをゲートのバスラインの方向に複数
個配列したマルチセル構造としたことを特徴とする請求
項1記載のマイクロ波トランジスタ。
3. The microwave transistor according to claim 1, wherein a plurality of cells are arranged in the direction of the bus line of the gate to have a multi-cell structure.
JP7265090A 1995-10-13 1995-10-13 Microwave transistor Expired - Fee Related JP2739851B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7265090A JP2739851B2 (en) 1995-10-13 1995-10-13 Microwave transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7265090A JP2739851B2 (en) 1995-10-13 1995-10-13 Microwave transistor

Publications (2)

Publication Number Publication Date
JPH09106994A true JPH09106994A (en) 1997-04-22
JP2739851B2 JP2739851B2 (en) 1998-04-15

Family

ID=17412465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7265090A Expired - Fee Related JP2739851B2 (en) 1995-10-13 1995-10-13 Microwave transistor

Country Status (1)

Country Link
JP (1) JP2739851B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7689946B2 (en) 2006-10-19 2010-03-30 International Business Machines Corporation High-performance FET device layout
US7791160B2 (en) 2006-10-19 2010-09-07 International Business Machines Corporation High-performance FET device layout
US10355130B2 (en) 2015-02-04 2019-07-16 Mitsubishi Electric Corporation Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110326091B (en) 2017-02-27 2023-05-23 新唐科技日本株式会社 Transistors for High Frequency

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291071A (en) * 1986-06-10 1987-12-17 Nec Corp Field-effect transistor
JPH03289143A (en) * 1990-04-05 1991-12-19 Matsushita Electron Corp Microwave integrated circuit element
JPH05251479A (en) * 1991-11-27 1993-09-28 Nec Corp Field effect transistor for high frequency
JPH0729918A (en) * 1993-07-08 1995-01-31 Sumitomo Electric Ind Ltd High frequency field effect transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291071A (en) * 1986-06-10 1987-12-17 Nec Corp Field-effect transistor
JPH03289143A (en) * 1990-04-05 1991-12-19 Matsushita Electron Corp Microwave integrated circuit element
JPH05251479A (en) * 1991-11-27 1993-09-28 Nec Corp Field effect transistor for high frequency
JPH0729918A (en) * 1993-07-08 1995-01-31 Sumitomo Electric Ind Ltd High frequency field effect transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7689946B2 (en) 2006-10-19 2010-03-30 International Business Machines Corporation High-performance FET device layout
US7791160B2 (en) 2006-10-19 2010-09-07 International Business Machines Corporation High-performance FET device layout
US10355130B2 (en) 2015-02-04 2019-07-16 Mitsubishi Electric Corporation Semiconductor device

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