JPH09102772A - Atm-stm conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output an accurate STM output signal without increasing the delay of data at a conversion part by preventing the overflow or underflow of a data memory circuit despite input of the fluctuation that is larger than the estimated value when the width of delay variance is large. SOLUTION: An up-down counter 21 of a fluctuation calculation circuit 2 calculates the fluctuation value of an ATM input signal. A latch circuit 22 selectively holds the maximum absolute value of fluctuation while the fluctuation value is measured. An adder 23 adds the fixed value (ta) to the maximum absolute value of fluctuation. A comparator 31 of an (x) cell write decision circuit 3 monitors the ATM input signal based on the addition value of the adder 23. When the cells equal to the addition value are inputted, a read start signals is outputted to a read address counter 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM / STM converter, and more particularly to an ATM (Asynchronous).
ATM / STM (Synchronous) of a device that performs data communication using a transmission mode network
The present invention relates to a decellization unit of a transmission mode conversion unit.

[0002]

2. Description of the Related Art Since an ATM signal rides on an information transmission basket called an ATM cell and is sent to a partner device, jitter (jitter) is generated every time it passes through a cross-connect device and a cell multiplexing device in an ATM network. Will end up.

On the other hand, the STM signal is an isochronous signal which does not cause fluctuation like the ATM signal, and is a signal which must keep the continuity and periodicity of information constant.

In the ATM / STM conversion circuit for converting the ATM signal and the STM signal, the ATM signal is temporarily stored, and the stored data is read out at an isochronous timing without fluctuation, so that the ATM signal and the STM signal can be read. Is being converted. In that case, as a circuit for temporarily storing the ATM signal, a buffer memory [for example, a FIFO (first-in first-out) memory] capable of sequentially writing and sequentially reading and absorbing delay variation is used.

In a communication system that operates as described above, as shown in FIG. 4, a DTE (Data Ter
DCE (Data Circuits ter) connected to the minal equipments 11 and 16, respectively.
minal equipment) 12, 15 and ATM
/ STM converters 13 and 14 and subscriber transmission line 201,
Connections are made at 202 to form an STM network. This STM
In the network part, ST is transmitted via subscriber transmission lines 201 and 202.
Data communication is performed by M signal.

Also, the ATM / STM converters 13 and 14
An ATM network is formed by connecting these via a relay transmission line 200. In this ATM network portion, data communication is performed by an ATM signal via the relay transmission line 200. In the ATM network, a cross route and a multiplexing function are used to change a path route and a path storage in data communication.

When passing through the ATM network, since the cross-connect and multiplexing functions operate on a cell-by-cell basis, delay variation occurs with respect to the reference phase. For example, as shown in FIG. 3, when cells A to E appear on an ATM input signal, cell B has a cell fluctuation amount of + t1, cell C has a cell fluctuation amount of −t1, and cell D has a cell fluctuation amount of −t2. As for the fluctuation amount, the cell fluctuation amount of + t2 may occur in the cell E, respectively.

This delay variation + t1, -t1, -t2, +
The amount of traffic t2 is usually determined by the amount of traffic in the ATM network, but the variation width of the delay variation may change greatly even when the number of passage stages such as the path route and cross connect is changed.

In the hardware for converting such a signal, it is necessary to determine the required storage amount (buffer amount) in the data memory circuit and the reading start point in the data memory circuit.

[0010]

SUMMARY OF THE INVENTION The conventional ATM described above.
In the / STM conversion circuit, when the fluctuation width of the delay fluctuation greatly changes due to a change in the number of pass stages such as the path route or the cross connect, the required storage amount in the data memory circuit and the read start point in the data memory circuit are set in hardware. Although it can be dealt with by changing it, if a fluctuation more than expected is input, the data memory circuit overflows or underflows, and an accurate STM output signal cannot be output.

In order to avoid this phenomenon, the required storage amount in the data memory circuit may be set to a large value in advance. However, if the required storage amount in the data memory circuit is increased, the data delay in the conversion section will increase. New problems arise.

Japanese Patent Laid-Open No. 5-244186 discloses AT
In a circuit that controls the reading of the buffer by comparing a buffer having a capacity of twice the maximum fluctuation time in the M network with a preset threshold value with the number of cells in the buffer,
An example in which the contents of the buffer are sequentially read after the maximum delay time in the ATM network after the arrival of the first cell is described in detail.

In this example, by adopting the above-mentioned configuration, it is possible to realize the fluctuation absorption which is economical and has a small delay time, and to minimize the jitter of the decellized signal. However, in this example, the frequency on the lead side is ± Δ
Since it may change f, it cannot be applied to a device that transmits output data via a subscriber transmission line. That is, the signal speed in the transmission line interface is the only absolute one, and the frequency fluctuation generated in the circuit is not allowed.

Further, the preset threshold value can be changed within a range of ± 1, but the change is for preventing abnormal operation. Therefore, the threshold for the cell fluctuation is fixed, and this threshold cannot be changed significantly. Therefore, the above example is applied to the AT of the system in which the delay variation such as the change of the path route in the ATM network may change significantly.
It cannot be applied to M / STM converters.

Therefore, an object of the present invention is to solve the above-mentioned problems and prevent the data memory circuit from overflowing or underflowing even if an undesired fluctuation is input when the fluctuation width of the delay fluctuation greatly changes. However, it is another object of the present invention to provide an ATM / STM conversion device that can output an accurate STM output signal without increasing the data delay in the conversion unit.

[0016]

An ATM / S according to the present invention.
The TM conversion device is an ATM / STM conversion device including a data buffer for converting cell data input via an asynchronous transfer mode transmission line into synchronous transfer mode data, the asynchronous transfer mode transmission line In the measuring means for measuring the fluctuation amount of the cell data in, the detection means for detecting that the cell data is input at least the fluctuation amount measured by the measuring means, and based on the detection result of the detecting means, And a means for reading data from the data buffer.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

A fixed value is added by an adder to the maximum absolute value of the cell fluctuation amount measured before the actual data communication in the fluctuation calculation circuit, and the cell input is started, and the input of the added amount of cells is x cell write. When it is detected by the judgment circuit, the reading of the STM output signal from the data memory circuit is started.

This prevents the data memory circuit from overflowing or underflowing even if fluctuations larger than expected are input when the fluctuation width of the delay fluctuations greatly changes, resulting in an increase in data delay in the conversion unit. Therefore, an accurate STM output signal can be output.

Further, since the signal speed of the STM output signal does not change, the ATM / STM converter described above can be applied even where the STM side is not allowed to change the speed of a digital transmission line or the like.

Furthermore, since the variable range of the threshold value can be set large within the range of the capacity of the data memory circuit,
It is possible to cope with cell fluctuations (delay fluctuations) that greatly change when the ATM path route is changed in the ATM network.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention. In the figure, ATM /
The STM converter is a data memory circuit (variable length buffer)
1, fluctuation calculation circuit 2, x-cell write determination circuit 3
And a write address (WADR) counter 4 and a read address (RADR) counter 5. The write address counter 4 and the read address counter 5 may be provided in the data memory circuit 1.

The fluctuation calculation circuit 2 is up / down (UP /
DOWN) counter 21, a latch circuit 22, and an adder 23, and the x-cell write determination circuit 3 is composed of a comparator 31.

The up / down counter 21 of the fluctuation calculation circuit 2 calculates the fluctuation amount of the ATM input signal 100, which is incremented when the reference phase (T0) 102 is input and decremented when a cell appears on the ATM input signal 100. Then, the fluctuation amount of the cell, which is the counting result, is output to the latch circuit 22.

The latch circuit 22 selectively holds the maximum absolute value in the fluctuation amount from the up / down counter 21 during the fluctuation amount measuring period (while the start signal 103 is on), and holds the maximum value. The absolute value is output to the adder 23.

The adder 23 adds the fixed value ta to the maximum absolute value from the latch circuit 22, and outputs the added value 104 to the x cell write determination circuit 3. In this case, the fixed value ta is a value that the maximum absolute value from the latch circuit 22 was originally measured during a certain period and has no margin. Therefore, if the maximum absolute value is used as it is, the data memory circuit 1
There is a risk of underflow or overflow of. In order to avoid the risk, the adder 23 adds the fixed value ta as a margin to the maximum absolute value.

The comparator 31 of the x-cell write determination circuit 3 is based on the added value 104 from the adder 23 and the ATM input signal 10
When 0 is monitored and only the added value 104 is input to the cell, the read start signal 105 is output to the read address counter 5. The read start signal 105 is output only when the cell for the added value 104 is first input after the cell is input.

The ATM input signal 100 is written in the data memory circuit 1 by the write address 106 from the write address counter 4, read from the data memory circuit 1 by the read address 107 from the read address counter 5, and is output as the STM output signal 101. Is output.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

In one embodiment of the present invention, before actually transmitting an ATM signal using a relay transmission line, the fluctuation calculation circuit 2 uses a test cell to measure the amount of cell fluctuation in the relay transmission line.

In this case, the up / down counter 21 of the fluctuation calculating circuit 2 is incremented when the reference phase (T0) 102 is input and decremented when a cell appears on the ATM input signal 100. Therefore, when the count value of the up / down counter 21 is “0”, the reference phase (T0)
When a cell appears later, "+1" is counted, and when the count value is "0", a cell appears before the reference phase (T0), and "-1" is counted.

The latch circuit 22 receives the fluctuation amount (count value) from the up / down counter 21 during the fluctuation amount measuring period.
Among them, the maximum absolute value is selectively retained and the retained maximum absolute value is output to the adder 23.

In FIG. 2, the fluctuation amount from the up / down counter 21 to the latch circuit 22 is "0", "+1",
"0", "+1", "0", "-1", "0", "+"
1 "," 0 "," -1 "," -2 "," -3 ","-"
2 "," -3 "," -4 "," -5 "," -4 ", ...
Since they are output in the order of, "-5" is the maximum value. Therefore, the latch circuit 22 outputs “5” as the maximum absolute value to the adder 23.

The adder 23 adds the fixed value ta to the maximum absolute value "5" from the latch circuit 22 and outputs the added value 104 to the x cell write determination circuit 3. In this case, the fixed value ta is a value that the maximum absolute value from the latch circuit 22 was originally measured during a certain period and has no margin. Therefore, if the maximum absolute value is used as it is, the fixed value ta of the data memory circuit 1 is not changed. There is a risk of underflow or overflow. In order to avoid the risk, the adder 23 adds the fixed value ta as a margin to the maximum absolute value. Since the fixed value ta is set to "1" in this embodiment, the added value x is sent from the adder 23 to the x cell write determination circuit 3.
Is output as 5 + 1 = 6.

The comparator 31 of the x-cell write determination circuit 3 uses the ATM input signal 10 based on the added value "6" from the adder 23.
When 0 is monitored and the added value "6" is input to the cell, the read start signal 105 is output to the read address counter 5.

When the read start signal 105 is input, the read address counter 5 outputs the read address 107 to the data memory circuit 1 and starts reading the STM output signal 101 from the data memory circuit 1. Therefore,
Since the staying number of cells in the data memory circuit 1 varies between +1 and +11, underflow or overflow of the data memory circuit 1 does not occur.

The start signal 103 shown in FIG.
This is used when the latch circuit 22 and the comparator 31 are initialized and restarted when the M-pass route is changed, etc. The amount of cell fluctuation is measured in the high level section of the start signal 103, and the low level section is measured. The actual data communication is now being carried out.

As described above, in one embodiment of the present invention, it is necessary to measure the cell fluctuation amount prior to the actual data communication. However, when the ATM path route is changed or the like originally, it is used for the test in the ATM network. OAM (Operating
n, Administration Maintenan
ce) The operation test is conducted by flowing cells etc.
If an M cell or the like is used as a test cell, it is possible to measure the cell fluctuation amount prior to actual data communication.

Further, in the embodiment of the present invention, a large capacity FIFO memory is required as the data memory circuit 1,
At present, image FIFO memory ICs that do not require address control from the outside are commercially available. Therefore, the data memory circuit 1 can be relatively easily configured by using the image FIFO memory.

As described above, the adder 23 adds the fixed value ta to the maximum absolute value of the cell fluctuation amount measured before the actual data communication in the fluctuation calculation circuit 2, and the cell input is started and the added value x minutes are added. By starting the reading of the STM output signal 101 from the data memory circuit 1 when the input of the cell is detected by the x-cell write determination circuit 3, fluctuation more than expected is input when the fluctuation width of the delay fluctuation greatly changes. Even if this happens, the data memory circuit 1 can be prevented from overflowing or underflowing, and the accurate STM output signal 101 can be output without causing an increase in data delay in the conversion unit.

Further, since the signal speed of the STM output signal 101 does not change, even if the speed change of the digital transmission path is not allowed on the STM side, the above ATM / ST
It is possible to apply the M conversion device.

Further, since the variable range of the threshold value can be set large within the range of the capacity of the data memory circuit 1, the cell fluctuation (delay fluctuation) which greatly changes when the ATM path route is changed in the ATM network. ) Can be dealt with.

[0043]

As described above, according to the present invention, when the fluctuation amount of cell data in the transmission line for asynchronous transfer mode is measured and it is detected that at least the measured fluctuation amount of cell data is input. By starting to read data from the data buffer, even if fluctuations larger than expected are input when the fluctuation range of delay fluctuations changes significantly, the data memory circuit is prevented from overflowing or underflowing, and the data in the conversion unit is prevented. There is an effect that an accurate STM output signal can be output without causing an increase in delay.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between conventional cell fluctuation and ATM / STM conversion.

FIG. 4 is a block diagram showing a conventional system configuration.

[Explanation of symbols]

 1 Data Memory Circuit 2 Fluctuation Calculation Circuit 3 x Cell Write Judgment Circuit 4 Write Address Counter 5 Read Address Counter 21 Up / Down Counter 22 Latch Circuit 23 Adder 31 Comparator

Claims (3)

[Claims] 1. An ATM / STM conversion device including a data buffer for converting cell data input through an asynchronous transfer mode transmission line into synchronous transfer mode data, the asynchronous transfer mode transmission line comprising: In the measuring means for measuring the fluctuation amount of the cell data in, the detection means for detecting that the cell data is input at least the fluctuation amount measured by the measuring means, and based on the detection result of the detecting means, ATM / STM having means for reading data from a data buffer
Conversion device. 2. The measurement means is configured to measure the fluctuation amount by using test cell data input via the asynchronous transfer mode transmission line. ATM / STM converter. 3. The ATM according to claim 1, wherein the data buffer is configured so that an area for accumulating the cell data can be changed according to a measurement result of the measuring means. / STM converter.