JPH09116113A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: In a semiconductor device having a memory cell such as a DRAM and a circuit such as a logic, a semiconductor device capable of speeding up circuits other than the memory cell without degrading the data retention characteristics of the memory cell. And a method for manufacturing the same. SOLUTION: A memory cell is formed after covering a circuit field effect transistor with an insulating layer, and after forming the memory cell, a diffusion layer surface of the circuit field effect transistor is exposed.
Then, a coating conductive layer is formed on the surface of the exposed diffusion layer of the field effect transistor for a circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a memory cell such as a DRAM and peripheral circuits, logic circuits and the like are mounted together, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A high-speed logic equipped with a large capacity dynamic random access memory (DRAM) for processing an image signal at high speed for a personal computer or game machine and displaying it on a display. Devices are needed. This is because in a 2-chip configuration of general-purpose DRAM and logic, when exchanging data between DRAM and logic, there is a limit to the bus width, so a large amount of data cannot be sent at the same time, and processing speed is limited. Is.

In order to improve the performance of logic devices in the future, salicide technology (silicide layers are formed on both the polysilicon gate and the source / drain layers) is used to reduce the resistance of the diffusion layer. The need is emerging. However, when the diffusion layer of the switching MOS transistor forming the DRAM part is salicided, the heat treatment for forming the bit line after the salicide formation and the heat treatment for forming the capacitor increase the resistance of the salicided diffusion layer and cause a junction. There is a problem that the leak rises.

In order to explain this problem, a process of forming a conventional stack type DRAM having a salicide structure will be specifically described. First, as shown in FIG. 17A, after forming an element isolation region (LOCOS) 220 on a substrate 111, a polycide and an insulating film are deposited and patterned to form a gate electrode 2.
21 are formed. Then, ion implantation for LDD is performed to form the LDD diffusion layer 112. Next, an oxide film is deposited and then etched back to form sidewalls, thereby forming an insulating layer 222 that covers the electrodes. Then, after ion implantation for source / drain, the diffusion layer is exposed and titanium is deposited and heated to form a silicide layer 223 in the diffusion layer.

Thereafter, as shown in FIG. 17B, an impurity-doped polysilicon film 224 for the lower electrode is formed,
Then, annealing is performed in nitrogen gas at about 800 ° C. for about 10 minutes. Next, after patterning the lower electrode, R
TA (Rapid Thermal Anneal) is performed at 900 ° C. for about 1 minute in an ammonia atmosphere, and then a silicon nitride film is deposited by CVD.
(About 700 ° C.), and then the silicon nitride film is oxidized, for example, at 850 ° C. for 10 minutes under the condition of H ₂ + O ₂ to form a dielectric film (ONO film) 225. Then, an impurity-doped polysilicon film 226 for the upper electrode is formed by CVD,
After annealing at about 800 ° C., this is patterned to obtain the stack type DRAM shown in FIG.

As described above, when a DRAM capacitor is manufactured after salicide of the diffusion layer, a heat treatment of about 800 ° C. (in the above example, a heat treatment of 850 ° C. for about 50 minutes in total) is added. However, there are problems that the resistance of the diffusion layer that has been salicided increases and that the junction leak increases. Therefore, when implementing DRAM on chip on a high-speed logic device, DR
There is a problem that the data retention characteristic of AM deteriorates.

Therefore, in a logic device having a DRAM mounted therein, in order to increase the speed of the logic device while suppressing an increase in junction leakage of the DRAM, a process of lowering the resistance of a diffusion layer of the logic portion while mounting a DRAM that is not salicided is required. Although necessary, there are problems with this process.

FIG. 18 is a sectional view of an on-chip DRAM having a stack type general purpose DRAM and a logic circuit mounted therein. This DRAM part is a COB (Capacitor Over Bitli
ne) type, the capacitor has a so-called double cylinder type structure. A general manufacturing process of this semiconductor device will be briefly described. An element isolation region 230 is formed on the substrate 111 by the LOCOS method or the like, a gate oxide film is formed on the surface of the active region, and then polysilicon or tungsten silicide into which impurities are introduced. Then, silicon oxide is sequentially formed by CVD, and then patterned to form a gate electrode 231. After that, the n-type impurity is ion-implanted by using the gate electrode 231 and the LOCOS 230 as a mask to perform LDD 112.
To form Then, after thickly depositing silicon oxide, this is etched back to form a side wall 232, and then ion implantation for source / drain is performed to form a source / drain.
The drain 113 is formed. Then, the silicon nitride film 233
After the film formation, the BPSG film 234 is deposited and flattened. The bit contact 235 is opened and impurities are introduced into the polysilicon 237 and the tungsten silicide 238.
Are stacked and then patterned to form the bit line 240. BPSG (Boro Phospho Silicate Glass) 241
Is deposited and planarized, and then a silicon nitride film 242 is formed.
After opening the storage node contact 245 and forming a sidewall 246 of silicon oxide on the inner wall thereof, the node contact 245 is filled with polysilicon 247. BPSG
Of silicon by several hundreds nm, and is etched using the silicon nitride film 242 as an etching stopper in the shape of the memory node.
After forming a groove in the PSG film and subsequently depositing impurity-doped polysilicon 250, a sidewall is formed on the inner wall of the groove. Then, a polysilicon film 251 and a silicon oxide film are sequentially formed, the silicon oxide film is etched back to expose the polysilicon film, and then the polysilicon film 250 is etched. As a result, the side wall is exposed, so the silicon oxide film containing the side wall is removed. As a result, a storage node having a double cylinder structure is formed. Next, after forming an ONO film on the polysilicon surface,
After depositing polysilicon and further depositing a silicon oxide film 253, patterning is performed to complete a plate electrode, and an on-chip DRAM having a structure as shown in FIG. 18 can be obtained.

In such a process, a heat treatment for forming a bit line and a heat treatment for forming a capacitor (corresponding to annealing at 850 ° C. or more for 1 hour or more) are required when forming a DRAM part. Therefore, if salicide is formed in the logic transistor portion, the salicide diffusion layer is formed and then the DRAM portion is formed, which causes a problem that resistance of the salicide diffusion layer and junction leakage increase.

Therefore, it is considered impossible to realize a high-speed logic device equipped with a stack type general-purpose DRAM cell in which salicide is applied to a transistor in a logic section. However, at present, there is a demand for a high-speed logic device equipped with a large capacity DRAM for image signal processing.

The present invention has been made in view of the above circumstances, and in a semiconductor device having a memory cell such as a DRAM and a circuit such as a logic, a circuit other than the memory cell is not deteriorated without degrading the data retention characteristic of the memory cell. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same which can speed up the process.

[0012]

In order to achieve the above object, the present invention provides a field effect transistor for memory which constitutes a memory cell and a field effect transistor for circuit which constitutes a circuit other than the memory cell on the same substrate. In the semiconductor device formed as described above, a covering conductive layer is provided on part or all of the surface of the diffusion layer of the circuit field effect transistor, and the covering conductive layer is formed on the diffusion layer of the memory field effect transistor. Provided is a semiconductor device characterized by having no.

The present invention also provides a method of manufacturing a semiconductor device, wherein a memory cell and a field effect transistor for a circuit which constitutes a circuit other than the memory cell are formed on the same substrate.
A step of forming an insulating layer covering the circuit field effect transistor, a step of forming a memory cell, and a step of exposing a part or all of the diffusion layer surface of the circuit field effect transistor after forming the memory cell. And a step of forming a coating conductive layer on the surface of the diffusion layer of the exposed field effect transistor for a circuit, the method for manufacturing a semiconductor device.

The semiconductor device of the present invention is a semiconductor device in which a field effect transistor for memory which constitutes a memory cell and a field effect transistor for circuit which constitutes a circuit other than the memory cell are formed on the same substrate, A coating conductive layer made of, for example, a metal or a metal alloy is formed on a part or the whole of the surface of the diffusion layer of the circuit field effect transistor, and the diffusion layer of the memory field effect transistor has such a coating. No conductive layer is formed.

Therefore, since the memory cell is formed in the diffusion layer having no conductive layer such as silicide, the junction leak does not increase. Further, since the conductive layer is provided only in the diffusion layer of the transistor that constitutes the circuit other than the memory cell, the resistance of the diffusion layer can be reduced and the speed of the logic circuit can be increased. Therefore, the general-purpose DRAM and the high-speed logic circuit can be mounted together without deteriorating the performance of each other.

The semiconductor device manufacturing method of the present invention is
After covering the circuit field-effect transistor with an insulating layer, forming a memory cell, exposing the diffusion layer surface of the circuit field-effect transistor after forming the memory cell, and diffusing the exposed circuit field-effect transistor A coated conductive layer is formed on the layer surface.

Therefore, the memory cell can be formed on the diffusion layer not provided with the covering conductive layer such as silicidation.
There is no increase in junction leakage in RAM or the like. Further, since the covering conductive layer is provided on the diffusion layer of the circuit transistor after the memory cell is already formed, the resistance of the diffusion layer in the covering conductive layer such as silicidation is increased by the heat treatment when forming the capacitor of the memory cell. There is no inconvenience. Therefore, in the semiconductor device manufactured by the method of the present invention, the data retention characteristic is good in the memory cell section and the speedup is achieved in the circuit section.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiments of the present invention will be specifically described below, but the present invention is not limited to the following embodiments. [First Embodiment] FIGS. 1 to 6 show an example of a manufacturing process of a semiconductor device of the present invention having a DRAM having a fin-type storage node and a circuit portion in which a silicide is formed in a diffusion layer of a MOS transistor. It is a thing.

First, as shown in FIG. 1, an element isolation region (LOCOS) 20 is formed on the surface of the substrate 10 by patterning a silicon nitride film or the like and thermally oxidizing it. Then, after forming the gate oxide film 21, a tungsten polycide film and an oxide film having a thickness of several hundred nm are deposited by CVD or the like, and these are patterned to form the gate electrode 40 and the offset oxide film 22. Next, impurity ion implantation for LDD is performed to form the LDD diffusion region 11. Then, a silicon oxide film 23 having a thickness of several hundred nm is formed by the CVD method.
After the silicon nitride film 24 having a thickness of several tens nm is formed by the low pressure CVD method, the BPSG film 25 is deposited by several hundreds nm by the CVD method, and this BPSG is flowed at 800 to 900 ° C.
Can be obtained.

In this embodiment, the circuit MOS transistor is formed of a silicon oxide film 23, which is an insulating layer, a silicon nitride film 24,
Then, in a state of being covered with the BPSG film 25, a process of forming a memory cell portion is started next. Note that the sidewalls of the transistors in the circuit portion are formed later.

As shown in FIG. 2, after forming an impurity-doped polycrystalline polysilicon film 41 of tens of nm and a silicon oxide film 26 of tens of nm by CVD or the like, a resist pattern for storage node contact is formed, With this as a mask,
Silicon oxide film 26, polycrystalline polysilicon film 41, BPS
The G film 25, the silicon nitride film 24, and the silicon oxide film 23 are sequentially etched to open the storage node contact 12. In this case, when the BPSG film 25 and the silicon oxide film 23 are etched, the silicon nitride film 24 is etched with a high selectivity. Then, an impurity-doped polycrystalline silicon film 42 is formed by CVD or the like, whereby the polycrystalline silicon film 42 and the LDD 1 are formed.
It is electrically connected to 1. Next, resist patterning for the storage node is performed, and using this as a mask, the polycrystalline silicon film 42, the silicon oxide film 26, and the polycrystalline silicon film 4 are used.
1 is sequentially anisotropically etched. As a result, the lower electrode forming the fin-type stack type storage node is formed.

Next, as shown in FIG. 3, the oxide film 26 sandwiched between the polycrystalline silicon films 42 and 41 of the lower electrode by HF.
Wet etching is performed on the BPSG film 25 and the silicon nitride film 24 as stoppers. As a result, the fin portion (storage node) of the lower electrode of the capacitor is exposed. Then, RTA is performed at 900 ° C. for about 1 minute in an ammonia atmosphere, then a silicon nitride film is formed by CVD (about 700 ° C.), and then a silicon nitride film is formed, for example, at 850 ° C. for 10 minutes.
Oxidizes under the condition of H ₂ + O ₂ and turns on the surface of the storage node
After forming the O film 27, the impurity-doped polycrystalline silicon film 43 for the plate electrode and the low pressure CVD silicon nitride film having a thickness of several tens of nm are formed by CVD. Subsequently, resist patterning for the plate electrode is performed, and the silicon nitride film 28 and the polycrystalline silicon film 43 are etched using this resist as a mask. In this case, the polycrystalline silicon film 4 of the lower electrode
The oxide film 26 sandwiched between 2 and 41 can be left as it is, and the BPSG film 25 can be etched after the upper electrode is formed.

Further, in this embodiment, the resist is left, and then the silicon nitride film 24 and the oxide film 2 in the circuit portion are continuously formed.
3 and 3 are anisotropically etched. As a result, as shown in FIG. 3, the capacitor of the DRAM is completed, and at the side wall of the gate electrode 40 of the circuit MOS transistor,
The sidewall 29 is formed. Further, the surface of the substrate 10 in the source / drain region of the peripheral circuit portion is exposed. After removing the resist, the insulating layer of the circuit portion may be etched using the upper electrode as a mask to expose the diffusion layer.

Thereafter, as shown in FIG. 4, after ion implantation for source / drain, heat treatment is performed to form a source / drain diffusion layer 13, and then a refractory metal such as Ti of several tens nm is formed. Sputter with a thickness of about
Lamp annealing is performed at about 650 to 850 ° C. to form the silicide layer (covering conductive layer) 14. The unreacted Ti remaining on the silicon oxide is etched off with a solution containing H ₂ O ₂ . After that, a silicon nitride film 30 is deposited by several tens of nm by the low pressure CVD method, and a silicon oxide film 31 is further deposited by several hundreds of nm by the CVD, and then it is flattened by the CMP method (chemical mechanical polishing method) or the like. . This is because the present embodiment exposes the substrate surface of the peripheral circuit portion after forming the capacitor, and thus a considerable step is generated. For example, as shown in FIG.
As shown in 1., from the substrate surface to the top surface of the capacitor is 1.
The step difference from the upper surface of the insulating layer of the transistor of the peripheral circuit to the upper surface of the capacitor above the transistor of the DRAM portion is about 0.58 μm.

Next, as shown in FIG. 5, resist patterning for bit contacts in the DRAM cell portion is performed to form an oxide film 31, a silicon nitride film 30, and a silicon nitride film 2.
8. The bit contact 15 is formed by sequentially anisotropically etching the upper electrode polycrystalline silicon film 43, the silicon nitride film 24, and the oxide film 23. After depositing a silicon oxide film by CVD for several hundreds of nm, this is etched back to form a side wall 32 on the side wall of the bit contact hole. The side wall 32 forms a plate electrode 43.
And separate. After that, a phosphorus-doped polycrystalline silicon film 44 is formed in the bit contact portion by CVD or the like, and then etched back to fill the bit contact hole.

Finally, as shown in FIG. 6, the contacts are patterned in the circuit portion, and the oxide film 31 and the silicon nitride film 30 are anisotropically etched to open the contacts.
After depositing a barrier metal 45 on this, the contact is filled with a blanket tungsten 46 by depositing tungsten and etching back. After that, 1 Al wiring 47,
The inter-layer insulating film 33 and the 2Al wiring 48 are formed to complete the device on which the DRAM is mounted.

According to the process of this example, it is possible to surely form the silicide only in the diffusion layer of the circuit portion without forming the silicide in the diffusion layer of the memory cell. Higher speed can be realized by lowering the resistance of the circuit, and the data retention characteristic is good in the DRAM section. In addition, a memory cell that requires heat treatment is formed in advance, and then silicide is formed in the circuit portion. Further, CMP is used for planarization, and BPS accompanied with heat treatment is used.
Since the flow of G is not performed, the silicide thus formed is not affected by the heat treatment, and the resistance is prevented from increasing. Further, since the sidewall is formed on the side wall of the gate electrode of the transistor when the insulating layer of the circuit portion is etched back to expose the diffusion layer, the process is simplified. [Second Embodiment] Next, the DRAM memory cell portion is constituted by a double cylinder type storage node, and COB (Capa
An example of a method for manufacturing a semiconductor device in which a buried metal layer in which a buried groove formed in an insulating film as a covering conductive layer is buried is provided in a diffusion layer of a logic circuit MOS transistor will be described. .

First, as shown in FIG. 7A, the substrate 10
By patterning a pad oxide film, a silicon nitride film, etc. on the surface and performing thermal oxidation, a device isolation region (LOC) is formed.
OS) 20 is formed. Then, after the gate oxide film 21 is formed by thermal oxidation, the impurity-doped polysilicon, the tungsten polycide film, and the silicon oxide film are C-doped to a thickness of several hundred nm.
The gate electrode 40 and the offset oxide film 22 are formed by depositing by VD or the like and patterning them. Next, using the gate electrode 40 and the LOCOS 20 as a mask, As or phosphorus is accelerated at a voltage of about several tens keV and the dose is 1 × 10 ¹² to 1 ×.
Impurity ion implantation for LDD is performed at about 10 ¹⁴ and LD
The D diffusion region 11 is formed.

After that, as shown in FIG. 7B, a silicon oxide film is formed by CVD to a thickness of about several tens to one hundred and several tens nm, and this is etched back to form a sidewall on the side wall of the gate electrode 40. 29 is formed. Then, the source / drain ions are implanted to form the source / drain 13. Then, a silicon nitride film 24 is formed to a thickness of about several tens nm by a low pressure CVD method, and a BPSG film 25 is formed to a thickness of several hundreds n.
m is formed by CVD, and BPSG is flattened by flow or CMP.

Next, as shown in FIG. 8A, the bit contact BC is opened by resist patterning and reactive ion etching, and the impurity-doped polysilicon 5 is formed.
1 and tungsten silicide 52 are deposited to a thickness of several tens of nm to cover the inner surface of the bit contact BC and then patterned to form the bit line 53.

Then, as shown in FIG. 8B, BPS
G70 is formed by CVD of several hundreds nm, and is flowed or flattened by CMP, and then a silicon nitride film 71 is formed by CVD of several tens of nm by a low pressure CVD method. Then, by opening the storage node contact NC and etching back after depositing the silicon oxide film, the storage node contact hole NC is formed.
After forming the side wall film 72 for ensuring the dielectric strength on the inner wall, polysilicon is deposited and etched back to fill the storage node contact hole NC with the polysilicon plug 54.

Then, as shown in FIG. 9, an insulating layer 73 is deposited by BPSG or NSG to a thickness of several hundred nm. Then
An insulating layer 7 on each storage node contact hole is formed by reactive ion etching using a resist patterned into the shape of the storage node by photolithography as a mask.
3 is etched using the silicon nitride film 71 as an etching stopper to form a storage node trench NH in the insulating layer 73 to expose the surface of the storage node polysilicon plug 54.

Next, an impurity-doped lower polysilicon film 55 to be a lower electrode of the capacitor is deposited by CVD of about tens to hundreds of tens nm, and then a silicon oxide film is formed by CVD of about tens of nm.
Then, the side wall 74 is formed on the inner wall of the storage node groove NH by etching back after the storage node groove NH is deposited. Further, after the impurity-doped upper polysilicon film 56 is deposited by CVD of about several tens nm to one hundred and several tens nm, the silicon oxide film 75 is deposited by CVD of about several hundreds nm.

Then, the silicon oxide film 75 is etched back to expose the upper polysilicon film 56, and then the upper polysilicon film 56 and the lower polysilicon film 55 are reacted with silicon oxide under a high selection ratio condition. Performs a characteristic ion etching. As a result, as shown in FIG. 10, the tips of the side walls 74 are exposed.

After that, as shown in FIG. 11, the remaining silicon oxide film 75, the silicon oxide film 73, and the sidewalls 74 composed of silicon oxide are etched off with an HF diluent or the like using the silicon nitride film 71 as an etching stopper. To do. As a result, a double cylinder type storage node is completed. Subsequently, the surface of the impurity-doped polysilicon 55, 56 is lamp-annealed in a nitrogen gas atmosphere to remove the silicon nitride film by C
A dielectric film 76 composed of an ONO (silicon oxide / silicon nitride / silicon oxide) film is formed by depositing a few nm by VD and further oxidizing the silicon nitride film. Next, the impurity-doped polysilicon film 57 is formed by CVD to have a thickness of several tens nm to a hundred and several tens nm
Then, a silicon oxide film or a silicon nitride film 77 is formed by several hundred nm CVD, and the polysilicon film 57 and the insulating film 77 are patterned by photolithography to form a plate electrode. Alternatively, after the impurity-doped polysilicon 57 is patterned to form the plate electrode, the silicon oxide film or the silicon nitride film 77 may be formed by CVD of several hundred nm. As a result, the DRAM cell portion is completed as shown in FIG.

Next, the step of forming a coating conductive layer on the diffusion layer of the MOS transistor in the circuit section is started. As shown in FIG. 12, an insulating layer (a silicon nitride film 71, a silicon oxide film 70, a silicon oxide film 2) that covers the MOS transistors in the logic circuit portion.
5. The silicon nitride film 24) is sequentially etched to form a buried groove BH reaching the diffusion layer. Then, a Ti film and TiN as an adhesion layer are formed by a sputtering method or a CVD method.
A film 58 is formed, and then a tungsten film is formed by the CVD method. After that, the adhesion layer and the tungsten film are etched back by reactive ion etching to fill the burying groove BH with the tungsten plug 59 to form a burying metal layer (covering conductive layer) 60. Alternatively, instead of etching back, polishing may be performed by a CMP method. After that, a silicon oxide film 78 to be an interlayer insulating film is formed by CVD of several hundreds nm and is flattened by a CMP method or the like.

Finally, as shown in FIG. 13, a contact hole is opened in the interlayer insulating film 78, and a T-shaped layer is formed by sputtering.
After depositing the tungsten 62 with the iN film 61 of about several tens of nm by the CVD method, they are patterned to form a tungsten wiring. After that, after depositing an interlayer insulating film 79, a via hole is opened, the via hole is filled with a TiN film 63 and a tungsten plug 64, and a TiN film 65 and A are formed.
The aluminum wiring formed of the 1Cu or AlSiCu film 66 is patterned, and the interlayer insulating film 80 is formed again. Hereinafter, this is repeated to form a multilayer wiring.

According to the process of this example, the buried metal layer 60 can be reliably formed only in the diffusion layer of the circuit portion without forming the buried metal layer in the diffusion layer of the memory cell. In the circuit portion, high speed can be realized by lowering the resistance of the circuit such as the logic circuit, and in the DRAM portion, the data retention characteristic is good. In addition, since the memory cell that needs heat treatment is formed in advance, the covering conductive layer (buried conductive layer) of the circuit portion is formed, and since the bit line is formed before forming the capacitor, The embedded conductive layer 60 is prevented from being affected by heat when forming the bit line.
We are trying to prevent an increase in resistance.

DRAM of such an on-chip DRAM
A plan view of the part is shown in FIG. FIG. 9 corresponds to a cross-sectional view taken along the line AA of FIG. In FIG. 14, four gate electrodes 40 of the DRAM section are wired in parallel, and the active region and the gate electrode 40 form a first transistor Tr1 and a second transistor Tr2. The bit line 53 is orthogonal to the gate electrode 40 and is connected to these transistors through a bit contact BC in the common diffusion region of the first transistor Tr1 and the second transistor Tr2. The storage node MN formed on the bit line 53 is
The node contact NH is connected to the diffusion layer of the transistor. The memory cell size is 1.20 × 0.6 =
It is 0.72 μm ² . The number of cells is 5000, for example.

FIG. 15 shows an example of a plan view of a transistor in the logic circuit area. This figure shows a state in which a buried metal layer 60 is provided in the diffusion layer of the transistor, and most of the region of the diffusion layer is covered with the buried metal layer. A transistor is composed of the gate electrode and the active region. Tungsten wiring and aluminum wiring are connected to the buried metal layer 60 via contact holes. FIG. 16 is a plan view showing a region separating the active regions. The distance between the active regions is set to 0.50 μm, and the distance between the tungsten wiring and the active region is set to 0.32 μm.

In the present embodiment, the burying groove is completely filled with metal, but silicide may be formed by a method of depositing titanium or the like on the exposed diffusion layer and then reacting it, and then filling with a tungsten plug. . The present invention is not limited to the above embodiment. For example, DRAM
However, the present invention is not limited to this, and FRAM, S
The present invention can be applied to all semiconductor devices having capacitors such as RAM, and can be variously modified without departing from the scope of the present invention.

[0042]

The semiconductor device of the present invention is a semiconductor device in which memory cells and circuits which are fast and have good data retention characteristics are mounted together. Further, according to the method of manufacturing a semiconductor device of the present invention, it is possible to manufacture a semiconductor device in which circuits other than the memory cell can be speeded up without deteriorating the data retention characteristic of the memory cell.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a manufacturing process in a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing a step that follows FIG.

FIG. 3 is a cross-sectional view showing a step that follows FIG.

FIG. 4 is a cross-sectional view showing a step that follows FIG.

FIG. 5 is a sectional view showing a step continued from FIG.

6 is a cross-sectional view showing a step that follows FIG.

7A and 7B are cross-sectional views showing the manufacturing process of the second embodiment.

8A and 8B are cross-sectional views showing a step that follows FIG. 7.

FIG. 9 is a cross-sectional view showing a step that follows FIG.

FIG. 10 is a cross-sectional view showing a step that follows FIG.

11 is a cross-sectional view showing a step that follows FIG. 10.

FIG. 12 is a cross-sectional view showing a step that follows FIG. 11.

FIG. 13 is a cross-sectional view showing a step that follows FIG.

FIG. 14 is a plan view of a DRAM section according to the second embodiment.

FIG. 15 is a plan view of a transistor in a logic circuit area.

FIG. 16 is a plan view showing a region separating an active region in a logic circuit region.

17 (a) and 17 (b) are cross-sectional views showing a manufacturing process of a conventional capacitor using silicide.

FIG. 18 is a cross-sectional view showing the structure of a conventional logic device including a DRAM.

[Explanation of symbols]

10: substrate, 11: LDD, 13: source / drain,
14: silicide (covering conductive layer), 20: LOCOS,
21: gate oxide film, 23: oxide film, 24: silicon nitride film, 27: ONO film, 28: silicon nitride film, 40: gate electrode, 41, 42: lower electrode of capacitor, 43: upper electrode of capacitor (plate) Electrode), 53: bit line, 54: polysilicon plug, 58: adhesion layer, 59:
Tungsten plug, 60: embedded metal layer (covering conductive layer)
NC: node contact hole, NH: node groove, BH:
Groove for embedding

Claims (11)

[Claims] 1. A semiconductor device in which a memory field effect transistor forming a memory cell and a circuit field effect transistor forming a circuit other than the memory cell are formed on the same substrate. A semiconductor device having a coating conductive layer on part or all of the surface of a diffusion layer of a transistor, and not having the coating conductive layer on the diffusion layer of the field effect transistor for memory. 2. The semiconductor device according to claim 1, wherein the coated conductive layer is made of a metal or a metal alloy. 3. The semiconductor device according to claim 1, wherein the memory cell is composed of a dynamic random access memory. 4. A method of manufacturing a semiconductor device in which a memory cell and a field effect transistor for a circuit that constitutes a circuit other than the memory cell are formed on the same substrate, and a step of forming an insulating layer covering the field effect transistor for the circuit. A step of forming a memory cell, a step of exposing a part or the whole of the diffusion layer surface of the circuit field effect transistor after the formation of the memory cell, and the exposed surface of the diffusion layer of the circuit field effect transistor. And a step of forming a coated conductive layer on the substrate. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the surface of the diffusion layer of the transistor is exposed by etching back an insulating layer covering the field effect transistor for a circuit. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the insulating layer covering the circuit field effect transistor is etched back while leaving the resist for patterning the memory cell as it is. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the insulating layer covering the field effect transistor for a circuit is etched back using the electrodes constituting the memory cell as a mask. 8. The method of manufacturing a semiconductor device according to claim 5, wherein a side wall is formed on the side wall of the gate electrode of the field effect transistor for a circuit by the etch back. 9. A step of forming an embedding groove reaching the diffusion layer of the transistor in an insulating layer covering the circuit field effect transistor to expose a part or all of the diffusion layer, and the embedding groove. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of filling the conductor with a conductor to form a coated conductive layer. 10. The semiconductor device according to claim 4, wherein the coated conductive layer is made of a metal or a metal alloy. 11. The method of manufacturing a semiconductor device according to claim 4, wherein the memory cell is a dynamic random access memory.