JPH09121198A - Wireless communication device control device - Google Patents

Abstract

(57) Abstract: It is difficult for a control device to input / output a control signal in a TDMA system, which needs to be input / output in the order of microseconds, at an accurate timing. A timer circuit (20) counts a master clock supplied from the outside, and when counting a predetermined number of master clocks designated by a CPU (10), the count value is returned to a value at the start of counting and the TDMA frame period is set. The corresponding periodic operation is performed. The comparison circuits 31 to 3n compare the count value output from the timer circuit 20 with the set value set by the CPU 10, and output a strobe signal to the wireless unit when they match.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a controller for a wireless communication device suitable for a wireless communication system based on a time division multiple access system.

[0002]

2. Description of the Related Art FIG. 22 shows, for example, Mitsubishi Electric Technical Report No. 60, No. 10 (1986) pp. FIG. 55 is a block diagram showing a configuration of a mobile station of a car telephone system which is the conventional wireless communication device shown in 55 to 59. In the figure, 1 is a transmission / reception antenna, 2 is an antenna duplexer provided to perform transmission and reception by one antenna, 3 is a transmission unit that modulates or amplifies a transmission signal, and 4 is a signal of a required frequency. An oscillating frequency synthesizer, 5 is a receiving unit that demodulates a signal in a predetermined band, 6 is a control unit that controls each unit, 7 is a baseband signal processing unit that handles voice signals, 8 is a transmitting unit, and 9 is a receiving unit. is there.

FIG. 23 is a block diagram showing the case where the control unit 6 is composed of a microcomputer. In the figure, 10 is C
PU, 11 RAM for reading and writing data, 12 ROM for storing programs, 13 timer circuit, 14
Reference numerals 1 to 146 are input / output ports (hereinafter referred to as I / O ports) for interfacing with the outside, and 16 is a bus.

Next, the operation will be described. CPU10
Operates according to a program in the ROM 12. That is, of the I / O ports 141 to 146, the transmission unit 3, the frequency synthesizer 4, and the reception unit 5 (these are collectively referred to as a radio unit. The portion of the radio unit related to transmission is referred to as a radio transmission unit) and the base. A necessary control signal is given through the I / O port assigned to the band signal processing unit 7, and necessary information is inputted from them. If time management is required while controlling these, a timer interrupt is generated in the timer circuit 13, and real-time control is performed according to the timer interrupt. For example, when handling the transmitter activation signal (TXON), the I / O port assigned to TXON is made inactive within a fixed time after the assignment of the wireless channel.

As described above, the CPU 10 gives a control signal such as TXON to the radio section via the I / O ports 141 to 146. Frequency division multiple access method (FDMA method)
When the communication is performed by the wireless communication unit, the operation of the wireless unit is steady, and thus the control of the CPU 10 allows the wireless unit to operate without any problem. However, for example, the next-generation car telephone system (standard number IS-5, which is being considered by the TIA in the United States).
When communication is performed by the time division multiple access method (TDMA method) as in 4), the operation of the wireless device is intermittent. That is, as shown in FIG. 24, transmission / reception must be performed only for the allocated time slot in one TDMA frame. FIG. 24 shows 3 multiplexed TDM.
The case of the A system is shown. Therefore, taking TXON as an example, as shown in FIG. 25, TXON corresponding to the time slot needs to be output.

[0006]

The conventional controller for the wireless communication device is constructed as described above, and the CPU 10 controls the input / output of the control signal. Therefore, there has been a problem that it is difficult to input / output the control signal in the TDMA method, which needs to be input / output in the order of microseconds, at accurate timing. Even if the CPU 10 and other peripheral circuits that operate at high speed are used, there are problems such as an increase in power consumption and an increase in cost of the device.

The present invention has been made to solve the above problems, and even in the case of TDMA communication,
An object of the present invention is to obtain a flexible controller for a wireless communication device, which can process a control signal at an accurate timing and can easily change the setting of the input / output timing of the control signal. Another object of the present invention is to obtain a control device for a wireless communication device that can easily realize timing control of a transmission system that is difficult to control.

[0008]

According to a first aspect of the present invention, there is provided a controller for a wireless communication device, which counts a master clock supplied from the outside and circulates the count value in a cycle corresponding to a TDMA frame. And a strobe signal generation circuit that outputs a strobe signal to the wireless unit when the count value of the timer circuit and the set value corresponding to the strobe timing required by the wireless unit are matched, and the timer circuit. And a control circuit for setting a period corresponding to the TDMA frame and setting a set value in the strobe signal generating circuit.

In the controller of the wireless communication device according to the second aspect of the present invention, the strobe signal generating circuit outputs the strobe signal each time the count value of the timer circuit matches each set value set by the controller. To do.

According to a third aspect of the present invention, there is provided a control device for a wireless communication device capable of arbitrarily changing a set value set in a strobe signal generating circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. 1 is a block diagram showing a control device for a wireless communication device according to a first embodiment of the present invention. In the figure, 20 is a timer circuit in which a count value (timer count value) returns to an initial value in a cycle corresponding to a TDMA frame.
Reference numeral 2 is an input line of a baseband master clock (hereinafter referred to as a master clock) that serves as a reference clock, 24 is a count value supply line, 31 to 3n are comparison circuits for outputting strobe signals, and 41 to 4n are strobe signals (ST).
B) is a strobe output line that is output, and other components are the same as those shown in FIG. 23 with the same reference numerals. However, the content of the program stored in the ROM 12 is different from the conventional one. It should be noted that, here, I / O through which a signal that does not require strict timing control passes
Only the O ports 141 and 142 are provided. Also,
In the first embodiment, the strobe signal generation circuit is realized as the comparison circuits 31 to 3n. Control circuit is CP
It is realized as a program in U10 and ROM 12 (different from the conventional program).

FIG. 3 is a configuration diagram showing a configuration example of the timer circuit 20. In the figure, 202 is connected to the bus 16 and is C
An initial value register for temporarily storing the initial value given by the PU 10, and a timer counter 204 for counting the master clock. FIG. 4 is a configuration diagram showing a configuration example of the comparison circuit 31. In the figure, 302 is connected to the bus 16 and CP
An input register whose setting value is set by U10, 304
Is an output register that outputs a set value, 306 is a latch circuit that latches the count value of the timer counter 204, and 308 is a comparator that compares the set value output from the output register 304 with the value held by the latch circuit 306. , 310 are output latch circuits for synchronizing the coincidence detection pulse output from the comparator 308 with the master clock. The configurations of the other comparison circuits 32 to 3n are also the same.

Next, the operation will be described. First, the CPU
10 performs the following initial settings. That is, an initial value corresponding to a value of (one frame time of TDMA frame) / (master clock cycle) is set in the initial value register 202 of the timer circuit 20. In addition, each comparison circuit 31 to 3
A set value corresponding to various strobe timings required by the wireless unit is set in the n input register 302. CP
After that, U10 does not participate in the generation of the strobe signal except when it is necessary to change the strobe timing.

Timer counter 204 of timer circuit 20
Generates a carry signal when counting and counting up the master clock. By this carry signal, the initial value held in the initial value register 202 is loaded into the timer counter 204. After that, the timer counter 20
4 starts counting from the initial value and repeats the operation of generating a carry signal by counting up. Therefore, the carry signal generation period is equal to the TDMA frame period. That is, in this case, the initial value is such that the difference between the initial value and the count-up value is (one frame time of the TDMA frame) / (master clock cycle). The carry signal also serves as a frame interrupt signal (INT) to the CPU 10.

The count value of the timer counter 204 is constantly output to the supply line 24. Therefore, the count value is supplied to each of the comparison circuits 31 to 3n. Each comparison circuit 31
3n, since the set value in the input register 302 has been transferred to the output register 304 by the frame interrupt signal, the comparator 308 sets the set value and the latch circuit 30.
The count value captured in 6 can be compared. Then, when they match, a match detection signal is output. This match detection signal is latched in the output latch circuit 310 by the master clock. The output of the output latch circuit 310 is output to the wireless unit as a strobe signal.

FIG. 2 shows the relationship between the count value and the strobe signal when "3" is set in the comparison circuit 31 and "10" is set in the comparison circuit 32. The strobe signal is used for the timing control required by the radio section. Then, for example, when n comparison circuits 31 to 3n are provided, n types of strobe signals are supplied to the radio unit. As is clear from the above description, each strobe signal is also generated in the same cycle as the TDMA frame cycle.

When a signal having a pulse width longer than the pulse width of the strobe signal is required, an RS flip-flop (hereinafter referred to as "F / F") 50 is provided after the output latch circuit 310, as shown in FIG. Should be provided. In this way, a signal with a wide pulse width as shown in FIG. 6 can be created. The timing and pulse width of this signal are set to arbitrary values by controlling the set values of the comparison circuits 31 to 3n corresponding to the two strobe signals input to the F / F 50.

Further, it is easy to change the generation timing of the strobe signal. That is, the CPU 10 may set the changed set value in the input register 302 of the comparison circuits 31 to 3n while receiving the TDMA frame immediately before the TDMA frame received when the timing change is required. Good. With this configuration, the output register 3 is output when the next frame interrupt signal is output.
A new set value is set in 04, and the generation timing of the strobe signal is changed.

It is also easy to adjust or change the phase of the TDMA frame, that is, to shift the generation timing of the frame interrupt signal. That is, the initial value given to the timer circuit 20 may be set to a value corresponding to the phase amount to be shifted, and the normal initial value may be given to the timer circuit 20 again when the frame interrupt signal is output.

Although the case where two strobe signals are used to generate a signal having a long pulse width has been described, a counter circuit may be used for the same purpose. For example, as shown in FIG. 7, the CPU 10 sets a count value K corresponding to the pulse width in the counter circuit 51. Then, as shown in FIG. 8, the strobe signal n
The countdown is started by using as a trigger, and the F / F 50 is reset by the borrow signal. Thus, a signal having a pulse width corresponding to the count value K is created. The count value K is held inside the counter circuit 51, and the counter circuit 51 receives the frame interrupt signal.
It is loaded in the counting part of.

Further, when serial data transfer is required, such as frequency setting for the frequency synthesizer of the radio section, as shown in FIG. 9, the output latch circuit 31 is used.
Register 5 in which data is set in advance after 0
2 and the output circuit 54 may be provided. In this case, C
The PU 10 sets predetermined data in the register 52. Then, the output circuit 54 takes in data by using the strobe signal as a trigger and outputs predetermined data as serial data in synchronization with the master clock. The enable signal is active while the serial data is being output. In this way, it is possible to output arbitrary serial data to the wireless unit. And
Providing two such circuits facilitates monitoring of channels other than the own channel in the TDMA frame.

According to the first embodiment, there is an effect that the real-time control becomes possible because the timing control becomes possible without the control unit such as the CPU intervening. Further, it is possible to obtain a plurality of timing signals required in the TDMA system without the intervention of a control unit such as a CPU.

Embodiment 2 FIG. 10 is a block diagram showing a control device for a wireless communication device according to a second embodiment of the present invention. In the figure, 30 is a comparison circuit for comparing a count value with a set value, 60 is a data update circuit in which a plurality of set values can be set, and 62 is a selection circuit for outputting a strobe signal to predetermined strobe output lines 41 to 4n. is there. In this case, the strobe signal generation circuit is composed of a comparison circuit 30, a data update circuit 60 and a selection circuit 62. In addition, 61 has shown the coincidence detection pulse which the comparison circuit 30 outputs.

FIG. 11 is a configuration diagram showing a configuration example of the data update circuit 60. In the figure, reference numeral 64 is connected to the bus 16, receives a necessary data from the CPU 10, and writes the data in the RAM 66, and a write control circuit 68, 68 receives the coincidence detection pulse 61, and the comparison circuit 30 and the selection circuit 6
2 is a read control circuit for giving necessary data to the memory.

Next, the operation will be described. CPU10
At the time of initialization, the data update circuit 60 is provided with set values for creating necessary strobe generation timings and information indicating output destinations of strobe signals corresponding to these set values in order of strobe generation timings. . Then, the write control circuit 64 writes the set value and the information indicating the output destination of the strobe signal in the RAM 66. The comparison circuit 30 has a structure as shown in FIG. 4, for example.
However, in this case, the set value set in the input register 302 is immediately transferred to the output register 304.
Upon receiving the frame interrupt signal, the read control circuit 68 gives the first set value to the comparison circuit 30. Also,
The first information is given to the selection circuit 62.

Then, the comparison circuit 30 compares this set value with the count value of the timer circuit 20, and if they match, outputs a coincidence detection pulse 61 to the selection circuit 62 and the read control circuit 68. The selection circuit 62 selects the strobe output lines 41 to 4n indicated by the first information and outputs a strobe signal to the selected strobe output lines 41 to 4n. On the other hand, the read control circuit 68 causes the coincidence detection pulse 6
When 1 is received, the next set value is given to the comparison circuit 30 and the information corresponding to the set value is given to the selection circuit 62. Thereafter, this operation is repeated and the necessary number of strobe signals are output from the selection circuit 62. Further, the cycle of each strobe signal matches the cycle of the TDMA frame.

The second embodiment also has the effect of enabling real-time control by enabling timing control without intervention of a control unit such as a CPU. Also, CPU
It is possible to obtain a plurality of timing signals required in the TDMA system without the intervention of a control unit such as.

Although the mobile station has been described in each of the above-mentioned embodiments, the transmission / reception cycle counter setting is fixed and the strobe signal generating circuits are provided for a plurality of channels, so that the present invention is also applicable to the base station.

Embodiment 3 12 is a block diagram showing a control device for a wireless communication device according to a third embodiment of the present invention. When the mobile station moves at a high speed, the reception timing synchronization is deviated, but this can be corrected by adding a circuit for detecting the reception timing as shown in FIG. The controller of the wireless communication device shown in FIG. 12 has a unique word detection circuit 112 for correcting the reception timing.
And a latch circuit 114 are further provided.
Further, the unique word detection circuit 112 introduces a predetermined one of the strobe signals. This strobe signal is a signal meaning the reference timing signal at that time.

Next, the operation will be described. The unique word detection circuit 112 starts its operation according to the detection instruction from the CPU 10. Next, the unique word detection circuit 112
The unique word is detected from the received data and the received reproduction clock according to the reference timing signal. When a unique word can be detected, a detection pulse is output. This detection pulse is given to the latch circuit 114 which introduces the count value of the timer circuit 20. The latch circuit 114 latches the count value at that time by the detection pulse. And C
The PU 10 reads the value held in the latch circuit 114. The reception synchronization timing for each TDMA frame can be detected from the read value.

The CPU 10 can detect the deviation of the reception timing by performing the moving average value processing based on the reception synchronization timing of each TDMA frame. CPU1
For 0, the reception timing can be corrected by setting a value according to the detected shift amount in the timer circuit 20 and then resetting the initial value.

Embodiment 4 FIG. 13 is a block diagram showing a control device for a wireless communication device according to a fourth embodiment of the present invention. In the controller of the wireless communication device according to each of the above-described embodiments, the CPU 10 is interrupted by the frame interrupt in the TDMA frame unit even during the intermittent reception operation.
Therefore, it is necessary to keep the CPU 10 operating even when the reception process is not required, and extra power is consumed. The control device for a wireless communication device according to the fourth embodiment shown in FIG. 13 can deal with such a problem. As shown in FIG. 13, the controller of the wireless communication device is provided with a frame number counter 122 that counts the number of received TDMA frames, an active frame detector 124, and a gate circuit 126.

Next, the operation will be described. Timer circuit 2
The carry signal output by 0 is not used as a frame interrupt signal, and the carry signal is input to the frame number counter 122 as a frame pulse (FP). The frame number counter 122 is a counter such that the number of TDMA frames forming a superframe is one round. For example, when the superframe is composed of 12 TDMA frames, the count value is "0"-
The value "11" is cycled. Further, the active frame detector 124 is previously notified from the CPU 10 of data indicating the number of the TDMA frame to be received. Therefore, the active frame detector 124 compares the count value of the frame number counter 122 with the set number data, and outputs a reception start signal while they match.

The reception start signal is the gate signal of the gate circuit 126, and the gate circuit 126 outputs the frame pulse to the CPU 10 as the frame interrupt signal only while the reception start signal is active. FIG.
Shows the generation example of each signal when intermittently receiving three TDMA frames in the superframe. In this way, if the frame interrupt signal is generated only when reception is required, the CPU 10 can be deactivated when the reception operation is not requested, and low power consumption can be realized. .

Embodiment 5 FIG. As shown in FIG. 15, a propagation delay time ta occurs in the transmission between the base station (BS) and the mobile station (MS). In the communication by the TDMA system, it is required that the mobile station output the transmission signal by compensating for the propagation delay time ta.

FIG. 16 is a block diagram showing a control apparatus for a wireless communication device according to a fifth embodiment of the present invention which can also perform such compensation. In the figure, 127 is a first strobe signal generating circuit for generating a strobe signal (RXSTB) to be given to the radio receiving section, and 70 is a timing correction value given by the CPU 10 and a timer circuit (here, the first timer circuit). A comparison circuit for comparing the count value of 20 with 80, a second timer circuit for starting the counting of the master clock triggered by a trigger signal, and 90 for a second strobe for generating a strobe signal (TXSTB) to be given to the wireless transmission unit. It is a signal generation circuit. Reference numerals 91 to 9m are strobe output lines connected to the wireless transmission unit.

The first strobe signal generating circuit 12
As the configurations of the seventh and second strobe signal generation circuits 90, the configuration of the strobe signal generation circuit (the one shown in FIG. 1 or the one shown in FIG. 10) in the first embodiment or the second embodiment can be adopted as it is.

FIG. 17 is a configuration diagram showing a configuration example of the comparison circuit 70. In the figure, 702 is connected to the bus 16,
An input register in which the timing correction value is set by the CPU 10, 704 is an output register that outputs the timing correction value, 706 is a latch circuit that latches the count value of the first timer circuit 20, and 708 is the timing that is output from the output register 704. A comparator that compares the correction value with the value held by the latch circuit 706, and 710 is an output latch circuit that synchronizes the trigger signal output by the comparator 708 with the master clock. Reference numeral 709 denotes a trigger signal given to the second timer circuit 80.

FIG. 18 is a configuration diagram showing a configuration example of the second timer circuit 80. In the figure, 802 is an initial value register connected to the bus 16 for temporarily storing an initial value given from the CPU 10, and 804 is a timer counter for counting a master clock.

Next, the operation will be described. The operations of the first timer circuit 20 and the first strobe signal generation circuit 127 are the same as the operations of the strobe signal generation circuit in the first or second embodiment.
Here, the description is omitted. In this case, the CPU 10
Is a comparator circuit 70 and a second timer circuit 8 during initialization.
Initial values are also set in the 0 and the second strobe signal generation circuit 90. In other words, for the comparison circuit 70, the timing correction value created based on the transmission timing correction amount designated by the base station, and for the second timer circuit 80, for example, the initial value of "0000", Then, each set value (set value for each transmission) for generating each strobe signal is given to the second strobe signal generation circuit 90. Here, the configuration of the second strobe signal generation circuit 90 is as shown in FIG. 19 when the configuration shown in FIG. 1 is adopted. Therefore, each set value is given to each comparison circuit 911-91m.

In the comparison circuit 70, the input register 70
The timing correction value set to 2 is transferred to the output register 704 by the frame interrupt signal. Then
The comparator 708 is a timing correction value and latch circuit 706.
Is compared with the count value of the first timer circuit 20 held in. When they match, the output latch circuit 710
A trigger signal is output via. Therefore, the timing correction value set by the CPU 10 is a value such that (timing correction value−initial value of the first timer circuit 20) × (master clock cycle) is a transmission timing compensation value.

In the second timer circuit 80, the timer counter 804 takes in the value in the initial value register 802 and starts counting when the trigger signal is input. When the initial value is "0000", the count is incremented from "0000". Then, the count value is output to the second strobe signal generation circuit 90.

Thereafter, the comparison circuit 70 outputs the trigger signal at the same cycle as the cycle of the TDMA frame, and the count value of the second timer circuit 80 is returned to "0000" accordingly. The comparison circuit 70 outputs the trigger signal only once after the timing correction value is set by the CPU 10,
The second timer circuit 80 may be configured to be activated by its trigger signal and thereafter reload the initial value by itself, as in the first timer circuit 20.

Each comparison circuit 911 to 91m of the second strobe signal generation circuit 90 compares the count value of the second timer circuit 80 with each set value, and outputs a strobe signal if they match. The output strobe signal is provided to the wireless transmission unit. The wireless transmission unit performs timing control according to the provided strobe signal. Thus, the wireless transmission unit can perform transmission control at the corrected transmission timing.

When a change in the transmission timing correction amount is notified from the base station during communication, the CPU 10
When receiving the frame immediately preceding the TDMA frame that needs to be modified, the input register 7 of the comparator circuit 70
For 02, the changed timing correction value is set. Then, a new timing correction value is transferred to the output register 704 by the next frame interrupt signal. Therefore, the transmission control can be performed from the next TDMA frame at a new correction timing. Also in this case, the strobe signal can be processed by adding the circuit shown in FIG. 5, FIG. 7 or FIG. 9 after the second strobe signal generation circuit 90.

Embodiment 6 FIG. When the mobile station moves at a high speed, the reception timing synchronization is deviated, but this can be corrected by adding a circuit for detecting the reception timing as shown in FIG. The correction operation is the same as in the case of the third embodiment shown in FIG. 12, and description thereof will be omitted here.

Embodiment 7 FIG. As shown in FIG. 21, the frame number counter 122, the active frame detector 12
4 and the gate circuit 126 are added, a frame interrupt signal is not generated when the TDMA frame which is not requested to be received in the superframe is input, and the CPU 1
0 intermittent activation is possible. The operation is the same as in the case of the fourth embodiment shown in FIG. 13, and the description is omitted here.

[0048]

As described above, according to the first aspect of the present invention, the controller of the wireless communication device controls the output of the timer circuit in which the count value circulates according to the cycle of the TDMA frame and the preset value. Since the strobe signal is generated by comparing with, and the count value of the timer circuit is corrected based on the unique word detection timing, timing control can be performed without intervention of a control unit such as a CPU. This enables real-time control,
Moreover, there is an effect that the one whose timing can be easily changed can be obtained. Further, the reception timing can be easily corrected. In particular, since the strobe signal is used to generate the strobe signal corresponding to the TDMA frame in the radio device for the TDMA communication system, the strobe signal is used for the TDM.
There is an effect that what can be input / output corresponding to the A frame at an accurate timing on the order of microseconds is obtained.

According to the second aspect of the present invention, in the controller of the wireless communication device, the strobe signal generating circuit causes the strobe signal to be generated each time the count value of the timer circuit and each set value set by the controller match. Is output, there is an effect that a plurality of timing signals required in the TDMA system can be obtained without the intervention of a control unit such as a CPU.

According to the third aspect of the present invention, the controller of the wireless communication device is configured so that the set value set in the strobe signal generating circuit can be arbitrarily changed. Therefore, the strobe signal generating timing can be easily changed. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a control device for a wireless communication device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a relationship between a strobe signal and a count value.

FIG. 3 is a configuration diagram showing a configuration of a timer circuit.

FIG. 4 is a configuration diagram showing a configuration of a comparison circuit.

FIG. 5 is a circuit diagram showing a circuit that changes the pulse width of a strobe signal.

FIG. 6 is a timing diagram showing a relationship between a strobe signal and an F / F output.

FIG. 7 is a circuit diagram showing another circuit for changing the pulse width of the strobe signal.

FIG. 8 is a timing chart showing the relationship between the output of the counter circuit and the F / F output.

FIG. 9 is a configuration diagram showing a configuration of a circuit for outputting serial data.

FIG. 10 is a block diagram showing a control device for a wireless communication device according to a second embodiment of the present invention.

FIG. 11 is a configuration diagram showing a configuration of a data update circuit.

FIG. 12 is a block diagram showing a control device for a wireless communication device according to a third embodiment of the present invention.

FIG. 13 is a block diagram showing a control device for a wireless communication device according to a fourth embodiment of the present invention.

FIG. 14 is a timing chart showing the relationship between the transmission start signal and the CPU operation.

FIG. 15 is a timing diagram showing a propagation delay time.

FIG. 16 is a block diagram showing a control device for a wireless communication device according to a fifth embodiment of the present invention.

FIG. 17 is a configuration diagram showing a configuration of a comparison circuit.

FIG. 18 is a configuration diagram showing a configuration of a second timer circuit.

FIG. 19 is a configuration diagram showing a configuration of a second strobe signal generation circuit.

FIG. 20 is a block diagram showing a control device for a wireless communication device according to a sixth embodiment of the present invention.

FIG. 21 is a block diagram showing a control device for a wireless communication device according to a seventh embodiment of the present invention.

FIG. 22 is a block diagram showing a mobile station of a car telephone system.

FIG. 23 is a block diagram showing a control device of a conventional wireless communication device.

FIG. 24 is an explanatory diagram showing a TDMA frame.

FIG. 25 is a timing chart showing the timing of TXON.

[Explanation of symbols]

10 CPU (control circuit), 12 ROM (control circuit), 20 timer circuit, 30, 31 to 3n comparison circuit (strobe signal generation circuit), 60 data update circuit (strobe signal generation circuit), 62 selection circuit (strobe signal generation) circuit).

Claims (3)

[Claims] 1. A control device provided in a wireless communication device for a TDMA communication system, comprising: a timer circuit that counts a master clock given from the outside and circulates the count value at a cycle corresponding to a TDMA frame. , A strobe signal generating circuit for comparing the count value of the timer circuit with a set value corresponding to the strobe timing required by the wireless unit and outputting a strobe signal to the wireless unit when they match, and the timer. And a control circuit that sets a cycle corresponding to the TDMA frame in the circuit and sets the set value in the strobe signal generation circuit.
A controller of a wireless communication device for a DMA communication system. 2. The strobe signal generating circuit has a plurality of set values set by a control device, and outputs a strobe signal each time the count value of the timer circuit and each set value match. Item 1. A control device for a wireless communication device according to Item 1. 3. The control device for a wireless communication device according to claim 1, wherein the control device can arbitrarily change a set value set in the strobe signal generating circuit.