JPH09154072A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the power source of image pickup device. SOLUTION: This device is provided with a power supply circuit 12 for supplying a power supply potential Vd2 to a CCD 11 and a booster circuit 14 for supplying a ground potential Vg2 to a driver circuit 13. A driving clock ϕd1 for driving the power supply circuit 12 is started synchronously with the blanking period of horizontal scan of CCD 1, boosted by the driver circuit 13 and supplied to the power supply circuit 12 later. A driving clock ϕd2 for driving the booster circuit 14 repeatedly rises and falls synchronously with the timing of horizontal scan of CCD 1 and further, its frequency is switched high during the period of frame transfer of CCD 11. Thus, the power supply potential and ground potential supplied to respective circuit blocks are made single.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus which obtains image data for each screen by using a CCD solid-state image pickup device.

[0002]

2. Description of the Related Art In computer equipment such as personal computers and word processors, it is well known to use an image scanner which scans and reads an object document when capturing image data.
It has been considered to use an image pickup device using a CCD solid-state image pickup element that can deal with a three-dimensional object. In that case, the operation of the imaging device is controlled by the computer device, and the image data is taken out in units of one screen in response to a request from the computer device.

FIG. 6 is a block diagram showing the structure of an image pickup device in which image data is taken out on a screen-by-screen basis using a CCD solid-state image pickup device, and FIG. 7 is a timing chart for explaining its operation. The CCD solid-state imaging device 1 has a plurality of light receiving pixels arranged in rows and columns, and accumulates information charges generated in accordance with an image of an illuminated object in each light receiving pixel. The CCD 1 is, for example, of a frame transfer type, and as shown in FIG. 8, a plurality of vertical shift registers 1v continuous from the image pickup unit to the storage unit, and a horizontal shift register 1 arranged on the output side of each vertical shift register 1v.
h and an output section 1d arranged on the output side of the horizontal shift register 1h. In the imaging unit, the vertical shift register 1v is electrically separated to form a plurality of light receiving pixels, and information charges generated by photoelectric conversion are accumulated in each light receiving pixel. The information charge accumulated in each light receiving pixel of the image pickup unit is applied to each vertical shift register 1 by the frame transfer clock φf and the corresponding vertical transfer clock φv.
The inside of v is transferred from the imaging unit to the storage unit and temporarily stored. The information charges accumulated in the accumulation section are transferred from each vertical shift register 1v to each bit of the horizontal shift register 1h in units of one row by the vertical transfer clock φv, and at the same time, from the horizontal shift register 1h to the output section by the horizontal transfer clock φh. Each row is serially transferred to 1d.
The information charges transferred to the output unit 1d are stored in the capacitors bit by bit, so that the charge amount is converted into a voltage value and output as a video signal Y0 (t). At this time, in the output section 1d, the information charge accumulated in the capacitor is transferred to the horizontal transfer clock φh.
Is discharged to the drain in response to the reset clock φr synchronized with. Further, the CCD 1 has a so-called vertical overflow drain structure in which an excessive information charge generated in the image pickup section is absorbed in the substrate side, and the information charge accumulated in the image pickup section is transferred to the substrate side by the substrate clock φb. Can be discharged.

The driver circuit 2 includes a timing control circuit 3
The multi-phase frame transfer clock φf and the vertical transfer clock φv generated by are boosted and supplied to the image pickup unit and the storage unit of the CCD 1. At the same time, the substrate clock φb generated by the timing control circuit 3 is boosted and supplied to the substrate of the CCD 1. The timing control circuit 3 is activated by an activation signal TG provided from an external computer device, and based on a reference clock having a constant cycle, a frame transfer clock φf, a vertical transfer clock φv, and a horizontal transfer clock φ.
h and reset clock φr, and board clock φb
Generate The substrate clock φb is for discharging the information charges of the image pickup portion of the CCD 1 and is raised in response to the activation signal TG. The frame transfer clock φf is C
The information charges of the image pickup section of the CD 1 are transferred at high speed to the storage section in units of one screen, and are activated with a delay of a fixed period L from the fall of the substrate clock φb. This period L
Is a period during which information charges are accumulated in each light receiving pixel of the image pickup section of the CCD 1, and the exposure state of the CCD 1 is determined by the computer device side and set to an optimum state. Further, the frame transfer clock φf is clocked without a transfer operation during the period when the substrate clock φb is raised, so that the information charges of the image pickup section are easily discharged to the substrate side. The vertical transfer clock φv is for taking in the information charges transferred from the image pickup unit by the frame transfer clock φf to the storage unit and transferring the information charges from the storage unit to the horizontal transfer unit row by row. This vertical transfer clock φv is
The frame transfer clock φf is activated with a delay of a fixed period L from the fall of the substrate clock φb, and then a line feed pulse is generated at a constant cycle. The horizontal transfer clock φh is for sequentially transferring the information charges transferred from the storage section to the horizontal transfer section in units of one row to the output section side.
It is activated in response to the line transfer pulse of the vertical transfer clock φv. The reset clock φr is the CCD 1
The information charges accumulated in the output part of the above are discharged, and the phases are shifted at the same cycle as the horizontal transfer clock φh. As a result, the information charges accumulated in each light receiving pixel of the image pickup unit during the period L are transferred from the image pickup unit to the storage unit on a screen-by-screen basis, and then from the storage unit via the horizontal transfer unit on a row-by-row basis. Sequential transfer output.

The signal processing circuit 4 takes in the image signal Y0 (t) output from the CCD 1 and, after processing such as sample hold and automatic gain control (AGC), in the case of a color image, performs color separation, Processing such as color difference matrix and balanced modulation is performed. Further, a synchronizing signal for determining the timing of vertical scanning and horizontal scanning is added, and an image signal Y1 (t) including a luminance component, a color component and a synchronizing signal is generated. For example, in the sample hold process, only the difference between the levels is extracted from the image signal Y0 (t) in which the reference level and the signal level are alternately repeated at a constant cycle, and in the AGC process,
The gain for the image signal Y0 (t) is adjusted so that the average level of the image signal Y1 (t) falls within an appropriate range. The A / D conversion circuit 5 processes the image signal Y1 (t) output from the analog signal processing circuit 4 by the analog signal processing circuit 4 (C
Image data D1 (n) corresponding to each light-receiving pixel of CCD1 by analog / digital conversion in synchronization with the output operation of CD1)
Generate The image data D (n) thus generated is sequentially transferred to the computer device on a line-by-line basis.

[0006]

When the CCD 1 is driven, a high voltage is required for controlling the substrate potential, frame transfer operation, and vertical transfer drive. For example, the timing control circuit 3 and the signal processing circuit 4 operate in the range of 0V to 5V, while the frame transfer operation of the CCD 1 and the vertical transfer drive use a clock that changes in the range of -7V to 5V.
In addition, the output of CCD 1 has a voltage of 15V with respect to the ground potential.
The electric potential of is supplied. Therefore, the CCD 1 and the driver circuit 2 need a power source different from the timing control circuit 3 and the signal processing circuit 4.

[0007] Therefore, an object of the present invention is to simplify the power source by making it possible to drive the image pickup apparatus with a single power source.

[0008]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of light-receiving pixels are arranged in a matrix and information charges corresponding to a subject image are formed. Of a solid-state image sensor for accumulating each image on a screen-by-screen basis
A drive circuit that transfers each row in the vertical direction, and then transfers it in the horizontal direction and sequentially outputs it, and a booster circuit that generates a constant potential based on a drive clock having a predetermined period and supplies the same to the drive circuit, and a constant voltage. A timing control circuit that determines each timing of vertical scanning and horizontal scanning of the solid-state image sensor according to a reference clock of a cycle; and a signal processing circuit that receives an output of the solid-state image sensor and generates a predetermined video signal, The frequency of the drive clock supplied to the booster circuit is switched according to the frequency at which the drive circuit operates.

As a result, to the solid-state image pickup device requiring a high voltage, the transfer clock of the level required for driving is supplied from the drive circuit which receives the potential generated by the booster circuit. Then, when the drive circuit operates at a high frequency, the frequency of the drive clock for driving the booster circuit is switched to a high frequency, so that the power shortage in the drive circuit is compensated.

[0010]

1 is a block diagram showing the structure of an image pickup apparatus according to the present invention. The CCD solid-state image sensor 11 is
A plurality of light receiving pixels are arranged in rows and columns, and information charges corresponding to a subject image are accumulated in each light receiving pixel. This CCD 1 is, for example, of a frame transfer system similar to that of FIG. 6, and after transferring the information charges accumulated in the image pickup unit to the storage unit in units of one screen,
The image signal Y0 (t) is output by transferring and outputting in units of one row via the horizontal transfer unit. For CCD1,
From the power supply circuit 12 built in the device to the second power supply potential Vd2
Is supplied to the first ground potential V from a power source external to the device.
g1 is supplied.

The power supply circuit 12 includes two diodes 12
a and 12b and two capacitors 12c and 12d. First and second diodes 12a, 12b
Are connected in series, the first power supply potential Vd1 is applied to the anode side of the first diode 12a, and the first ground potential Vg1 is applied to the cathode side of the second diode 12b via the first capacitor 12c. To be done. First diode 1
The first driving clock φd1 is applied to the connection point between 2a and the second diode 12b via the second capacitor 12d, and the second diode 12b and the first capacitor 12c are connected.
The second power supply potential Vd2 is taken out from the connection point with
It is supplied to D1. The driver circuit 13 uses the frame transfer clock φ generated by the timing control circuit 13.
f, the vertical transfer clock φv, and the substrate clock φb are boosted and supplied to each part of the CCD 1. At the same time, the first drive clock φd1 generated by the timing control circuit 14 is boosted and supplied to the power supply circuit 12. This driver circuit 1
The first power supply potential Vd1 is supplied to 3 from the power eye outside the device, and the second ground potential Vg2 is supplied from the booster circuit 14 incorporated in the device. As a result, the driver circuit 13 operates from the second ground potential Vg2 to the first power supply potential Vd1.
To work between. The booster circuit 14 includes three diodes 1
4a, 14b, 14c and three capacitors 14d, 1
It is composed of 4e and 14f. The first to third diodes 14a, 14b, 14c are connected in series, and the first capacitor 14 is provided on the anode side of the first diode 14a.
The first ground potential Vg1 is applied via d, and the first ground potential Vg1 is applied to the cathode side of the third diode 14c. Second diode 14b and third diode 1
2c via the second capacitor 14e at the connection point with 4c
Drive clock φd2 is applied to the first diode 14
An inverted clock of the second drive clock φd2 is applied to the connection point between a and the second diode 14b via the third capacitor 14f. Then, the second ground potential Vg2 is taken out from the connection point between the first diode 14a and the first capacitor 14d and supplied to the driver circuit 13.

The timing control circuit 15 is activated by an activation signal TG supplied from a computer device, and the frame transfer clock φ is activated based on a reference clock having a constant cycle.
f, vertical transfer clock φv, horizontal transfer clock φh reset clock φr, and substrate clock φb are generated. At the same time, the first and second drive clocks φd1 and φd2 synchronized with the vertical transfer clock φv are generated. Here, the substrate clock φb, the frame transfer clock φf, and the vertical transfer clock φ
v, horizontal transfer clock φh and reset clock φr are
As shown in FIG. 2, the information charges that are the same as those generated by the timing control circuit 3 shown in FIG. After being transferred from the storage unit to the storage unit, the storage unit sequentially outputs the output in units of one row via the horizontal transfer unit. The first drive clock φd1 drives the power supply circuit 12 to generate the second power supply potential Vd2 for the CCD 11, and is raised in synchronization with the line transfer pulse of the vertical transfer clock φv. The period from the rise to the fall of the first drive clock φd1 is set so as to be within the blanking period of the horizontal scanning of the CCD 11. The second drive clock φd1 drives the booster circuit 14 to generate the second ground potential Vg2 for the driver circuit 13, and repeats rising and falling in synchronization with the horizontal scanning timing of the CCD 11. Then, while the frame transfer clock φf is clocked,
The frequency is switched to a high level so that the driver circuit 13 does not suffer from power shortage. A pair of buffer circuits 1
6a and 16b receive the second drive clock φd1 generated by the timing control circuit 15 and its inverted clock, and drive the booster circuit 14. That is, since the timing control circuit 15 has a small driving capability of the output clock, the timing control circuit 15 is provided separately from the buffer circuits 16a and 16a.
6b is provided to ensure that the booster circuit 14 can be driven.

The signal processing circuit 17 takes in the image signal Y0 (t) output from the CCD 1, performs various processes such as sample hold and gamma correction, and outputs it as an image signal Y1 (t) according to a predetermined format. The signal processing itself in this signal processing circuit 17 is the same as that of the signal processing circuit 4 shown in FIG. Then, the A / D conversion circuit 18 takes in the image signal Y1 (t) output from the signal processing circuit 17, and performs analog / digital conversion of the image signal Y1 (t) in synchronization with the signal processing operation of the signal processing circuit 17. By doing C
Image data D (t) corresponding to each light receiving pixel of the CD 11 is generated. The reference circuit 19 is the A / D conversion circuit 18
On the other hand, two types of reference potentials corresponding to the dynamic range of the image signal Y1 (t) are supplied.

Timing control circuit 15 and buffer circuit 1
6, the signal processing circuit 17, the A / D conversion circuit 18, and the reference circuit 19 are integrated on the same semiconductor substrate to be formed as an integrated circuit element 20 for image pickup control. The integrated circuit element 20 is set to operate by receiving the first power supply potential Vd1 and the first ground potential Vg1. As a result, all the circuit blocks including the CCD 11 can be operated by the single power supply of the first power supply potential Vd1 and the first ground potential Vg1.

FIG. 3 is a circuit diagram showing the configuration of the output portion of the CCD 11. The horizontal transfer unit 11h is the same as the horizontal shift register 1h shown in FIG. 8, is driven by the horizontal transfer clock φh, and sequentially transfers and outputs information charges in units of one row. An output control gate 11g for controlling the output of the information charges is provided at the output end of the horizontal transfer section 11h, and a constant potential Vd4 generated from the second power source potential Vd2.
Is applied. The output unit 11d includes the source follower circuit 2
1 and a reset transistor 22, and a potential V generated from the second power source potential Vd2 and the second power source potential Vd2.
It operates by receiving d3. The reset transistor 22 receives the reset clock φr synchronized with the horizontal transfer clock φh, and precharges the capacitance for receiving the information charges on the output side of the horizontal transfer unit 11h to the second power supply potential Vd2 in synchronization with the output operation. Then, the source follower circuit 21 takes out the potential change of the capacitance that receives the information charges output from the horizontal transfer section 11h and outputs it as the image signal Y0 (t). This source follower circuit 21 is connected to the second power source potential Vd2 and the first power source potential Vd2.
The potential Vd3 generated from the second power source potential Vd2 is applied to the gate of the transistor that is a two-stage configuration and is connected to the ground potential Vg1. The first to third resistors 23, 24, 25 are connected to the second
Is connected in series between the power supply potential Vd2 and the first ground potential Vg1. Then, the potential Vd3 supplied to the source follower circuit 21 is taken out from the connection point between the first resistor 23 and the second resistor 24, and output control is performed from the connection point between the second resistor 24 and the third resistor 25. The potential V supplied to the gate 11g
d4 is taken out. For these connection points, the potential V
In order to stabilize d3 and Vd4, a capacitor 26,
27 is attached externally. As described above, the CCD 11 is configured to operate with the second power supply potential Vd2 and the first ground potential Vg1.

FIG. 4 is a waveform diagram for explaining the operation of the booster circuit 14. Here, a case where the first power supply potential Vd1 is 5V and the first ground potential Vg1 is 0V will be described. Since the timing control circuit 15 operates between 0V and 5V, the second
The crest value of the drive clock φd2 is 5V. Therefore, the second diode 1 to which the second drive clock φd2 is applied
The potential at the connection point A between 4b and the third diode 14c is
Since the maximum potential is clamped to 0V by the third diode 14c, it changes between −5V and 0V in the same phase as the second drive clock φd2. Furthermore, the potential at the connection point B between the first diode 14a and the second diode 14b to which the inverted clock of the second drive clock φd2 is applied is the potential change at the connection point A and the second diode 14b.
Since the maximum potential is clamped to −5V by the clamping operation by, the voltage changes between −10V and −5V in the opposite phase to the second drive clock φd2. Then, the second ground potential Vg2 taken out from the connection point of the first diode 14a and the first capacitor 14d becomes about -10V due to the smoothing action of the first capacitor 14d. In normal operation, a voltage drop corresponding to the threshold value of the diode and a loss due to the driving load of the driver circuit 13 occur.
V or so. In the case of a circuit that is actually operated, the threshold value of the diode, the driving capability, the capacitance of the capacitor, etc. may be set so that the second ground potential Vg2 has a target value.

FIG. 5 is a waveform diagram for explaining the operation of the power supply circuit 12. Here, the first power supply potential Vd1 is 5 V and the second ground potential Vg2 supplied from the booster circuit 14 is −10.
The case of V will be described. Since the driver circuit 13 operates between −10 V and 5 V, the first drive clock φd1 is
The peak value is boosted to 15V and supplied to the power supply circuit 12. The potential of the connection point C between the first diode 12a and the second diode 12b to which the boosted first drive clock φd1 is applied is clamped at 5V by the first diode 14c. It changes between 5V and 20V in the same phase as the driving clock φd1 of 1. Then, the second diode 12b and the first capacitor 12
The second power supply potential Vd2 extracted from the connection point with c is
Approximately 20V due to the smoothing action of the first capacitor 12c
Becomes In a normal operation, like the booster circuit 14, the voltage drops to about 15V because a voltage drop corresponding to the threshold value of the diode and a loss due to the driving load of the CCD 11 occur. Also in this booster circuit 12, in the case of a circuit which is actually operated, the threshold value of the diode, the driving capability, the capacitance of the capacitor, etc. may be set by setting the second power supply potential Vd2 to a target value.

[0018]

According to the present invention, a power supply circuit and a booster circuit capable of operating with a power supply common to a timing control circuit and the like are provided for an image pickup device and its drive circuit that require a high drive voltage. It becomes possible to unify the power supply. Therefore, the power supply circuit can be simplified and the power consumption can be reduced.

Further, when the operating frequency of the drive circuit is increased and the power consumption is increased, the frequency of the drive clock for driving the booster circuit is increased to prevent power shortage. In other words, when the operating frequency of the drive circuit is low, the frequency of the drive clock that drives the booster circuit is lowered to reduce power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an image pickup apparatus of the present invention.

FIG. 2 is a timing diagram illustrating the operation of the image pickup apparatus of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an output portion of a CCD solid-state image pickup device mounted in the image pickup apparatus of the present invention.

FIG. 4 is a waveform diagram illustrating the operation of the booster circuit.

FIG. 5 is a waveform diagram illustrating the operation of the power supply circuit.

FIG. 6 is a block diagram illustrating a configuration of a conventional imaging device.

FIG. 7 is a timing diagram illustrating the operation of the conventional imaging device.

FIG. 8 is a schematic diagram showing a configuration of a frame transfer type CCD solid-state imaging device.

[Explanation of symbols]

1, 11 CCD solid-state image sensor 2, 13 Driver circuit 3, 15 Timing control circuit 4, 17 Signal processing circuit 5, 18 A / D conversion circuit 11h Horizontal transfer section 11g Output control gate 11d Output section 12 Power supply circuit 12a, 12b Diode 12c, 12d Capacitor 14 Booster circuit 14a-14c Diode 14d-14f Capacitor 16a, 16b Buffer circuit 19 Reference circuit 20 Integrated circuit element 21 Source follower circuit 22 Reset transistor 23, 24, 25 Resistor 26, 27 Capacitor

Claims (3)

[Claims] 1. A solid-state image sensor in which a plurality of light-receiving pixels are arranged in rows and columns and information charges corresponding to a subject image are accumulated in a screen unit, and information charges accumulated in each light-receiving pixel of the solid-state image sensor are arranged in one row. Each of which is transferred in the vertical direction, and then transferred in the horizontal direction and sequentially output, and a booster circuit which generates a constant potential based on a drive clock having a predetermined cycle and supplies it to the drive circuit, and a constant cycle. A timing control circuit that determines each timing of vertical scanning and horizontal scanning of the solid-state image sensor according to the reference clock of 1), and a signal processing circuit that receives an output of the solid-state image sensor and generates a predetermined video signal. An imaging device, wherein the frequency of a drive clock supplied to a booster circuit is switched according to the frequency at which the drive circuit operates. 2. The image pickup apparatus according to claim 1, further comprising a power supply circuit that generates a power supply potential for driving the solid-state image pickup device in response to an output of the drive circuit. 3. The frame transfer method, wherein the solid-state image pickup device has an image pickup unit in which a plurality of light receiving pixels are arranged in a matrix and a storage unit for storing one screen of information charges stored in the image pickup unit. The image pickup apparatus according to claim 1, wherein a frequency of a drive clock for driving the booster circuit is increased during frame transfer in which accumulated information charges are transferred to an accumulation unit.