JPH0915303A - IC tester - Google Patents

Abstract

PURPOSE: To generate an expected value of VRAM with simple circuit configuration, by storing result data and timing data generated by the same operation as a device to be tested, in a memory in advance, and accessing the memory at test. CONSTITUTION: A CPU 1 transmits the control data and the control signal corresponding to the content of a display memory RAM (VRAM) 12 to control circuit 303 and 314, respectively, and a VRAMDG 30 is made into operating condition for the RAM 12, and a VRAM expected value generation circuit 31 is made into expected value writing condition. Then, starting up (2) for starting test. Relating to DG 30, an ALU 304 operates to write display data into an DRAM part 301, and the circuit 303 counts for generating timing data. The circuit 31 stores them (312). The CPU 1 stops the DG 30, and makes the circuit 31 into the expected value generation condition for starting actual test. The circuit 314 reads the display data as the expected value data out of the storage 312, and further, outputs to a decision part 5 when counting of the read timing data finished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an IC tester,
Specifically, unlike a normal RAM, memory IC, logic IC, etc., such as a display memory RAM (VRAM) or an on-screen IC, a simple circuit for an IC that outputs data at a special timing with respect to input data. The present invention relates to an IC tester that can be tested with.

[0002]

2. Description of the Related Art Conventional IC testers include so-called memory testers and logic testers or IC testers for testing both. In the IC tester for memory, the test pattern is generated by the arithmetic operation circuit (AL
U) is used to generate an algorithmic pattern that changes sequentially, and in the logic tester,
As a hardware for controlling the flow (sequence) of a pattern program, a pattern memory called a sequence pattern generator (SQPG) or a sequence generator and an address generation circuit are used to set pattern data to be generated in the pattern memory, and this memory is set. By accessing, a predetermined pattern required for the test is generated.

By the way, the IC includes a memory and a logic I.
In addition to C, there is a memory such as a VRAM or an on-screen IC that has a built-in memory and generates serial data at a specific terminal at a specific timing with respect to input data. In particular, the on-screen IC has an internal VRAM, and a character generator for superimposing, a circuit for synthesizing a video signal, a character signal and a video signal, and various circuits for display control are integrated at the same time. Has been done.

A typical VRAM of this type of IC is a DRAM.
An IC having a RAM cell as a core to which an image processing function is added. In addition to a timing control circuit, the IC includes a parallel / serial conversion circuit for converting parallel data into serial data for horizontal 1-line display on a CRT display. It has a SAM unit (serial conversion memory unit). The SAM section is mainly composed of a circuit for reading data for one column of DRAM in parallel in one cycle at a time, loading the data in the shift register, shifting the data in the shift register with a high-speed clock, and outputting the data.

[0005]

When testing such an IC, since the output data is serially output at an internal high-speed clock timing with respect to the test data written in the DRAM, the write test data is written. The expected value for inspection must be generated at a special timing converted to serial according to. However, it is difficult to generate this algorithmically. That is, since the timing of the output data with respect to the input data and the generation state of the serial data are different from those of the conventional memory tester or logic tester, the expected value for inspection and the generation timing thereof are the conventional algorithmic pattern generator (A).
LPG) is not sufficient. Further, even when the pattern is generated by the pattern memory, the amount of expected values generated becomes enormous, and it is difficult to control the timing.

Therefore, in the inspection of this kind of IC, the DRA
As an expected value generation method for simultaneously testing the M test and the SAM test, the data generated from the SAM corresponding to the DRAM test data is temporarily stored in the buffer memory and tested. Conceivable. However, from the writing timing of the test data of DRAM, D
Various timing data including the data transfer timing from the RAM to the SAM unit and the output timing from the SAM unit to the output terminal are required for each data, and the amount of data is huge and the output timing is fast. Therefore, it is difficult to control, and it is practically difficult to create a test program including expected values.

In order to avoid such a situation, it can be considered that a special pseudo VRAM is provided as one of the pattern generators inside the IC tester to generate an expected value. However, while generating the test pattern, the data is simultaneously given to the pseudo VRAM in real time,
Since the timing control to obtain the output data as an expected value has to be performed, the hardware has changed greatly,
It has the drawback of becoming an expensive IC tester. Further, it is possible to perform a simulation to perform a pseudo VRAM or an operation similar to this by software instead of by hardware, but the program becomes long and it takes a lot of time and effort to create it as a test program, which is a problem. . An object of the present invention is to solve the above-mentioned problems of the prior art, and to achieve VR with a simple circuit configuration.
IC that generates result data at special timing such as AM
It is an object of the present invention to provide an IC tester that can generate its expected value and whose timing control is simple.

[0008]

The features of the IC tester of the present invention for achieving the above-mentioned object are that the test data inputted to the device under test are operated in substantially the same manner as the device under test and the result data is obtained. To generate the timing data from the input time of the test data to the data output time, the memory, and the result data and the timing data from the data generation circuit and receive these data in correspondence with the test data. The result corresponding to this timing data of the memory is accessed after the timing indicated by this timing data from the time of inputting the test data after accessing the memory and reading the timing data when receiving the expected value write state and test data to be stored in the memory. When the device under test is tested, it has an expected value generation state that outputs data as an expected value. In which and a write and read control circuit which is the expected value generation state after being set to the expected value writing condition.

[0009]

As described above, a data generation circuit that operates substantially the same as the device under test and generates an output result and timing data from input to output is provided, and test data is supplied to obtain expected value data. And the data of its generation timing are generated in advance by the data generation circuit at the time of the test and stored in the memory, and at the time of the test, the same test data is used to access this memory to read the timing data and read the timing data. Based on, the expected value is generated at a predetermined timing. By doing this, it is not necessary to control the device equivalent to the device under test to generate the expected value in real time, the device does not need to be simulated by the program, and the memory is accessed at the actual test time. Since it is sufficient to control to generate the expected value, VR
The circuit for controlling expected value generation in a tester for an IC such as AM is simple.

[0010]

1 is a block diagram of an embodiment to which an IC tester according to the present invention is applied, and FIG. 2 is a VRAM thereof.
3 is a flowchart of generation and output of expected value data of FIG. Reference numeral 10 denotes an IC tester, which is an arithmetic processing unit (CP
U) 1, an algorithmic pattern generator (ALPG) 2 for generating an algorithmic pattern, and a VRAM
A pattern generator (VRAMPG) 3, an applied waveform generation unit 4, a determination unit 5, and pin electronics 6 including a driver, an I / O switching circuit, a relay, etc., and an ALPG 2 and a VRAMPG 3 are included in the bus 1.
It is connected to the CPU 1 through 1. A VRAM (DUT) 12, which is a device under test, is connected to the pin electronics 6 via a socket or a probe. Reference numeral 9 denotes a clock generation circuit, which is AL
The operation clock is sent to PG2, VRAMPG3 and the like.
The applied waveform generation unit 4 and the determination unit 5 may be treated as circuits inside the pin electronics 6.

The ALPG 2 has an address data generating circuit 24 including an ALU 20, registers 21 and 22, a selector 23, and a pattern memory therein, and a data generator 25 including various logic circuits such as an EXOR gate and an AND gate. And outputs the address pattern signal data ADD, the clock pattern signal data CLKD, and the data pattern signal data DATA to the bus 7 to apply the address pattern signal, the clock pattern signal to the applied waveform generation unit 4 and the VRAMPG3. Each data pattern signal is transmitted. The VRAMPG 3 is composed of a VRAM data generator (VRAMDG) 30 and a VRAM expected value generation circuit 31, and is given to the CP via the bus 11.
The data obtained from the VRAMDG30 when the expected value write state is set according to the control signal from U1 is set to V
The RAM expected value generation circuit 31 writes the expected value in the internal memory and sends the expected value to the determination unit 5 via the line 8 when the expected value generation state is set.

The VRAMDG 30 is a hardware circuit that simulates a so-called VRAM, and has a function of generating time data (timing data) from an input signal to an output signal in addition to an output result. This circuit is enabled in the expected value write state and disabled in the expected value generation state according to the control signal of the CPU 1 sent via the bus 11. Then, in the expected value write state, the VRAM is operated in response to the input data to generate the output result, and the output timing data from the data input to the output is generated to generate the VRAM.
It is sent to the expected value generation circuit 31. Inside it, VRA
A DRAM unit 301 similar to M, a parallel / serial conversion circuit 302, a control circuit 303, an arithmetic circuit (A
LU) 304, selector 305, and internal clock generation circuit 306, and the control circuit 301 is a VRAM (DUT) 12 tested in response to a control signal from the CPU 1 sent via the bus 11.
The capacity corresponding to the capacity of the DRAM section 12a of the above is set as the capacity of the DRAM section 301, and is incorporated in the parallel / serial conversion circuit 302 according to the bit number of the conversion shift amount of one cycle of the SAM section 12b of the VRAM (DUT) 12. Set the number of stages of the shift register in the registered register group.

The VRAM stores one screen of data in a bit pattern, and the VRAM stores it as a code like an on-screen IC and accesses the character generator by the code to access the bit data of the display pattern. In the latter case, for example, when a character display of 8 × 8 dots or 8 × 16 dots is performed, a specific display bit pattern is updated 8 times or 16 times every vertical address update. Since it occurs twice, a counter that generates a pattern a plurality of times in accordance with the update of the vertical address may be provided inside. In the former case, a vertical address counter for managing each horizontal line may be provided. Then, the count values of these counters can be output to the VRAM expected value generation circuit 31 together with the timing data.

The control circuit 303 sends a control signal to each circuit according to the data from the CPU 1,
It is mainly composed of a so-called gate array consisting of an AND logic group and an OR logic group and a counter that counts processing cycles, and sends a control signal to each of the above circuits. The arithmetic circuit 304 performs timing calculation corresponding to the horizontal dot clock of the CRT display, the horizontal scanning period, its blanking period, and the vertical scanning period, its blanking period, etc. The display pattern data or code data to be written and the read signal are generated by calculation. Normal,
Writing is performed during the blanking period, and reading is performed during the scanning period (raster period). However, in the case where the raster period is divided into the writing period and the reading period, part of the raster period is allocated to the writing period. To be When code data is written in the DRAM section 301 such as an on-screen IC, a character generator (ROM) is built in the DRAM section 301 to generate a pattern. The internal clock generation circuit 306 generates a clock pulse corresponding to a cycle such as a horizontal dot clock or a clock corresponding to vertical scanning in synchronization with a clock pattern signal input from the outside or a clock of the clock generation circuit 9, and generates each circuit. Send to.

The VRAM expected value generation circuit 31, when set to the expected value write state, outputs the output result from the VRAMDG 30 and the timing value (time data) from input to output according to the input address signal. When the timing value is stored in a predetermined address of the memory and the expected value generation state is set, the timing value is read from the predetermined address according to the input address signal and the timing indicated by the timing value from the address signal input. After that, the output result data is output to the determination unit 5 as an expected value. This circuit includes an address access circuit 311 and a RAM storage unit 31.
2, a write control circuit 313, and a control circuit 314 having a counter inside. The control circuit 314 receives a control signal from the CPU 1 via the bus 11 and stores the output result from the VRAMDG 30 and the timing value from the input at a predetermined address of the RAM storage unit 312 in the VRAM expected value generation circuit 31. Or the address access circuit 311 is controlled to serially output the expected value to the determination unit 5 according to an address pattern signal from the outside.

Next, the operation of generating expected value data of the VRAM will be described with reference to FIG. First, the generation of expected value data of VRAM will be described.
G30 is enabled and VRAM (DU
Control data corresponding to the contents of the DRAM section 12a and the SAM section 12b of the T) 12 via the bus 11 to the VRAMDG3.
0 to the control circuit 303, and VRAMDG3
0 is set so that the VRAM (DUT) 12 is in the operating state (step 101), and the control circuit 3
A control signal is sent to 14 to set the VRAM expected value generation circuit 31 to the expected value write state (step 10).
2). As a result, VRAMDG30 becomes VRAM (DU
T) 12 is set to the same operating state. VRAM
The expected value generation circuit 31 is set to a state in which the output result from the VRAMDG 30 and the timing value from input to data output are stored in a predetermined address of the memory.

The CPU 1 stops the operations of the applied waveform generating section 4, the determining section 5 and the pin electronics 6, and
The LPG 2 is activated to start the test on the VRAM (DUT) 12 (step 103). This makes bus 7
The data ADD of the address pattern signal, the data CLKD of the clock pattern signal, and the data DATA of the data pattern signal are sent to VRAMPG3 via. VR
The AMDG 30 receives the data of the address pattern signal, the data of the clock pattern signal, and the data of the data pattern signal, and the arithmetic circuit 304 operates according to the control of the control circuit 303 according to the clock pattern signal to cause the DRAM unit 301 to receive a predetermined address. Display pattern data or code data is written in the position.

The written display pattern data or code data is read out in 8-bit parallel data, for example, in accordance with the horizontal dot clock of the internal clock generation circuit 306 at a timing corresponding to the horizontal scanning period.
It is sent to the register group of the parallel / serial conversion circuit 302. Here, 8-bit parallel is converted from parallel / serial to generate output result data. In addition, DRA
When the code data is written in the M section 301, the 8-bit code data is read and the character generator is accessed thereby, and 8-bit parallel display bit pattern data is generated from the character generator. The 8-bit data that makes up each line of characters is sequentially accessed with the update of the above-mentioned data is sent to the parallel / serial conversion circuit 302.

During this operation, the control circuit 303 counts up the internal counter according to the clock from the clock generation circuit 9 to generate timing data from the data input of the address pattern signal to the data output (step 104). . Then, the value of the counter, which is timing data, is V together with the display bit pattern in accordance with the timing at which the display bit pattern data serially converted by the register group 305 is output.
It is sent to the RAM expected value generation circuit 31 (step 10).
5). In the serial bit pattern, data for horizontal 1 line scanning is continuously converted every 8 bits according to the data written in the DRAM unit 301.
It is output as continuous data for one line.

In the VRAM expected value generation circuit 31, the write control circuit 313 receives the data of such a display bit pattern for one line and the timing data from the data input to the output, and under the control of the control circuit 314. RAM storage unit 312 indicated by the address access circuit 311
The display bit data and the timing data are written in the address (1) in association with each other (step 106). The address access circuit 311 performs address conversion of the address signal input according to the control signal from the control circuit 314 into an address in the RAM storage unit 312, and sets the address to an appropriate address in the RAM storage unit 312. In the above description, the expected value is written using the data of the address signal as a reference, but the data may be stored as a combination of the address signal and the test data signal. Since the description becomes very complicated, the case where the test program simply sends the predetermined test data to the DUT 12 in order using the address signal as a key for the test is described here.

Next, the actual start of the test and the generation of the expected value data of the VRAM will be described. The CPU 1 disables the VRAMDG 30 (as an expected value generation state) at the start of the test and stops its operation (step 111). ). Then, the control signal for setting the expected value generation state is sent to the control circuit 314 (step 112). Further, the CPU 1 has the applied waveform generator 4
Then, the operating state of the determination unit 5 and the pin electronics 6 is set, the ALPG 2 is activated, and the VRAM (DUT) 1
The test for 2 is started (step 113). As a result, the data A of the address pattern signal is transmitted via the bus 7.
DD, clock pattern signal data CLKD, and data pattern signal data DATA are sent to the VRAMPG3.

The VRAM expected value generation circuit 31 receives the data ADD of the address pattern signal and the data CLKD of the clock pattern signal among the respective data, and the address received by the address access circuit 311 according to the control signal from the control circuit 314. Data ADD of pattern signal
Is converted into an address corresponding to that of the RAM storage unit 312, and the control circuit 3 is converted from this converted address.
14 reads the above-mentioned display bit pattern for one line from the RAM storage unit 312 as expected value data, further reads timing data, counts the clock from the clock generation circuit 9 by the internal counter, and counts up to the timing of the timing data ( At step 113), when the counting is completed, the display bit pattern for one line is serially output as expected value data to the determination unit 5 in correspondence with the horizontal dot clock (step 115).
In this case, only the internal clock generation circuit 306 of the VRAMDG 30 may be activated, and a horizontal dot clock may be received from this to serially output the display data for one line as an expected value.

The data output to the judgment unit 5 is VRAM.
The data output from the serial data output terminal of the (DUT) 12 is sequentially compared to determine whether the data timing and the values of “1” and “0” are pass / fail, and the determination results are sequentially stored in the fail memory. Go. In the above case, the delay time may be set to the time for data to reach from the VRAM (DUT) 12 to the determination circuit of the determination unit 5 in the determination unit 5, but the VRAM expected value generation circuit 31
Then, the delay time is added and output to the determination unit 5,
The timing of the expected value data may be matched with the VRAM (DUT) 12 side.

As described above, in the embodiment, the data for each horizontal 1 line is received by the VRAM expected value generating circuit 31 and stored in memory together with the timing data. The data is not limited to the minute data, and may be stored together with the timing data for every 8 bits, for example. further,
At this time, at the same time, the count value serving as the address of the vertical line is counted by the counter and sent to the VRAM expected value generation circuit 31 and at the same time stored in memory, and the expected value corresponding to each line is referred to by referring to this count value. Can be adopted. In the embodiment, the data of the address signal is used to store the data that is the expected value correspondingly, but the same expected value is used for the same test data pattern signal output corresponding to the screen. Therefore, instead of the address signal, such a test data pattern may be used and the output result data (expected value) and its timing data may be stored in association therewith. Also,
As for the access when the expected value is generated, the expected value and the timing data can be accessed by converting the data of the data pattern into the memory address.

[0025]

As described above, according to the present invention, the data generating circuit which operates substantially the same as the device under test and generates the output result and the timing data from the input to the output is provided. Then, the test data is given to generate the expected value data and its generation timing data at the time of the test in advance by the data generation circuit, and the data is stored in the memory. At the time of the test, the same test data is used to store this memory. Since the timing data is accessed and read, and the expected value is generated at a predetermined timing based on this timing data, it is not necessary to control the device equivalent to the device under test in real time to generate the expected value. You don't have to simulate the device programmatically, Since suffices control of generating an expected value by accessing the memory, the expected value generation control of the tester for IC such as a VRAM becomes simple circuit. As a result, it is possible to easily test devices that have special timing for the result data with respect to the input data, and no special test program is required to generate the expected value. It can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment to which an IC tester according to the present invention is applied.

FIG. 2 is a flowchart of generation and output of expected value data of the VRAM.

[Explanation of symbols]

1 ... CPU, 2 ... Algorithmic pattern generator (A
LPG, 3 ... VRAM pattern generator (VRA
MPG), 4 ... Applied waveform generation section, 5 ... Judgment section, 6 ... Pin electronics, 7, 8, 11 ... Bus, 10 ... IC tester, 12 ... VRAM (DUT), 30 ... VRAM data generator (VRAMDG), 31 ... VRAM expected value generation circuit.

Claims (2)

[Claims] 1. Data for operating the input test data in substantially the same manner as a device under test to output result data, and for generating timing data from the input time of the test data to the data output time. A generation circuit,
A memory, an expected value write state in which the result data and the timing data are received from the data generation circuit, and these data are stored in the memory in correspondence with the test data; and the memory when the test data is received. Is accessed to read the timing data and output the result data corresponding to the timing data of the memory as an expected value after the timing indicated by the timing data from the input time point of the test data. An IC tester including a write / read control circuit that is set to the expected value generation state after being set to the expected value write state when the device under test is tested. 2. The device under test is a VRAM, the test data includes an address signal and a data signal, and the write / read control circuit responds to the address signal in the expected value write state. The IC tester according to claim 1, wherein the result data and the timing data are stored in the memory, the timing data is read from the memory in response to the address signal in the expected value generation state, and the result data is output. .