JPH09162871A - Cell synchronization device, cell synchronization monitoring device, and cell resynchronization device - Google Patents

Abstract

(57) Abstract: A cell synchronization method for an ATM switch or the like is to reliably realize cell synchronization protection. A free-running frame creation circuit 101 creates a free-running frame. The phase adjustment circuit 102 adjusts the transfer timing of the input cell based on the free-running frame.
The three-time continuous loss-of-synchronization monitoring unit 103 detects the loss of synchronization of the cell frame by monitoring whether or not the pulse timings of the input cell frame and the free-running frame are consecutively lost three times in a row. After that, the three-time continuous synchronization recovery monitoring unit 105 monitors whether or not the input cell frame and each pulse timing of the output of the counter 104 continuously match three times to recover the synchronization of the cell frame. To detect. After that, the re-synchronization signal generation circuit 106 initializes the free-running frame generation circuit 101 at the pulse timing of the input cell frame, and the out-of-synchronization out-of-sync monitoring unit 103 three times.
To resynchronize the input cell frame with the free-running frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell synchronization system in an ATM switch or the like.

[0002]

[Prior Art and Problems to be Solved by the Invention] ATM
(Asynchronous Transfer Mode) In exchanges, fixed length data called cells is the minimum unit of transfer,
Since this cell is autonomously switched by hardware, it is possible to transmit and exchange a large amount of data.

In this case, the cells are switched at high speed and autonomously by hardware, so that the cells are transferred at correct timing greatly affects the communication quality in the exchange. Once the cell timing is shifted, it may not be possible to correctly recognize the virtual identifier, which is the address information stored in the beginning portion (header portion) of the cell, and the cell transfer information such as tag information for self-sustained switching. As a result, there arises a problem that the cell is discarded or misdelivery is caused.

In recent years, computer communication has become popular due to the widespread use of personal computers and the like, and the communication quality of exchanges is being questioned even more than before. Unlike voice, when data transfer is executed, even if one bit of data may be lost or erroneous, it may be meaningless. In this respect as well, the communication quality in the exchange becomes more important.

In view of the current situation, a technique for recognizing a cell at a correct timing is important, and a technique for re-synchronizing when the timing is wrong is becoming important.

However, since the ATM switching technology is a new technology, no effective technology for establishing cell synchronization has been proposed so far. An object of the present invention is to reliably realize cell synchronization protection.

[0007]

According to a first aspect of the present invention, there is provided:
It is premised on a cell synchronizer that establishes synchronization of cell data, which is data transferred so as to have a fixed cell length, based on a cell frame, which is data indicating the transfer timing of the cell data.

First, in synchronization with the input cell frame,
It includes a free-running frame creating means for creating a free-running frame that is a new cell frame having the cell length. Next, a phase adjusting means for adjusting the transfer timing of the input cell data based on the free-running frame is included.

Next, there is provided a cell frame out-of-sync detecting means for detecting the out-of-sync of the input cell frame by monitoring the transfer timing of the input cell frame and the transfer timing of the free-running frame. This means, for example,
Out-of-sync of the input cell frame is detected by monitoring whether the pulse timing of the input cell frame and the pulse timing of the free-running frame continuously deviate by the first predetermined number of times. More specifically, the cell frame desynchronization detection means includes a first mismatch detection circuit that detects that the pulse timing of the input cell frame does not match the pulse timing of the free-running frame, and the pulse timing of the input cell frame. And a first coincidence detection circuit for detecting that the pulse timing of the free-running frame coincides,
The output of the first mismatch detection circuit is used as the count input, and the first
Out-of-sync counter that uses the output of the coincidence detection circuit as a reset input, and a first out-of-sync count signal that outputs an out-of-sync detection signal when the value of the count output of the out-of-sync counter matches the first predetermined number of times. And a detection circuit.

Then, it has a frame width detecting means for detecting the frame width of the input cell frame. This means includes, for example, a frame width counter synchronized with a cell frame that starts counting at the pulse timing of an input cell frame and outputs a pulse at the timing of counting the cell long time.

Next, after the cell frame out-of-sync detecting means detects the out-of-sync of the input cell frame, the frame width detecting means monitors the frame width to detect the recovery of synchronization of the input cell frame. It has a synchronization recovery detecting means. This means is, for example, that the frame widths detected by the frame width detecting means are consecutive in the second
The synchronization recovery of the input cell frame is detected by monitoring whether or not the cell length matches the predetermined number of times. More specifically, the cell frame synchronization recovery detecting means outputs a second coincidence detecting circuit for detecting that the pulse timing output from the frame width counter coincides with the pulse timing of the input cell frame, and the frame width counter outputs. The output of the first non-coincidence detection circuit is reset by using the outputs of the second non-coincidence detection circuit and the first non-coincidence detection circuit that detect that the pulse timing of the input cell frame and the pulse timing of the input cell frame do not coincide with each other. It includes a synchronization coincidence number counter as an input and a second predetermined number count detecting circuit which outputs a synchronization restoration detection signal when the value of the count output of the synchronization coincidence number counter coincides with the second predetermined number.

Then, based on the synchronization recovery detection signal, the resynchronization signal for making the transfer timing of the free-running frame created by the free-running frame creating means coincide with the transfer timing of the input cell frame is created. It includes a resynchronization signal generating means for supplying the means.

In the configuration of the first aspect of the present invention described above, the transfer timing of the input cell data is adjusted based on the free-running frame which is a new cell frame having a cell length, so that It is possible to compensate for the deterioration of the cell frame pulse signal due to signal loss.

Further, by detecting the out-of-sync of the input cell frame based on the monitoring of the transfer timing of the input cell frame and the transfer timing of the free-running frame, it is possible to properly detect the out-of-sync of the input cell data. .

Further, after the synchronization loss of the input cell frame is detected, the synchronization restoration of the input cell frame is detected based on the monitoring of the frame width of the input cell frame, so that the synchronization restoration of the input cell data can be properly performed. Can be detected.

Then, the transfer timing of the free-running frame is made to coincide with the transfer timing of the input cell frame based on the detection of the synchronization recovery, so that the resynchronization can be reliably achieved.

Next, the second aspect of the present invention has the same premise as that of the first aspect of the present invention. And first, an error check code calculating means for calculating an error check code for the transmitted cell data, and an error check code adding means for adding the calculated error check code to the transmitted cell data, And a transmission unit that transmits the cell data to which the error check code is added together with the cell frame indicating the transfer timing thereof.

Next, a receiving means for receiving a cell frame and receiving cell data in synchronization with the cell frame, and an error checking code calculating means for calculating an error checking code for the received cell data. , Out-of-sync detecting the out-of-sync between the received cell frame and the received cell data by comparing the calculated error-check code with the error-check code added to the received cell data And a receiver including a detector.

With such a system configuration, it is possible to appropriately detect the loss of synchronization between the cell data and the cell frame.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. One Embodiment FIG. 1 is a configuration diagram of one embodiment of the present invention, and FIG. 2 is a relational diagram of cells and cell frames in an ATM switch.

First, in order to correctly recognize the cell timing, a cell frame indicating the beginning of cell data is used. This signal is, for example, as shown in Fig. 2 (a),
It is a pulse signal that rises for 1τ time before 1τ time of the beginning of the cell, and is transferred by a signal line different from the signal line for transferring cell data. In this case, the cell length in the exchange is 64 as shown in FIG. 2 (b).
If it is τ time, the cell frame is 1 every 64 τ hours.
The pulse signal rises for τ time.

Inside the ATM switch, by recognizing the head of the cell based on this cell frame, it becomes possible to correctly recognize the virtual identifier and tag for performing the correct switching.

Here, in general, between exchanges, a pulse signal of a cell frame may be deteriorated due to a signal loss on a transmission line. In order to compensate for such deterioration, replacement of cell frames is performed in the exchange. This function is realized as a function of newly generating a cell frame synchronized with the cell length and synchronizing its pulse timing with the pulse timing of the input cell frame. In this case, the pulse width of the newly generated cell frame exactly matches the cell length as long as the oscillation circuit operates normally. However, due to various factors, the pulse width of the input cell frame changes and the input timing of the pulse also changes. Therefore, it is necessary to have a function of monitoring the synchronization between the timing of the input cell frame and the timing of the newly generated cell frame and restoring the synchronization when the synchronization is deviated.

FIG. 1 is a circuit configuration diagram for realizing such a function. This configuration is roughly divided into a free-running frame creation circuit 101, a phase adjustment circuit 102, a three-time continuous out-of-sync monitoring section 103, a frame width counter 104 synchronized with a cell frame, and a three-time continuous synchronization recovery monitoring section. 105 and a resynchronization signal generation circuit 106.

The free-running frame creating circuit 101 creates a free-running frame which is a new cell frame. The phase adjustment circuit 102 has a built-in buffer and adjusts the transfer timing of the input cell based on the free-running frame.

The three times consecutive out-of-synchronization monitoring section 103 monitors whether or not the pulse timings of the input cell frame and the free-running frame generated by the free-running frame creating circuit 101 are out of sequence three times in succession. When the out-of-synchronization of the cell frame is detected, when it is detected, the control system (not shown) is notified to that effect. Even after the loss of synchronization is detected, the phase adjustment circuit 1 is operated until the next synchronization is restored.
02 continues control of the input cell based on the free-running frame generated by the free-running frame creation circuit 101. This is to reduce the influence on the device at the subsequent stage in the exchange.

The pulse width of the free-running frame exactly matches the cell length as long as the oscillator circuit (not shown) in the free-running frame creating circuit 101 is normally operating. Therefore,
The out-of-sync of the input cell frame can be detected by the out-of-sync monitoring section 103 comparing the self-running frame with the input cell frame three times in a row.

The frame width counter 104 synchronized with the cell frame starts counting at the pulse timing of the input cell frame and outputs a pulse at the timing counted for the cell length (for example, 64τ) time.

The three-time continuous synchronization recovery monitoring unit 105 outputs the pulse timing of the input cell frame and the frame width counter 104 synchronized with the cell frame after the three-time continuous synchronization loss monitoring unit 103 detects the synchronization loss of the cell frame. By observing whether or not the pulse timing to be performed matches three times in succession, that is, whether or not the pulse width of the input cell frame matches the cell length three times in succession,
Detects cell frame synchronization recovery.

The resynchronization signal generating circuit 106 initializes the free-running frame generating circuit 101 at the pulse timing of the input cell frame after the continuous synchronization recovery monitoring section 105 detects the synchronization recovery of the cell frame three times, By resetting the continuous loss-of-synchronization monitoring unit 103, resynchronization between the input cell frame and the free-running frame is established.

More detailed configurations and functions of the above-described embodiment will be described below. As shown in FIG.
The out-of-sync monitoring unit 103 for three consecutive times detects the mismatch detection circuit 10
7, the coincidence detection circuit 108, and the out-of-sync counter 1
09, a 3-count detection circuit 110, a one-shot pulse generation circuit 111, and an OR circuit 116.

Further, the three-time continuous synchronization recovery monitoring section 105
The match detection circuit 112, the mismatch detection circuit 113, the synchronous match number counter 114, the 3 count detection circuit, the AND circuit 117, and the OR circuit 118.

The operation of the present embodiment based on the configuration so far will be described with reference to the timing chart shown in FIG. Each circuit in the following configuration operates in synchronization with the falling edge of the pulse.

First, the free-running frame creating circuit 101, as shown in FIG. 3 (b), creates free-running frames B at, for example, exactly 64τ time intervals. The phase adjustment circuit 102 is
Based on this free-running frame B, the transfer timing of the input cell is adjusted.

Next, the non-coincidence detection circuit 107 in the three-time consecutive out-of-synchronization monitoring section 103 is constituted by, for example, an exclusive OR circuit, and the input cell frame A and the free-running frame B generated by the free-running frame creating circuit 101 are separated. The timing when the pulse timing is deviated is detected. For example, as shown at timing t1 in FIG. 3 (a), if the phase of the input cell frame A deviates from the free-running frame B for some reason, the pulse of the input cell frame A and the self-running At the timing of the pulse of frame B, the mismatch detection circuit 107
A pulse appears in the signal C shown in FIG. The signal C is input to the count input S of the out-of-sync counter 109. Then, by the pulse of the signal C,
The value of the count output F of the out-of-sync counter 109 is
As shown in FIG. 3 (f), it counts up as 1, 2.

On the other hand, the coincidence detection circuit 108 in the three-time consecutive out-of-synchronization monitoring section 103 is constituted by an AND circuit, for example, and detects the timing when the pulse timings of the input cell frame A and the free-running frame B coincide. For example, FIG.
As shown in the timing t2 of (a), when the phase of the input cell frame A coincides with that of the free-running frame B, at the timing of the pulse of the same input cell frame A (= pulse of the free-running frame B). , A pulse appears in the signal D shown in FIG. 3D output from the coincidence detection circuit 108. The signal D passes through the OR circuit 116 and the out-of-sync counter 1
It is input to the reset input R of 09. When a pulse appears in the signal D output from the match detection circuit 108 before the value of the count output F of the out-of-sync counter 109 reaches 3 due to the pulse of the signal C output from the mismatch detection circuit 107, the out-of-sync counter is displayed. The value of the count output F of 109 is reset to 0, for example, as shown at timing t2 in FIG. 3 (f).

The phase of the input cell frame A is, for example, as shown in FIG.
When continuously deviated as shown as t3 and t5 in (a), three pulses appear in the signal C output from the mismatch detection circuit 107 at these timings, which causes the count output F of the out-of-synchronization counter 109. Reaches a value of 3. The 3-count detection circuit 110 is composed of, for example, an AND circuit which receives the 2-bit output of the out-of-sync counter 109 and a flip-flop circuit which is set by the output of the AND circuit. And
For example, when the value of the count output F of the out-of-synchronization counter 109 reaches 3 as shown at timing t5 in FIG. 3, as shown in FIG.
The value of the out-of-synchronization detection signal G output from 10 is from 0 to 1
Stand up from (low level to high level).

In this way, when the pulse timings of the input cell frame and the free-running frame generated by the free-running frame creating circuit 101 are continuously out of sync three times, the continuous out-of-synchronization monitoring section 103 causes the cell frame to become out of sync three times. Out-of-synchronization is detected, and the value of the out-of-sync detection signal G indicating that is 0 to 1
Stand up. This change in the out-of-synchronization detection signal G is notified to a control system (not shown).

As described above, even after the loss of synchronization is detected, the phase adjusting circuit 102 generates the free-running frame shown in FIG. 3B generated by the free-running frame creating circuit 101 until the next synchronization is restored. Continue control of input cells based on frame.

When the value of the out-of-sync detection signal G rises from 0 to 1, the AND circuit 117 is turned on. As a result,
When the synchronization coincidence counter 114 starts counting, the three-time continuous synchronization recovery monitoring unit 105 starts actual operation.

The coincidence detection circuit 112 in the three-time continuous synchronization recovery monitoring section 105 is composed of, for example, an AND circuit,
The output of the frame width counter 104 synchronized with the input cell frame A and the cell frame shown in FIG.
The timing at which the pulse timing of the signal H shown in (h) matches, that is, the timing at which the pulse width of the input cell frame A comes to match the cell length is detected. For example, as shown in timings t7 and t8 of FIG. 3 (a), when the phase of the input cell frame A coincides with the signal H, the pulse of the coincident input cell frame A (= pulse of the signal H) At the timing, a pulse appears in the signal I shown in FIG. 3 (i) output from the coincidence detection circuit 112.
The signal I is input to the count input S of the synchronous coincidence counter 114 via the AND circuit 117. Then, under the condition that the value of the out-of-synchronization detection signal G shown in FIG. 3 (g) is 1, the value of the count output K of the synchronization coincidence counter 114 is changed by the pulse of the signal I as shown in FIG. As shown in k), it counts up as 1, 2.

On the other hand, the non-coincidence detection circuit 113 in the three-time continuous synchronization recovery monitoring section 105 is constituted by, for example, an exclusive OR circuit, and detects the timing when the pulse timings of the input cell frame A and the signal D are deviated. For example, Figure 3 (a)
As shown at the timing t9 of the input cell frame A
Of the input cell frame A when the phase of the input signal is shifted with respect to the signal D, the coincidence detection circuit 11
A pulse appears in the signal J shown in FIG. The signal J is input to the reset input R of the sync coincidence counter 114 via the OR circuit 118. And
When a pulse appears in the signal J output from the mismatch detection circuit 113 before the value of the count output K of the synchronous match frequency counter 114 reaches 3 due to the pulse of the signal I output from the match detection circuit 112, the synchronous match frequency counter 114 outputs a pulse. The value of the count output K is reset to 0, for example, as shown at the timing t9 in FIG.

Under the condition that the value of the out-of-sync detection signal G shown in FIG. 3 (g) is 1, the input cell frame A
Of the signal D with respect to the signal D, for example, t10 and t11 in FIG.
, And t12, when three consecutive coincidences occur, three pulses appear in the signal I output from the coincidence detection circuit 112 at these timings, which causes the value of the count output K of the synchronous coincidence counter 114 to be three. Reach The 3-count detection circuit 115 is composed of, for example, an AND circuit that receives the 2-bit output of the synchronous coincidence counter 114 and a flip-flop circuit that is set by the output of the AND circuit. Then, for example, as shown at timing t12 in FIG. 3, when the value of the count output K of the synchronization coincidence counter 114 reaches 3,
As shown in FIG. 3 (l), the 3-count detection circuit 115
The value of the signal L output by the signal rises from 0 to 1.

In this way, after the out-of-sync of the cell frame is detected, if the pulse width of the input cell frame coincides with the cell length three times in a row, the continuous synchronization recovery monitoring section 105 causes the cell frame synchronization to be three times. Is detected and the value of the signal L indicating that is raised from 0 to 1.

The resynchronization signal generating circuit 106 is composed of, for example, an AND circuit. Then, when the pulse of the input cell frame A is input as shown at timing t13 in FIG. 13 (a) in the state where the value of the signal L is 1, for example, the resynchronization signal generating circuit 106 outputs FIG. A pulse appears in the resynchronization signal E shown in e).

This re-synchronization signal E initializes the free-running frame creating circuit 101 and causes the out-of-sync counter 109 in the three-time consecutive out-of-sync monitoring section 103 to operate in the OR circuit 1.
3 (f) is reset via 16 and the 3-count detection circuit 110 in the three times consecutive out-of-synchronization monitoring section 103 is reset as shown in FIG. 3 (g).

When the 3-count detection circuit 110 is reset and the value of the out-of-sync detection signal G output from the 3-count detection circuit 110 falls from 1 to 0, for example, at timing t13 in FIG.
One-time pulse generation circuit 1 in the out-of-synchronization out-of-sync monitoring unit 103
11 outputs one pulse M as shown in FIG. 3 (m). This one-shot pulse M causes the synchronization coincidence counter 114 in the three-time continuous synchronization recovery monitoring unit 105 to operate in the OR circuit 1
It resets via 18 as shown in FIG. 3 (k), and further resets the 3 count detection circuit 115 in the three-time continuous synchronization recovery monitoring section 105 as shown in FIG. 3 (l).

As described above, resynchronization between the input cell frame and the free-running frame can be established. Other Embodiments FIG. 4 is a configuration diagram of another embodiment of the present invention.

The above-described embodiment is constructed on the premise that the falling edge of the pulse of the cell frame shown in FIG. 2A and the beginning of the cell data coincide with each other. On the other hand, in the embodiment described below,
The configuration is adopted to deal with the case where the two do not match.

First, in the transmission side device 401, the transmission cell is held in the buffer 403. With this, CRC
The calculation unit 404 executes a CRC (cyclic redundancy code) calculation on the transmission cell. And
The CRC adding unit 405 reads the transmission cell from the buffer 403, and, for example, in the header of the transmission cell, the CR calculated by the CRC calculation unit 404 for the transmission cell.
C is given. The transmission cell with CRC is
Receiving side device 402 via optical conversion unit (E / O) 406
Sent to.

Next, in the reception side device 402, the reception cell is received in synchronization with the reception cell frame via the optical / electrical conversion unit (O / E) 407, and is then held in the buffer 408. At the same time, the CRC calculation unit 409 executes the CRC calculation on the reception cell. And CRC
The check unit 410 uses the CRC added to the received cell.
It is checked whether the received cell data is synchronized with the received cell frame by checking whether or not and the CRC calculated by the CRC calculation unit 409 match.

The synchronization monitoring unit 411 has the same configuration as that of the embodiment having the configuration shown in FIG. 1, and its operation is
When the check result of the CRC check unit 410 is OK, it is as described above. In this case, the buffer 408
Corresponds to the phase adjustment circuit 102 of FIG.
11 outputs the free-running frame shown in FIG. 1 to the buffer 408. On the other hand, when the check result of the CRC check unit 410 is not OK, the out-of-sync detection signal G is forcibly raised from 0 to 1 in the three-time consecutive out-of-sync monitoring unit 103 shown in FIG. In order to realize this function, in the present embodiment, a flip-flop circuit (not shown) is added to the configuration shown in FIG. This flip-flop circuit has a CRC check unit 4
Set by the check result signal output by 10,
It is reset by the resynchronization signal E in FIG. 1, and its output and the output of the 3-count detection circuit 110 in FIG. 1 are input to an OR circuit (not shown), and the output of the OR circuit is used as the out-of-synchronization detection signal G. .

As described above, in the present embodiment, even if the received cell data is not synchronized with the received cell frame, the loss of synchronization can be detected.

[0054]

EXAMPLES Specific examples of the present invention based on the above-described embodiment will be described below.

FIG. 5 is an overall configuration diagram (1) of the ATM switching system according to the embodiment of the present invention, showing the configuration of the ATM host switching system. The configuration of FIG. 5 is roughly divided into a CD that realizes an interface between a line and a switch unit.
MIFSH 501 and dual switch CRSW
SH505 and CCRSH 504, which is a multiplex and duplex
It is composed of The CCRSH 504 is not indispensable, and the CDMIFSH 501 and the CRSWSH 505 may be directly connected.

The CDMIFSH 501 is a part particularly relevant to the present invention, and is composed of a line individual part 502 terminating a subscriber line or a trunk line and a duplicated common part 503.
FIG. 6 is an overall configuration diagram (2) of the ATM switching system according to the embodiment of the present invention, and is a diagram showing a configuration of a broadband remote concentrator (BRLC) 601 which is remotely connected to the ATM host switching system 602. .

The BRLC 601 is composed of a switch unit, which is a duplicated SWSH 603, and RLCSH 604 and MIFSH 605 which realize an interface between the line and the switch unit.

The RLCSH 604 is a part particularly related to the present invention, and is a line individual unit 609 terminating a normal subscriber line or a trunk line and an umbilical line individual unit 610.
And a duplicated common section 608. The umbilical line individual unit 610 uses an ATM line to connect to an ATM.
CRSWSH606 which is a switch unit in the host exchange 602
Is connected to the umbilical line individual unit 611 included in MIFSH 607 connected to.

The above-mentioned CDMIFSH 501 of FIG. 5 or of FIG.
In the RLCSH 604, the line individual unit 502, 609, or 610 terminates the line accommodated therein.
Next, FIG. 7 shows a common part 503 in the CDMIFSH 501 of FIG.
7 is a block diagram of the common unit 608 in the RLCSH 604 of FIG.

The Upward section 701 is the CDMIFSH 501 shown in FIG.
The main signal upstream cell input from the line individual unit 502 in the inside or the line individual unit 609 in the RLCSH 604 in FIG. 6 or the umbilical line individual unit 610 is processed. E / O section 704
Is the signal form of the cell output from the Upward unit 701,
The electric signal form is converted into the optical signal form, and the cell is output to the switch side.

The O / E unit 705 converts the signal form of the main signal downlink cell input from the switch side from the optical signal form to the electric signal form and outputs the cell to the Downward unit 702.

The Downward unit 702 is a part particularly related to the present invention. The Downward unit 702 processes the main signal downlink cells input from the O / E unit 705 while synchronizing them, and then processes them. Or output to 610.

The control unit 703 controls the Upward unit 701 and Down.
In-apparatus control for the ward unit 702 is executed. Further, the control unit 703 transmits control data to the uplink control link (Link) via the Upward unit 701, and receives control data from the downlink control link via the Downward unit 702. When the control unit 703 is provided in the common unit 608 in the RLCSH 604 of FIG. 6, the uplink control link is an intra-station communication for signaling cells from the BRLC 601 of FIG. 6 toward the ATM host switch 602. Is a link,
The downlink control link is from ATM host switch 602 to BRLC6.
Intra-station communication link for the signaling cell towards 01.

The above-mentioned Upward section 701 and Downward section 70
2 and the common unit 503 or 608 including the control unit 703.
Are duplicated. Then, the Upward section 70
The 1 and Downward units 702 form intersystem confounding with the Upward units 701 and Downward units 702 of other systems, respectively, and can mutually exchange control data.

Further, the Upward section 701 and the Downward section 702.
In between, a bidirectional loopback highway for folding back the test cell is formed. In the configuration shown in FIG. 7, the Upward unit 701 has the functions shown below.

A) Line individual unit 502, 609, or 61
0) Interface function for 0 b) Cell time multiplexing function c) IVCC function d) Uplink control link multiplexing function e) Interface function for E / O unit 704 f) Control interface function for control unit 703 g) Interlocking control function Next In addition, the Downward unit 702 has the following functions.

A) Interface function for O / E unit 705 b) Synchronization function and spatial multicast function (Spatial Mu)
lticast) c) Cell separation function (DMUX function) d) Logical multicast function (Logical Multicast) e) Downlink control link separation function f) Interface function for line individual unit 502, 609, or 610 g) Control unit 703 control Interface function h) Inter-system confounding control function The control unit 703 has the following functions.

1) Functions of the control unit 703 of the common unit 503 in the CDMIFSH 501 a) Downlink control link reception function b) Uplink control link transmission function c) Charging function d) Control function for individual line unit 502 e) LED lighting function f ) Fault detection function g) Path setting function h) Data collection function i) Control interface function for Upward section 701 j) Control interface function for Downward section 702 2) Function of control section 703 of common section 608 in RLCSH 604 a) In downlink station Cell reception function for communication b) Cell transmission function for uplink intra-station communication c) Charging function d) Control function for line individual units 609 and 610 e) LED lighting function f) Fault detection function g) Path setting function h) For Forward unit 701 Control interface function i) Control interface function for Downward section 702 j) PAC master function k) Craft person interface function l) Environmental alarm collection / lighting machine Of the above-described functions relating to the configuration of FIG. 7, the functions of particular relevance to the present invention is a synchronization feature b) about Downward unit 702.

FIG. 8 is a functional block diagram of the Upward unit 701 of FIG. The MUX unit 801 is a main signal upstream cell from a plurality (# 0 to # 15) of line individual units 502 in the CDMIFSH 501 of FIG. 5 or a plurality of line individual units 6 in the RLCSH 604 of FIG.
09 or a plurality of main signal uplink cells from the umbilical line individual unit 610 and a plurality (# 0 to # 1) from the Downward unit 702.
5) The main signal uplink cell of the loopback of 5) is time-multiplexed.
The individual line units 502, 609, 610 or Downward
The cell input from the unit 702 has a data length of 54 octets as will be described later with reference to FIG. 11 or FIG.
The transfer rate is 360 K (= 10 ³ ) cells / second.
The MUX unit 801 converts the data length of the cells input from the 16 line individual units to 64 octets as described later with reference to FIG. 13 or 14, and converts the converted cells to 184 MHz. Time multiplex in synchronization with the clock. As a result, the transfer rate of cells output from the MUX unit 801 is 5760 K cells / second. In addition,
The MUX unit 801 may be configured to time-multiplex cells having a transfer rate of 1440K cells / sec from four line individual units.

When the main signal upstream cell is input, the IVCC section 802 receives the degenerate address information ICID (Internal Channel IDentifie) stored in the header section of the cell.
r) Based on the address that corresponds to the combination of the value and the line number that identifies the line, read the cell transfer information from the internal memory, add it to the beginning of the cell, and add that cell to the E /
Output to the switch side via the O unit 704.

FIG. 9 is a functional block diagram of the Downward section 702 of FIG. The BM unit 901 receives the main signal downlink cell having the attribute of point-to-multipoint (PtMP) connection for one-to-many communication input from the O / E unit 705 or looped back from the Upward unit 701, Spatial (spatial) multicast is realized by searching the bitmap information according to the cell transfer information added to it. The BM unit 901 includes a synchronization unit (see FIG. 10) most relevant to the present invention.

The DMUX section 902 has a function of separating the main signal downlink cell from the downlink high speed highway to the downlink low speed highway. The LM unit 903 has a logical (logical) multicast function for a main signal downlink cell having an attribute of PtMP connection, and a cell going to the line individual unit of # 0 to # 15 and Up.
It has a function of separating a cell looped back to the ward unit 701.

FIG. 10 is a functional block diagram of the BM unit 901 of FIG. The synchronization unit 1001 is the most relevant part of the present invention. This will be described later.

The selection unit 1002 is the O / E unit 70 of FIG.
5 and the loopback cell from the Upward unit 701 in FIG. 7 are selected based on the selection instruction information from the control unit 703 in FIG. 7, and the selected cell is selected by the BM search unit 1003.
Output to.

The BM retrieving unit 1003 uses the degenerate address information added to the header of the main signal downlink cell having the attribute of PtMP connection, based on the BM.
The bitmap information stored in the table 1004 is searched, and the search result is embedded in the header part of the cell. The content stored in the BM table 1004 is the same as the control unit 7 in FIG.
Updated by 03.

The control link (Link) extraction unit 1005
The control link data that runs in parallel with the main signal downlink cell on the high speed downlink highway from the E unit 605 is extracted, transferred to the low speed clock (8 MHz), and transferred to the control unit 703 in FIG. 7.

In the above configuration, the synchronizing section 1001 is
The most relevant part of the present invention is the O / E unit 705 of FIG.
5760K cells flowing on the highway down highway from
It has a function of receiving a main signal downlink cell having a transfer rate of seconds and synchronizing it with a clock of 184.32 MHz in its own device.

Details of the function of the synchronizing section 1001 will be described below. (1) Cell reception function Among the main signal downlink cells input from the high-speed downlink highway, the valid cells are transmitted and the invalid cells are discarded. Here, a valid cell is a normally received main signal downlink cell, and an invalid cell is the opposite, and is defined as follows.

(A) Definition of valid cell: Cell satisfying conditions i) and ii) below i) A cell having a data length of 64 octets or more. Here, the self-frame disconnection is detected by a function not particularly shown.

Ii) No parity error has occurred in the header section. (b) Definition of invalid cell: A cell that satisfies the conditions i) or ii) below i) A short cell with a data length of less than 64 octets.

Ii) A parity error has occurred in the header section. (2) Fault detection function The synchronization unit 1001 operates from CRSWSH 505 to CDMIFSH 5 in FIG.
01 or the normality of the interface from SWSH 603 to RLCSH 604 in FIG. If the monitoring result is abnormal, the control unit 703 of FIG. 7 notifies the control processor of the exchange (not shown) via the Upward unit 701 and the uplink control link (Link). The faults detected are shown below.

(A) Cell frame disconnection failure (b) Clock disconnection failure (c) Parity failure (header section and payload section) (d) Multiframe disconnection failure (3) Synchronization function FIG. 11 shows the synchronization section of FIG. It is a functional block diagram which implement | achieves a synchronizing function among 1001 functions, and is a part most relevant to this invention.

In FIG. 11, the write control unit 1102 synchronizes the main signal downlink cell with the input cell frame transferred on a separate line together with the main signal downlink cell, and outputs the cell buffer (Cell Fifo).
) Write to 1101.

On the other hand, the read control unit 1104
Synchronizes with the read cell frame having the fixed phase difference mτ as shown in FIG. 12 with respect to the input cell frame (write cell frame) input to the write control unit 1102, and outputs the main signal downlink cell from the SEF buffer 1101. Read out and output it to the selection unit 1002 in FIG.

The synchronization unit 1103 is, for example, as shown in FIG.
The configuration is similar to that of the embodiment shown in FIG. The synchronization unit 1103 executes the synchronization monitoring operation described above in the description of FIG. 1 on the input cell frame (write cell frame) input from the write control unit 1102. As a result, it becomes possible to compensate for out-of-synchronization of cells caused by transmission loss on the optical transmission line connected to the O / E unit 705 of FIG. 7, for example. In this case,
The self-propelled frame creation circuit 101 of
A free-running frame is generated based on the 184.32 megahertz (MHz) clock shown in FIG. 11 which is output from O (Feedlock Lock Oscillator). Then, the read control unit 1104 generates a read cell frame (FIG. 12) having a fixed phase difference mτ with respect to the free-running frame output from the synchronization unit 1103, and in synchronization with this, a main signal from the SEF buffer 1101. Read the downlink cell. The out-of-sync detection signal G (see FIG. 1) output from the synchronization unit 1001 is transferred to the control unit 703 in FIG. 7, and then the control unit 703 transmits the out-of-sync detection signal G from the Upward unit 701 via an uplink control link (Link). In particular, the control processor of the exchange (not shown) is notified.

Finally, FIG. 13 is an explanatory diagram of an access operation to the cell buffer 1101 of FIG. FIG.
13A is a diagram showing an access operation regarding a short frame cell having a data length of less than 64 octets, FIG.
(b) is a diagram showing an access operation for a long frame cell having a data length longer than 64 octets.

As indicated by the mark X in FIG. 13 (a),
Cell buffer 1101 corresponding to a short frame cell
The address of is overwritten by the normal cell of the next frame, and the reading is not executed at the read timing corresponding to the short frame cell at the time of reading.

On the other hand, as indicated by the mark "x" in FIG. 13B, the long frame cell is directly stored in the cell buffer 1.
Although the data is written to the corresponding address of 101, the reading is not executed at the read timing corresponding to the long frame cell at the time of reading.

As described above, the synchronization for the main signal downlink cell is compensated.

[0090]

According to the first aspect of the present invention, the transfer timing of the input cell data is adjusted on the basis of the free-running frame which is a new cell frame having the cell length, so that the transmission line on the transmission line is adjusted. It becomes possible to compensate the deterioration of the pulse signal of the cell frame due to the signal loss.

Further, by detecting the out-of-sync of the input cell frame based on the monitoring of the transfer timing of the input cell frame and the transfer timing of the free-running frame, it is possible to appropriately detect the out-of-sync of the input cell data. Becomes

Furthermore, after the synchronization loss of the input cell frame is detected, the synchronization recovery of the input cell frame is detected based on the monitoring of the frame width of the input cell frame, so that the synchronization recovery of the input cell data is properly performed. It becomes possible to detect.

Then, the transfer timing of the free-running frame is made to coincide with the transfer timing of the input cell frame based on the detection of the synchronization recovery, so that the resynchronization can be reliably achieved.

According to the second aspect of the present invention, it becomes possible to appropriately detect the loss of synchronization between the cell data and the cell frame.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a relationship diagram between cells and cell frames.

FIG. 3 is a diagram showing a timing chart of the present embodiment.

FIG. 4 is a configuration diagram of another embodiment.

FIG. 5 is an overall configuration diagram (1) of an ATM exchange system that is an embodiment of the present invention.

FIG. 6 is an overall configuration diagram (Part 2) of the ATM exchange system according to the embodiment of the present invention.

FIG. 7 is a configuration diagram of a common unit in CDMIFSH / RLCSH.

FIG. 8 is a configuration diagram of an Upward unit in a common unit.

FIG. 9 is a configuration diagram of a Downward unit in the common unit.

FIG. 10 is a configuration diagram of a BM unit in a Downward unit.

11 is a configuration diagram of a synchronization mechanism 1001. FIG.

FIG. 12 is a relationship diagram between a write cell frame and a read cell frame.

FIG. 13 is an explanatory diagram of a cell buffer access operation.

[Explanation of symbols]

 101 Free-Running Frame Creation Circuit 102 Phase Adjustment Circuit 103 3rd Continuous Out-of-Synchronization Monitoring Unit 104 Frame Width Counter Synchronized to Cell Frame 105 3rd Continuous Synchronization Recovery Monitoring Unit 106 Re-Synchronization Signal Generation Circuit 107, 113 Mismatch Detection Circuits 108, 112 Match detection circuit 109 Out-of-sync counter 110, 115 3 Count detection circuit 111 1-pulse generation circuit 114 Synchronous match counter 116, 118 OR circuit 117 AND circuit 401 Transmitting device 402 Receiving device 403, 408 Buffer 404, 409 CRC Calculation unit 405 CRC assignment unit 406 Electric / optical conversion unit (E / O) 407 Optical / electrical conversion unit (O / E) 410 CRC check unit 411 Synchronization monitoring unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukie Yasaka 1-4-4 Hakataekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture, Fujitsu Kyushu Communication Systems Ltd. (72) Satoshi Kakuma, Nakahara-ku, Kawasaki-shi, Kanagawa 1015 Odanaka, Fujitsu Limited

Claims (13)

[Claims] 1. A cell synchronizer for establishing synchronization of cell data, which is data transferred so as to have a fixed cell length, based on a cell frame, which is data indicating a transfer timing of the cell data. A free-running frame creating unit that creates a free-running frame that is a new cell frame having the cell length in synchronization with the input cell frame; and a phase adjustment that adjusts the transfer timing of the input cell data based on the free-running frame. A cell synchronization device comprising: 2. The cell synchronization monitoring device for the cell synchronization device according to claim 1, wherein the input cell is monitored by monitoring a transfer timing of the input cell frame and a transfer timing of the free-running frame. A cell synchronization monitoring device comprising cell frame out-of-sync detection means for detecting out-of-sync of a frame. 3. The cell frame desynchronization detection means monitors whether or not the pulse timing of the input cell frame and the pulse timing of the free-running frame are continuously deviated by a first predetermined number of times, The out-of-synchronization of the input cell frame is detected. 4. The out-of-sync cell frame detection means detects a mismatch between the pulse timing of the input cell frame and the pulse timing of the free-running frame, and a mismatch detection circuit for the input cell frame. A first match detection circuit for detecting that the pulse timing and the pulse timing of the free-running frame match, and the output of the first mismatch detection circuit is used as a count input.
The out-of-sync counter having the output of the first match detection circuit as a reset input, and the value of the count output of the out-of-sync counter is the first
4. The cell synchronization monitoring device according to claim 3, further comprising: a first predetermined number of times count detection circuit that outputs an out-of-sync detection signal when the predetermined number of times of. 5. A cell synchronization monitoring device for the cell synchronization device according to claim 1, wherein frame width detection means for detecting a frame width of the input cell frame, and a frame detected by the frame width detection means. A cell synchronization monitoring device, comprising: cell frame synchronization recovery detection means for detecting synchronization recovery of the input cell frame by monitoring the width. 6. The frame width detection means includes a frame width counter synchronized with a cell frame that starts counting at the pulse timing of the input cell frame and outputs a pulse at the timing counted for the cell long time. The cell synchronization monitoring device according to claim 5, wherein 7. The cell frame synchronization restoration detecting means monitors whether or not the frame width detected by the frame width detecting means continuously matches the cell length a second predetermined number of times. The cell synchronization monitoring device according to claim 5, wherein the synchronization recovery of the input cell frame is detected. 8. The cell frame synchronization recovery detecting means, a second coincidence detecting circuit for detecting that the pulse timing output from the frame width counter coincides with the pulse timing of the input cell frame, and the frame width. A second mismatch detection circuit that detects that the pulse timing output by the counter does not match the pulse timing of the input cell frame, and the output of the first match detection circuit circuit is the count input, and the first mismatch The value of the count output of the synchronous coincidence counter that uses the output of the detection circuit as a reset input is the second
8. The cell synchronization monitoring device according to claim 7, further comprising: a second predetermined number-of-times count detection circuit which outputs a synchronization recovery detection signal when the predetermined number of times of. 9. The cell resynchronization device for the cell synchronization device according to claim 1, wherein the transfer timing of the free-running frame created by the free-running frame creating means is based on a synchronization recovery detection signal, A cell resynchronization device comprising: a resynchronization signal creating means for supplying a resynchronization signal for matching the transfer timing of the input cell frame to the free-running frame creating means. 10. A cell synchronizer for establishing synchronization of cell data, which is data transferred so as to have a fixed cell length, based on a cell frame, which is data indicating a transfer timing of the cell data. A free-running frame creating unit that creates a free-running frame that is a new cell frame having the cell length in synchronization with the input cell frame; and a phase adjustment that adjusts the transfer timing of the input cell data based on the free-running frame. Means, cell frame out-of-sync detection means for detecting out-of-sync of the input cell frame by monitoring transfer timing of the input cell frame and transfer timing of the free-running frame, and frame width of the input cell frame A frame width detecting means for detecting the After detecting the out-of-sync, by monitoring the frame width detected by the frame width detection means, cell frame synchronization recovery detection means for detecting the synchronization recovery of the input cell frame, based on the synchronization recovery detection signal A resynchronization signal creating means for supplying to the free running frame creating means a resync signal for matching the transfer timing of the free running frame created by the free running frame creating means with the transfer timing of the input cell frame, A cell synchronizer comprising: 11. Data that is provided in a transmission device that transmits cell data, which is data to be transferred so as to have a fixed cell length, and that indicates the synchronization of the cell data and the transfer timing of the cell data. A cell synchronizer established on the basis of a cell frame, wherein error check code calculating means for calculating an error check code for cell data to be transmitted, and the calculated error check code are transmitted. A cell synchronization device, comprising: an error check code adding means to be added to the cell data; and a transmitting means for transmitting the cell data to which the error check code is added together with the cell frame indicating the transfer timing thereof. . 12. Data that is provided in a receiving device that receives cell data transmitted by a transmitting device including the cell synchronizing device according to claim 11, and that synchronizes the cell data and indicates a transfer timing of the cell data. A cell synchronization device that is established based on a cell frame, the receiving means receiving the cell frame, receiving the cell data in synchronization with the cell frame, and an error for the received cell data. Error checking code calculating means for calculating a checking code, and the received cell by comparing the calculated error checking code with the error checking code added to the received cell data. Out-of-sync detecting means for detecting out-of-sync between a frame and the received cell data, and Le synchronization device. 13. A cell synchronizer for establishing synchronization of cell data, which is data transferred so as to have a fixed cell length, based on a cell frame, which is data indicating a transfer timing of the cell data. Error checking code calculating means for calculating an error checking code for the transmitted cell data, and error checking code adding means for adding the calculated error checking code to the transmitted cell data, A transmitting device that transmits cell data to which the error check code is added together with the cell frame indicating its transfer timing; and a transmitting device that receives the cell frame and synchronizes with the cell frame. And a means for calculating an error check code for the received cell data. Error checking code calculating means, by comparing the calculated error checking code with the error checking code added to the received cell data, the received cell frame and the received cell frame are received. An out-of-sync detecting means for detecting out-of-sync with cell data, and a receiving device including :.