JPH09185557A - Redundant memory and data processor using redundant memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a redundant memory containing a main memory, a multiplexer, a cache and a non-volatile memory. SOLUTION: The redundant memory 25 supports the data change of a work unit without affecting the access time of the redundant memory 25. For accessing to a defective address, the data part 42 of a cache 40 is accessed. When an access address is matched with a programmed address in the cache 40, the multiplexer 32 selects the cache 40 and a main memory 30 which completely functions is realized. For example, the data word of defective flash EEPROM can be substituted by programming the address of flash EEPROM in a non-volatile memory 31. The redundant memory 25 can be incorporated in a data processor such as a micro controller 20 containing a central processing unit 21 and an on-chip peripheral equipment 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor memory, and more particularly to redundant memory and data processors incorporating redundant memory.

[0002]

Semiconductor memories are used to store large amounts of data. These memories can store several bits of information to millions of bits of information. With the progress of technology, the size of memories integrated on various types of data processing chips is increasing.

In computer systems, some problems arise when memory locations produce incorrect data.
One example of a problem is the disabling or indeterminacy of the functionality of a user's application due to the corruption of control data read from erroneous locations stored in a data processor or integrated circuit. Understanding the roots of this problem requires tedious analysis by the user due to the randomness of these anomalies. Therefore, the memory
The component must be fully functional when utilized in a computer system.

[0004]

A random access memory (RAM) is an example of a semiconductor memory that stores a large amount of data in a small chip area. During the manufacturing process, random defects that occur from time to time can cause some of the memory cells to fail, that is, to be unable to store and provide the correct information. However, it is futile to discard the entire chip after testing due to one or a few defective memory cells. Therefore, the industry has come up with a solution, namely redundant memory.

In the past, redundant memory required replacing entire rows or columns to restore a single bit in order to prevent discarding the entire chip. Traditionally, this includes
By disconnecting and connecting using laser hardware,
It involves exchanging defective bits with redundant rows or columns. Finding the exact physical location on a silicon wafer or die requires the program to calculate and store the location so that the laser machine can cut the defect location and repair the defect location in redundant locations. . This procedure requires the purchase of laser hardware and significant test time, and substantially increases the overhead.

[0006] When a row and / or column is cut and repaired, another problem arises: first, it increases the column capacity for row redundancy and also increases the row capacity for column redundancy. Decoding time increases due to the second
Finally, there is an increase in die size area which leads to an increase in final product cost.

The problem of increased decoding time has several aspects. When implementing row or column redundancy, the extra rows or columns must be decoded, which adds capacity. Also, time must be added by selecting a redundant row or column and deselecting the row or column in the main array when the redundant row or column is selected by the decoder. Note that increasing capacity increases delay and access time. Memory access time is measured from the time a valid input address is provided to the memory to the time the data being accessed is valid on the data bus.

Dynamic random access memory (DRAM), static random access memory
Memory (SRAM), Read Only Memory (RO
M), EPROM (electrically programmable ROM),
EEPROM (electrically erasable and programabl
Various user memories, including eEPROM) and block erasable EEPROM (flash EEPROM), can utilize redundant techniques to replace defective rows and / or columns. However, if the memory is built into the microcontroller, the memory may not be accessible in all modes of operation. In order to bring these memories fully operational for user applications, there was a need for a method that allowed the customization of the configuration of non-volatile memory cells that provided redundancy. Therefore, US Pat. No. 5,179,536 "SE
MICONDUCTOR MEMORY DEVICE HAVING MEANS FOR REPLACI
NG DEFECTIVE MEMORY CELLS "start of defective blocks detected during testing of memories such as those taught by
The address was stored in a non-volatile memory address.

One example of a row / column redundancy scheme requires an address buffer, row decoder, column decoder, sense amplifier and memory cell array.
The address buffer couples the input address to the row and column decoders that generate the row and column address signals. The comparator detects if the input address matches the current defective row / column. If there is a match, the select circuit enables the redundant memory portion to drive. If they do not match, but the input address is within the memory range, a non-redundant row / column is selected. Once the correct location is decoded, the sense amplifier detects the data and drives it on the microcontroller's data bus. This type of redundant memory requires the address buffer to decode both the main memory and the redundant memory, which of course increases the time to decode the address.

[0010]

Therefore, defective parts in a memory array can be replaced without requiring special hardware, and a large integrated circuit area is not added, and decoding time and detection time are not significantly reduced. , Redundant memory technology is needed. Such a memory and a data processor utilizing this memory are provided by the present invention, the features and advantages of which will be apparent from the following detailed description in conjunction with the accompanying drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a redundant memory (REDUNDANT) according to the present invention.
A data processor in the form of a microcontroller 20 with a MEMORY) 25 is shown in a block diagram. The microcontroller 20 is an integrated circuit microcontroller, typically a central processing unit (CPU) 21, address
Bus (ADDRESS BUS) 22, Data bus (DATA BUS) 2
3. Peripheral device (PERIPHERAL) 24 and redundant memory (REDUN)
DANT MEMORY) 25 is included. CPU 21 has an output terminal connected to address bus 22 and a bidirectional terminal connected to data bus 23. Peripheral device 24 has an input terminal connected to address bus 22 and a bidirectional terminal connected to data bus 23. Redundant memory 2
5 has an input terminal connected to address bus 22 and a bidirectional terminal connected to data bus 23.

The redundant memory 25 is a main memory (MAIN
MEMORY) 30, non-volatile memory (NON-VOLATILE MEMORY)
31, multiplexer (MUX) 32 and cache
(CACHE) 40 is included. The main memory 30 has an input terminal connected to the address bus 22 and a bidirectional terminal. The non-volatile memory 31 has a bidirectional terminal connected to the data bus 23 and an output terminal. MUX32
Has a first bidirectional terminal, a second bidirectional terminal connected to the bidirectional terminal of the main memory 30, and a bidirectional terminal connected to the data bus 23. The cache 40 is
It includes a tag portion 41 labeled "TAG" and a data portion 42 labeled "DATA". Tag portion 41 has an input terminal connected to address bus 22 and an output terminal for providing a control output signal labeled "TAG HIT" 26. The data portion 42 is connected to the tag portion 41 and has a bidirectional terminal connected to the first bidirectional terminal of the MUX 32.

Main memory 30 is a conventional memory array in which data elements are arranged in rows and columns. In response to the input address, the word line driver activates the word line that selects a row. Another portion of the address enables the column decoder to select the selected row, ie, the column of the specified number of memory cells located in the specified data word. In main memory 30, each row consists of multiple data words, and these data words are
Consisting of multiple memory cells, each memory cell is a row /
Located at the column intersection.

According to the invention, the microcontroller 2
0 is a redundant memory 2 which provides redundancy in word units without adversely affecting the access time of the main memory 30.
5 is included. The redundant memory 25 includes a main memory 30 as a main memory array. Main memory 30
For information on defective memory addresses of the non-volatile memory 31
With cache 40. During testing, a defective memory word in the main memory 30 is detected and the non-volatile memory is detected by the conventional VLSI programming method at the patch address corresponding to the defective memory word in the main memory 30. 31 is programmed.

In operation, the patch address of the defective word address detected in the main memory 30 during the test and programmed in the non-volatile memory 31 during the reset of the microcontroller 20 during operation is transferred into the tag portion 41 of the cache 40. To be done. After that, during normal operation, the MU
X32 selectively connects data bus 23 to either main memory 30 or data portion 42 of cache 40 as determined by tag hit signal 26. It should be understood that normal operation in the context of this description is the point in time when the microcontroller 20 is not in the reset state. In addition to transferring the patch address stored in non-volatile memory 31 to tag portion 41 and data portion 42, the operation of the data processor during the reset state is well known in the art and will not be described in further detail. During normal operation, when the redundant memory 25 receives an address in the range associated with the redundant memory 25 that is conducted on the address bus 22, the cache 40 causes the main memory 30 to decode the corresponding address. First, it is determined whether the patch address stored in the tag portion 41 matches the address conducted on the address bus 22. When the conducted address matches the patch address, the tag portion 41
Activates the output signal tag hit 26 to MUX 32 to select its first bidirectional terminal and connect it to data bus 23. At the same time, the tag hit in tag portion 41 selects the appropriate data word in data portion 42, which is connected to data bus 23 via MUX 32. The tag selection and connection to the data bus 23 is made independent of the decoding circuit of the main memory 30 and therefore does not affect its access time. If the tag address does not match the address conducted on the address bus 22, the access is
As usual in memory 30, the output signal tag hit 26 from tag portion 41 becomes inactive,
Thereby, the Max 32 has the second both terminals, that is,
The terminal connected to the bidirectional terminal of the main memory 30 is selected and connected to the data bus 23.

When connecting to the data bus 23, leads,
Any type of access such as write, program or erase can be performed on either the non-volatile memory 31, the data portion 42 or the main memory 30.

Generally, the microcontroller 20 has a C
It has each of the three main blocks of a typical computer system on a single integrated circuit chip, including memory in the form of a PU 21, peripherals 24 and redundant memory 25. The CPU 21 is a RISC (reduced instructi)
on set computer), CISC (complex instruction set)
computer), digital signal processor (DSP) or any other known architecture, including known or conventional CPU architectures. CPU 21
Executes programmed instructions, which are stored on-chip from the perspective of the microcontroller,
It may be stored in the redundant memory 25. The peripheral device 24 is
It may be any conventional input / output module such as serial or parallel input / output ports, timers, etc. Further, the redundant memory 25 stores the operation parameter and the CPU 21.
A data scratch pad area can be provided for. Alternatively, the microcontroller 20 may include different classes of memory besides the redundant memory 25.
In such a case, one of the two memories may be a non-volatile memory for storing program instructions and operating parameters and the second memory may be a random access memory (RAM). The microcontroller 20
It may have some memory portions with defective memory cells, which require redundancy to function fully. The redundant memory 25 of the present invention can also be used when each memory portion has a different class of memory than the main memory 30. In this case, the main memory 30
Stores operating parameters, or redundantly CPU
Provide a data scratch pad area for 21
Higher accuracy can be achieved. That is, if main memory 30 is not the memory in which most of the opcodes and operands, whether internal or external to microcontroller 20, are stored, redundant memory 25 provides the functionality that that portion of memory previously had. Can be replaced.

FIG. 1 shows one possible microcontroller within the microcontroller family. Microcontroller 20 is only one example of such a microcontroller, as microcontrollers within the same data processor family typically have several different onboard peripherals. In another embodiment, the microcontroller 20 may include some onboard peripherals such as a system integrated module, serial communication module, timer module or other redundant memory, all of which correspond to the corresponding integrated circuit pins. Can have. Further, in the present embodiment, cache 40 can utilize addresses conducted on address bus 22 to determine a match, but the received address need only be a portion of address bus 22. further,
If the microcontroller 20 utilizes address translation or address encryption, respectively, the received address may be the translated or encoded version of the address bus 22, or a portion thereof. Finally, the coprocessor may be configured within the microcontroller 20.

In the embodiment shown in FIG. 1, the main memory 3
0 and the non-volatile memory 31 are flash EEPROM
Note that it consists of M cells. The tag portion 41 and the data portion 42 are composed of static latches. However, in another embodiment, the main memory 3
0 is a static random access memory (S
RAM), dynamic random access memory (DRAM), non-volatile random access memory (NVRAM), programmable read only memory (PROM), erasable PROM (EPROM),
It may comprise other types of memory including electrically erasable PROM (EEPROM). In general, if main memory 30 is a non-volatile memory, non-volatile memory 31 is preferably of the same type as main memory 30 for sharing control logic. However, the non-volatile memory 3 may or may not share the control logic.
1 need only be non-volatile. If the main memory 30 is a ROM, the non-volatile memory 30 is a ROM
First, it is difficult to know which ROM address in the main memory is defective at the time of manufacturing, that is, before the test.
This is because the OM is not programmable.

It should also be noted that in other embodiments it may be preferable to combine the non-volatile memory 31 of FIG. 1 and the cache 40 into a single circuit. In this case, the tag portion 41 and the data portion 42 may be any conventional non-volatile memory that retains a value when the redundant memory 25 is powered down. In this case, the configuration being reset can be bypassed. Finally,
In another embodiment, the function of MUX 32 is that the data portion 42 depends on whether a tag hit was activated.
Alternatively, it may be only for connecting the redundant memory 50 to the data bus 23. 2 shows a block diagram of redundant memory 50, showing a specific example of a redundant memory that can be used as redundant memory 25 of FIG. The redundant memory 50 has an address
It has an input terminal connected to bus 52 and a bidirectional terminal connected to data bus 54. In addition, the redundant memory 5
0 receives a reset input signal labeled "RESET" 56. The redundant memory 50 is generally a main memory (MAIN MEMORY) unit 60, a shadow unit 70,
It includes an input / output unit 80, a cache 90 and a sequencer 200.

The main memory section 60 is a row decoder.
(ROW DECODER) 61, Memory array (MEMORY ARRAY) 6
2 and a column decoder (COLUMN DECODER) 63. Row decoder 61 has an input terminal for receiving a part of a signal conducted on address bus 52, and an output terminal. Memory array 62 has an input terminal connected to the output terminal of row decoder 61, and a bidirectional data terminal. The column decoder 63 has a first bidirectional terminal connected to a set of data lines labeled "GLOBAL DATA LINE BUS" 59, and a first bidirectional terminal that receives a reset control signal 56. A second terminal connected to the input terminal and the data terminal of the memory array 62
It has a bidirectional terminal and a second input terminal for receiving a portion of the signal conducted on address bus 52.

The shadow section 70 includes a non-volatile shadow memory (NON-VOLATILE SHADOW MEMORY) 71 and a shadow decoder (SHADOW DECODER) 72. Nonvolatile shadow memory 71 has an input terminal for receiving reset 56, and a bidirectional terminal. Shadow decoder 72
Is a first input terminal for receiving a part of the signal conducted on the address bus 52, and a tag hit (TAG HIT).
A second input terminal for receiving the control signal, a first bidirectional terminal connected to the global data line bus 59, and a second bidirectional terminal connected to the bidirectional terminal of the nonvolatile shadow memory 71. Have.

The input / output unit 80 provides a multiplexer function between the main memory 60 and the cache 90, and has an internal I / O MUX unit 81 and a program load (PROGRAM).
LOAD) section 82 and sense amplifier (SENSE AMP) 83. The internal I / O MUX unit 81 uses the reset control signal 5
6, the first input terminal receiving 6 and the tag hit control signal 62
A second input terminal for receiving, a third input terminal, an output terminal, and a first bidirectional terminal connected to the data bus 54,
A second bidirectional terminal. Program load section 82
Has an input terminal connected to the output terminal of the internal I / O MUX section 81 and an output terminal connected to the global data line bus 59. The sense amplifier 83 is
It has an input terminal connected to the global data line bus 59 and an output terminal connected to the third input terminal of the internal I / O MUX section 81.

The cache 90 has a reset control signal 56.
A first input terminal for receiving a portion of a signal conducted on the address bus 52, and an internal I / O
It has a bidirectional terminal connected to the second bidirectional terminal of the MUX unit 81, and an output terminal for providing the tag hit output signal 62. The cache 90 stores "redundant tag enable (R
EDUNDANCY TAG ENABLE (RTE) "101, comparator (COMPA
RATOR) 102 and redundant data part (REDUNDANT DATA PO
RTION) 91 is included. The cache 90 is
It may include multiple entries that store redundant data.
FIG. 2 shows a typical entry having an RTE field 101, a comparator field 102 and a redundant data field 91. The RTE field 101 has an output terminal that provides an output. Comparator 102 is RTE1
A first input terminal controlled by the output terminal 01 and a second input terminal receiving a portion of the signal conducted on the address bus 52.
It has an input terminal and an output for providing a tag hit signal 62. Sense amplifier 83 has an input terminal connected to a bus labeled "Global Data Line Bus" 59. If no redundancy is required, the comparator 10
Part 2 is kept inactive and cache 9
Note that virtually zero power consumption is saved.

The sequencer 200 uses the reset control signal 5
A first input terminal for receiving 6 and a predetermined number of bits described as "N BITS" on the address bus 52.
The address bus 52 has a row decoder block 61, a column decoder block 6 and an output terminal.
3, internally connected to shadow decoder 72 and cache. Within the sequencer 200 is a counter 201 that provides an N-bit output when the reset control signal 56 is active. In addition, sequencer 200 provides other control signals to each block within redundant memory 50, which is not described herein.

In operation, during the reset state, the counter 20
1 transfers control, address and data information from the non-volatile shadow tag and data portion 71 to the RT
A sequence for storing in the E field 101, the comparator field 102 and the redundant data field 91 is generated. Specifically, the redundant tag enable control bits are loaded into RTE section 101 and the patch address of the defective memory word in memory array 62 is loaded into comparator field 102. Also,
If memory array 62 is a non-volatile memory, the data associated with the defective memory word may be loaded into redundant data field 91. Non-volatile shadow
This information from the memory 71 to the shadow decoder 72 is provided on the global data line bus 59, converted by the sense amplifier 83 and also the internal I / O.
It is coupled to a particular non-volatile memory cache field via the O MUX portion 81.

After the reset state, the RTE field 10
When 1 enables the comparator 102, the address comparator output, the tag hit signal 62, causes the address bus 5 to
It is activated when the address conducted on 2 matches the address field stored in the comparator 101. Redundant data field 91 is accessed for any array operation instead of the defective array address in memory array 62 when tag hit signal 62 is activated. Since the redundant data access is performed in parallel with the access to the main memory unit 60, the redundant data access does not increase the access time.

During the programming and erasing sequence of the redundant memory 50, if the redundant memory 50 is a non-volatile memory, a random control logic (RCL) is used.
ic) activates the programming voltage and control signals to the appropriate section in redundant memory 50 by methods well known in the art. Although not shown here, the same RCL circuit used to program the main memory section 60 during normal operation is used to program and erase the non-volatile shadow memory 71 during test mode.

The cache 90 of FIG. 2 is a two-way associative cache (two) with a total of four entries.
-way associative cache). However, the cache 90 is a direct mapped cache (direct ma
pped cache), full associative cache (ful
It is understood that it may be a ly associative cache) or any other type of cache, including any number of associative caches.

Existing complementary metal oxide semiconductor (CMO)
S) Using circuit design techniques, the effect of most areas with non-volatile memory tags (NVMT) is not shown, but random control logic (RCL) within sequencer 200.
Where an increase of about 10% per NVMT is obtained. RCL is believed to occupy approximately 8% of the total 128 Kbyte flash area. 128K bytes
The increase in flash EEPROM area is about 0.5% per NVMT. In contrast, another known redundancy method is a 128 Kbyte flash EEPROM.
Utilizing arrays requires about 4% more area per row, about 6% per column and about 8% more area per data structure.

When applied to these estimated percentiles, standard integrated circuit manufacturing textbooks must be consulted for defect density and yield information. The trade-off to select the optimal number of NVMTs to use is
NV and the design complexity embedded in the random control logic
Both the system improvements that MT brings should be considered.

Thus, a redundant memory is provided which improves access time, reduces area, and reduces the number of normal cells exchanged with defective memory as compared to known methods. Will be clear.

In one aspect of the invention, the cache (4
0,90) data part (42,91) and main
The memory (30, 60) is a memory of the same class.

In another aspect of the invention, the main memory (60) is composed of a row decoder (61), a column decoder (63) and a memory array (62). The row decoder (61) has an input for receiving the first portion of the address, and activates a selected row of the plurality of rows in response to the first portion of the address input. The column decoder (63) has an input for receiving a second portion of the address, and at least two of the plurality of columns for coupling the data terminals of the main memory (60).
Choose one. The memory array (62) has a plurality of memory cells, each memory cell being coupled to one of the plurality of rows and one of the plurality of columns.

In yet another aspect of the invention, the column decoder (63) further selects a plurality of second memory cells in response to the second portion of the address input, where the first memory cells are selected. And a plurality of second memory cells form a data word on one of the plurality of rows, and each of the plurality of rows form a plurality of data words.

In yet another aspect of the invention, the non-volatile memory (31, 70) is programmable during normal operation of the redundant memory (25, 50).

Another aspect of the invention is characterized in that the non-volatile memory (31, 70) is programmable during the test mode of the redundant memory (25, 50).

In yet another aspect of the invention, the cache (40) is further configured with a redundant tag enable field (RTE) (101), which RTE
Enables the comparison of the patch address with the input address in response to its logic state.

In yet another aspect of the invention, the tag portion (102) has a first input for receiving a patch address,
It consists of a comparator having a second input for receiving the input address and an output for providing the tag hit signal (26).

In another aspect of the invention, the comparator further has an enable input coupled to the redundant tag enable field (101).

According to yet another aspect of the present invention, the main memory (30, 60) is a cache memory.

In yet another aspect of the invention, the data processor (20) is a microcontroller and is coupled to the address bus (22,52) and the data bus (23,54). Peripherals (24)
Is further included. In yet another aspect of the invention, the step of detecting and storing during the test mode further comprises the step of detecting and storing during a probe test of the main memory (30, 60).

Although the present invention has been described in terms of a preferred embodiment, those skilled in the art will appreciate that modifications and variations can be made without departing from the spirit of the invention. For example, the main memory 30 includes SRAM, DRAM, RO
M, PROM, EPROM, EEPROM, FLASH
Any type of memory such as EPROM or NVRAM may be used. Further, the microcontroller according to the present invention includes a C
Any known CPU architecture such as ISC, RISC, DSP may be utilized with redundant memory 25 and may include various peripherals. Therefore,
The invention is intended to cover all such variations and modifications within the scope of the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data processor in the form of a microcontroller with redundant memory according to the invention.

FIG. 2 is a block diagram showing a redundant memory that can be used as the redundant memory in FIG.

[Explanation of symbols]

 20 Micro Controller 21 Central Processing Unit (CPU) 22 Address Bus 23 Data Bus 24 Peripheral Device 25 Redundant Memory 30 Main Memory 31 Nonvolatile Memory 32 Multiplexer (MUX) 40 Cache 41 Tag Part 42 Data Part 50 Redundant Memory 52 Address Bus 54 data bus 56 reset 60 main memory unit 61 row decoder 62 memory array 63 column decoder 70 shadow unit 71 non-volatile shadow memory 72 shadow decoder 80 input / output unit 81 internal I / O MUX unit 82 Program load section 83 Sense amplifier 90 Sequencer 91 Redundant data section 101 Redundant tag enable (RTE) 102 Comparator 200 Sequencer 201 Counter

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Thomas Jew Bluff Springs Road 6503, Number 1006, Number Austin, Texas, USA

Claims (5)

[Claims] A redundant memory (25, 50): a main memory (30, 60) having a plurality of rows and a plurality of columns, an address input, and a data terminal, wherein the address input Responding to the received address,
The main memory (30, 60) selects a first memory cell, the first memory cell representing a portion of the selected row, the main memory (30, 60); a patch
A non-volatile memory (3 having an address for storing an address
1, 70); a tag portion (4) coupled to the non-volatile memory (31, 70) and storing the patch address.
1, 100) and data corresponding to the patch address and connected to the data terminal (4)
2, 91) and an external data bus (23, 54) on the cache (40, 90) when the input address matches the patch address of the cache (40, 90). , 90) and the input address is the main
A multiplexer (32,80) for coupling the first memory cell of the main memory (30,60) to the external data bus (23,54) when in the category of a memory (30,60); Redundant memory (25, 50) characterized by being configured by: 2. A redundant memory (25, 50) comprising: a main memory (30, 60) having a plurality of rows and a plurality of columns, an address input, and a data terminal, wherein the address input Responding to the received address,
The main memory (30, 60) selects a first memory cell, the first memory cell representing a part of the selected row, the main memory (30, 60); receiving a patch address A cache (40, 90) having a tag portion (41, 100) for storing and a redundant data portion (42, 91) for storing data corresponding to the patch address and coupled to a data terminal; and an input address If it matches the patch address of the cache (40, 90), the external data bus (23, 54) is coupled to the data terminal of the cache (40, 90), and the input address is the main address. The first of the main memory (30, 60) if it is in the memory category
Redundant memory (25, 50) characterized by a multiplexer (32, 80) coupling a memory cell to said external data bus (23, 54). 3. A method for providing redundancy to a main memory (30,60) comprising: the main memory (3).
Detecting defective memory cells at 0, 60);
Storing a patch address corresponding to the defective memory cell in the tag portion (41, 100) of the cache (40, 90); receiving an input address; comparing the patch address with the input address; If the patch address matches the input address,
The data portion (42, 9) of the cache (40, 90)
1) to the data bus (23, 54); and if the patch address does not match the input address, the input address is in the category of the main memory (30, 60). Sometimes connecting the data terminals of the main memory (30, 60) to the data bus (23, 54). 4. A data processor comprising: an address bus (22, 52); a data bus (23, 54);
The address bus (22, 52) and the data
A central processing unit (21) coupled to the buses (23, 54) for processing instructions and accessing data; and the address buses (22, 52) and the data buses (3).
0,60) redundant memory (25,50), said redundant memory comprising: a main memory having a plurality of rows and a plurality of columns, an address input and a data terminal.
A memory (30, 60) for responding to an address received at the address input,
0,60) selects a first memory cell, said first memory cell representing a part of the selected row; and a main memory (30,60); a tag portion storing a patch address. (41,100) and a cache (40,9) having data corresponding to the patch address and having a data portion (42,91) coupled to a data terminal.
0) and: the input address is the cache (40, 90)
The data bus (23, 54) to the cache (40, 90) when it matches the patch address of
The first memory cell of the main memory (30, 60) is coupled to the data bus of the main memory (30, 60) when the data input address is in the category of the main memory (30, 60). A data processor (20) comprising a redundant memory (25, 50) consisting of a multiplexer (32, 80) coupled to (23, 54). 5. A method for providing redundancy to a main memory (30, 60) comprising: main memory (3).
Detecting defective memory cells at 0, 60);
Storing the patch address corresponding to the defective memory cell in the non-volatile memory (31, 70); loading the patch address into the tag portion (41, 100) of the cache (40, 90); Receiving an address; comparing the patch address with the input address; storing the data portion (42, 91) of the cache (40, 90) when the patch address matches the input address; Bus (23,5
4); and the main memory (30, 60) when the input address is in the category of the main memory (30, 60) if the patch address does not match the input address. , 60) of the data terminal to the data bus (23, 54);
A method characterized by comprising: