JPH09186315A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the withstand voltage of a semiconductor device form being reduced and to make it possible to prevent a diode from being broken due to a field concentration by a method wherein the relation between the distance between the junctions at both end parts of an overvoltage inhibiting diode and the distance between a junction at the end part, which is located on the gate electrode side, of the inhibiting diode and the outermost peripheral terminal of an FLR is specified. SOLUTION: In a semiconductor element consisting of a withstand voltage holding region, which is formed on an oxide film 121 and has a polycrystalline diode, the distance L1 between a fifth layer, which is closest to an IGBT region, and a fifth layer, which is furthest from the IGBT region, is set 4/5 or shorter of the distance L2 between the junction between polycrystalline silicon diodes, which is closest to the IGBT region, and the junction between the polycrystalline silicon diodes, which is furthest from the IGBT region. In this relation, as a change in a potential in the outer peripheral part of a field limiting ring(FLR) is equalized by an overvoltage inhibiting diode 130, a field concentration is not generated and the withstand voltage of a semiconductor device is not reduced. A potential distribution becomes equal in the outer periphery of the FLR by the diode 130 and the deterioration of the withstand voltage of the device can be prevented from being generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IGBT including a feedback diode and an overvoltage suppressing diode, and more particularly to an inverter IGBT.

[0002]

2. Description of the Related Art In recent years, energy depletion on a global scale has become a serious problem, and there is a strong demand for energy saving of electric systems. In addition, as industrial equipment has become more sophisticated and complex, driving equipment such as motors are required to have higher performance, smaller size, lower noise, and improved usability. In order to meet these demands, the conversion of drive equipment into inverters is being promoted, and from the field of consumer equipment such as air conditioners and lighting,
Inverters have been widely applied to large power fields such as steel and electric trains.

In order to improve the performance of the inverter, it is essential to improve the performance of the switching element. Recently, insulated gate bipolar transistors (hereinafter referred to as IGBTs) have been widely used in place of thyristors and GTOs. The IGBT is an element that has both high-speed switching characteristics of a MOSFET and high output characteristics of a bipolar transistor, and is effective for energy saving and downsizing of an inverter.

FIG. 2 shows a circuit of a three-layer full bridge inverter using an IGBT. In FIG. 2, 200 is IG
BT, 201 is a feedback diode, 210 and 211 are DC terminals connected to a DC power source, and 212 to 214 are AC terminals connected to a load.

Since the IGBT is a voltage drive type element, if it is applied to an inverter, the drive circuit can be downsized and the drive power can be reduced. Further, since the operating speed is high, there are advantages that the frequency of the inverter can be increased and noise can be reduced. For these reasons, it is widely applied to the field of consumer equipment such as air conditioners, lighting, and heat appliances, and it is considered that the field of application will be further expanded in the future. However, for that purpose, it is necessary to further improve reliability and reduce cost.

Highly reliable and low cost IGBT for inverter
IGB that integrates the circuit configuration shown in FIG.
T is being considered. FIG. 4 is a diagram showing a sectional structure when the circuit of FIG. 3 is incorporated in an IGBT. 3 and 4, the same components as those in FIG. 2 are designated by the same reference numerals. In FIG. 3, 110 is a gate electrode, 111 is an emitter electrode, 112 is an overvoltage suppressing diode gate side electrode, 113 is an overvoltage suppressing diode collector side electrode, 1
15 is a collector electrode, 130 is an overvoltage suppressing diode,
300 is an IGBT, 301 is a gate-emitter resistance,
302 is a feedback diode. Also, in FIG.
100 is a collector layer, 101 is a buffer layer, 102 is a drift layer, 103 is a base layer, 104 is a source layer, 10
5 is an electric field relaxation structure for maintaining the breakdown voltage (hereinafter referred to as Field
Limiting Ring: referred to as FLR layer), 106 is a cathode layer, 114 is a cathode wiring, 120 is an interlayer insulating film, 12
Reference numeral 1 is an oxide film, 400 is an arrow that schematically shows the current path of the feedback diode, and 401 is a symbol that conveniently shows the feedback diode. The overvoltage suppressing diode 130 is p
The drift layer 102 is insulated from the drift layer 102 by an oxide film, which is made of polycrystalline silicon in which the type layers and the n-type layers are alternately arranged. The number of repeating arrangements of the p-type layer and the n-type layer is IGBT.
Of the device withstand voltage of 600V.
It is about 40 to 80 series in GBT. Although not shown, the gate electrode 110 is connected to the overvoltage suppressing diode gate side electrode 112, and although not shown, a gate-emitter resistor 301 is provided between the gate electrode 110 and the emitter electrode 111. It is connected. Further, the region in which the IGBT cell is formed is called a conduction region, and the region in which a structure for holding the breakdown voltage is formed is called a breakdown voltage holding region.

First, the operation of the overvoltage suppressing diode will be briefly described. When an overvoltage is applied between the collector and the emitter, the overvoltage suppressing diode 130 breaks down and a current flows between the collector and the gate. This current flows through the gate-emitter resistor 301 to increase the gate potential VG, turn on the IGBT, and suppress the increase in overvoltage. By adding this diode to the IGBT,
The breakdown resistance of the IGBT against overvoltage can be improved, and the device can be downsized by making it snubberless. If the structure shown in FIG. 4 is incorporated in the IGBT, this function can be added without increasing the volume of the device. An IGBT with an overvoltage suppressing function is disclosed in Japanese Patent Laid-Open No. 2-185069.

Next, the operation of the feedback diode will be described. When a reverse bias is applied to the IGBT in the regenerative mode of the inverter, the feedback diode 302 shown in FIG.
Conducts. This feedback diode is the base layer 10 of FIG.
3, it is formed at the junction of the drift layer 102, and is indicated by 401 in FIG. The feedback diode current flows through path 400 to the collector electrode. By incorporating the feedback diode in the IGBT, the three-layer full-bridge inverter circuit of FIG. 2, which has been conventionally composed of 12 semiconductor elements, can be composed of 6 semiconductor elements, and the size can be further reduced. Such a feedback diode built-in IGBT is disclosed in, for example, Japanese Patent Application No. 2-512038.

If the above two measures for high reliability and low cost are simultaneously applied to the IGBT, a highly reliable and low cost IGBT can be realized.

[0010]

However, an IGBT incorporating the above-described overvoltage suppressing diode and feedback diode is incorporated.
Has the following problems.

The first problem is that the breakdown voltage of the device is lowered because the potential distribution of the overvoltage suppressing diode 130 does not match the potential distribution of the FLR 105. FIG.
The potential distribution by the overvoltage suppressing diode is shown in (a),
The potential distribution by FLR is shown in (b). In the case of the overvoltage suppressing diode, since the collector-emitter voltage is evenly shared by each of the p-type n-type repeating layers, the potential distribution shows a uniform equipotential line as shown by 500 in FIG. 7 (a). .
On the other hand, in the case of the FLR structure, the distribution of equipotential lines changes depending on the interval between adjacent FLRs. In general, I
Since the FLT of GBT can stably maintain the withstand voltage,
In many cases, the configuration is such that the potential change increases as it approaches the edge of the chip.

However, the overvoltage suppressing diode and the F
In the structure of FIG. 4 to which the LR structure is applied at the same time, the potential distribution due to the overvoltage suppressing diode and the potential distribution due to the FLR do not match each other, which causes a problem that the breakdown voltage decreases.
This is shown in FIG. FIG. 6 shows a potential distribution that takes into consideration the interaction between the potential distribution by the FLR and the potential distribution by the overvoltage suppressing diode. As shown in FIG. 6, since the electric potential distributions of the two do not match, a portion where the electric field is concentrated occurs, which causes a breakdown phenomenon to lower the breakdown voltage of the device.

The second problem is a breakdown phenomenon due to current concentration in the feedback diode. This will be described with reference to FIG. FIG. 7 is a plan view of an IGBT chip having an overvoltage suppressing diode and a feedback diode built-in, and in particular, an enlarged view of a corner portion of the chip. 7, the same components as those in FIGS. 2 to 6 are designated by the same reference numerals. In FIG. 7, 700 is a current line schematically showing the current of the feedback diode. As can be seen from FIG. 7, the current density of the feedback diode is higher at the corners of the chip than at other places, and the temperature rise due to energization becomes large. As is well known, since the current of the diode has a positive temperature characteristic, the current of the feedback diode increases at the corner of the chip as the temperature rises.
This becomes positive feedback, the current continues to increase, and eventually it is destroyed. In addition, there is a problem in that, if there is a portion where a current flows more easily than other places other than the corner portion of the chip, current concentration occurs and the diode is destroyed due to the positive feedback described above.

An object of the present invention is to solve the above-mentioned problems, in which the breakdown voltage is prevented from being lowered by optimizing the potential distribution of the overvoltage suppressing diode and the FLR, and the breakdown due to the current concentration of the feedback diode is prevented. Low cost,
It is to provide an inverter IGBT with low loss and high reliability.

[0015]

Means for Solving the Problems To solve the above problems,
The following means are conceivable as means for achieving the object of the present invention.

That is, a first conductive type first layer having a pair of main surfaces and in contact with one main surface, and a second conductive type first layer adjacent to the first layer and the other main surface. Second layer, a semiconductor substrate comprising a first electrode formed on one main surface, and a first conductivity type first selectively formed in the second layer adjacent to the other main surface. 3 layer, a fourth layer of the second conductivity type selectively formed in the third layer adjacent to the other main surface, and an insulating portion on the exposed portion of the other main surface of the third layer An IGBT region in which an IGBT composed of a second electrode formed through a film and a third electrode formed in contact with the third layer and the fourth layer is repeatedly arranged, and the IGBT region is surrounded. And a plurality of fifth layers of the first conductivity type selectively formed adjacent to the other main surface in the second layer, and the other main surface in the second layer. A sixth layer of the second conductivity type selectively formed adjacent to the surface and the end surface of the semiconductor substrate;
A fourth electrode formed in contact with the first electrode and electrically connected to the first electrode, an oxide film formed on the other main surface excluding the sixth layer, and one end portion thereof. Is formed on the oxide film by being composed of a plurality of layers of the first conductivity type and the second conductivity type, the second electrode being connected to the second electrode, the other end being connected to the fourth electrode, and being repeatedly arranged between both ends. And a withstand voltage holding region having a polycrystalline silicon diode and a I layer from the fifth layer closest to the IGBT region.
The distance L1 to the fifth layer farther from the GBT region is 4 / of the distance L2 from the junction closest to the IGBT region of the polycrystalline silicon diode to the junction farthest from the IGBT.
It is a means of 5 or less.

A first conductive type first layer having a pair of main surfaces and in contact with one main surface, and a second conductive type first layer adjacent to the first layer and the other main surface. A semiconductor substrate comprising a second layer and a first electrode formed on one main surface;
A third layer of the first conductivity type selectively formed in the second layer adjacent to the other main surface; and a third layer selectively formed in the third layer adjacent to the other main surface. A fourth layer of the second conductivity type, a second electrode formed on an exposed portion of the other main surface of the third layer via an insulating film, a third layer and a fourth layer. An IGBT region in which an IGBT including a third electrode formed in contact is repeatedly arranged, and surrounds the IGBT region,
A second layer of the second conductivity type selectively formed in the second layer adjacent to the other main surface and the end surface of the semiconductor substrate; and in contact with the fifth layer, A fourth electrode electrically connected to the first electrode, an oxide film formed on the other main surface excluding the fifth layer, and one end portion of the second electrode
The other end of the electrode is connected to the fourth electrode, and is composed of a plurality of first-conductivity-type and second-conductivity-type layers repeatedly arranged between both ends, and is formed on the oxide film. In a semiconductor element including a breakdown voltage holding region having a silicon diode, the interval between the first conductive type and the second conductive type repeating arrays of the polycrystalline silicon diode is wide on the second electrode side and on the fourth electrode side. Is a narrowing means.

Further, there is provided a seventh layer of the first conductivity type which is in contact with the fourth layer located at the end of the IGBT region and is selectively formed adjacent to the other main surface, The seventh layer is formed on the IGBT region side of the junction closest to the end of the polycrystalline silicon diode on the IGBT region side. The distance L3 from the contact position between the third electrode and the fourth layer located at the end of the IGBT region to the end of the seventh layer on the breakdown voltage holding region side is 20 μm or more.

At least one connected to the fourth electrode
1 or more first wirings, and any one of the first wirings
There is a first point on the fourth electrode farthest from the book, and the distance L4 between this first point and any one of the first wirings,
The cross-sectional area A of the fourth electrode, the current I flowing through the fourth electrode, and the resistivity ρ of the fourth electrode satisfy 0.035 ≧ ρ × (L4 / A) × I / 2 It is a means.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a sectional structure of a first embodiment according to the present invention. In FIG. 1, 100 is a collector layer, 101 is a buffer layer, 102 is a drift layer, 10
3 is a base layer, 104 is a source layer, 105 is an FLR layer,
106 is a cathode layer, 110 is a gate electrode, 111 is an emitter electrode, 112 is an overvoltage suppressing diode gate side electrode, 113 is an overvoltage suppressing diode collector side electrode, 11
4 is a cathode wiring, 115 is a collector electrode, 120 is an interlayer insulating film, 121 is an oxide film, and 130 is an overvoltage suppressing diode. Further, in FIG. 1, L1 is the distance between the junctions at both ends of the overvoltage suppressing diode, and L2 is the distance from the junction at the end on the gate electrode side of the overvoltage suppressing diode to the end of the outermost FLR.

The feature of this embodiment is that L1 and L2 satisfy the relationship of L2 ≦ (4/5) × L1 (1). It has been experimentally confirmed that when L2 does not satisfy the above condition, that is, when L2 ≧ (4/5) × L1, the breakdown voltage sharply decreases.

When the expression (1) is satisfied, the electric field concentration as shown in FIG. 6 does not occur because the overvoltage suppressing diode equalizes the potential change in the FLR outer peripheral portion shown in FIG. Does not fall. In order to match the potential distribution of the FLR with the potential distribution of the overvoltage suppressing diode, L1 is set to L
It is effective to make it 20% longer than 2. The potential distribution at this time is shown in FIG. On the outer periphery of the FLR, the overvoltage suppressing diode makes the potential distribution uniform and prevents the breakdown voltage from deteriorating.

FIG. 9 is a plan view of the IGBT of the first embodiment. The same components as those in FIGS. 2 to 8 are designated by the same reference numerals. In FIG. 9, 900 is a gate pad to which a gate wire is connected, 901 is an emitter pad to which an emitter wire is connected, and 902 is a gate wiring.
The overvoltage suppressing diode is formed so as to surround the periphery of the chip in the range indicated by the arrow 130. Also, FLR1
Reference numeral 05 is formed below the overvoltage suppressing diode 130 in FIG. 9, and is shown by a dotted line. Although not shown, the cathode wiring 114 can be connected to any position on the cathode electrode 113 by any number.

In this embodiment, p of the overvoltage suppressing diode is
Although an example in which the number of repeating n-type layers is 6 has been shown, of course, the invention is not limited to this, and it may be adjusted according to the breakdown voltage of the element.
The number of repeating sequences can be changed. Similarly, the FLR is also shown to have three lines in particular, but the number may be any number. Further, in this embodiment, a so-called punch-through type IGB provided with the buffer layer 101 is used.
Although the example of T is shown, the present invention can be similarly applied to the case of a non-punch through type IGBT that does not have a buffer layer. Of course, these conditions can be similarly considered in the following embodiments.

(Embodiment 2) FIG. 10 is a plan view showing a second embodiment according to the present invention. 2 through FIG.
The same components as those in FIG. 9 are designated by the same reference numerals.
10 is different from FIG. 9 in that the overvoltage suppressing diode is formed only in a region adjacent to the gate pad. The width L1 of the overvoltage suppressing diode is the same as that of the first embodiment.
However, as described above, it must be larger than the width L2 of the FLR. Therefore, the size is larger than that of the structure of the breakdown voltage holding region of only FLR. On the other hand, in the present embodiment, the loss of this area can be reduced by limiting the overvoltage suppressing diode to the region adjacent to the gate pad. That is, the area of the breakdown voltage holding region can be reduced in the region where the overvoltage suppressing diode is not formed, and the element size can be reduced.

However, in the overvoltage suppressing diode according to the present embodiment, since the element size is reduced, the resistance component of the diode increases, and the delay of overvoltage suppressing operation and the loss increase. Therefore, depending on whether it is important to reduce the element area or to reduce the delay or loss of the overvoltage operation, it is necessary to select an appropriate structure of either the first embodiment or the second embodiment. In this embodiment, the example in which the overvoltage suppressing diode 1000 is formed beside the gate pad has been shown. However, the position of the overvoltage suppressing diode is not limited to this, but when it is formed adjacent to the gate pad, The wiring from the gate pad to the overvoltage suppressing diode is shortened, which has the merit that the influence of parasitic capacitance and parasitic inductance generated in the wiring can be minimized.

(Embodiment 3) FIG. 11 is a sectional view showing a third embodiment according to the present invention. In FIG. 11, the same components as those in FIGS. 1 to 10 are designated by the same reference numerals. The feature of this embodiment is that by adjusting the repeating arrangement interval of the p-type n-type layers of the overvoltage suppressing diode, the overvoltage suppressing diode has a high electric field relaxation effect, and the FLR is eliminated to reduce the resistance of the built-in feedback diode. There is a reduction.

Since the current of the feedback diode flows through the path indicated by 400 in FIG. 4, the FLR layer 105 has a large resistance. It is necessary to remove the FLR layer 105 in order to reduce the resistance of the feedback diode, but it has been found that if this is removed, a sufficient breakdown voltage cannot be obtained. This is because the electric field relaxation effect of the overvoltage suppressing diode does not reach the inside of the drift layer, and electric field concentration occurs in the drift layer region deeper than several μm from the surface. This tendency becomes remarkable in a high breakdown voltage IGBT, that is, an IGBT having a large breakdown voltage holding region length.

In view of this, in this embodiment, the p-type n-type layer of the overvoltage suppressing diode is repeatedly arranged at an interval closer to the end of the chip to strengthen the electric field relaxing effect of the overvoltage suppressing diode. By narrowing the arrangement interval toward the outer peripheral portion of the chip, it becomes possible to mitigate the electric field concentration inside the drift layer, and it can be applied to a product having a higher breakdown voltage than the configuration of the second embodiment. However, in this embodiment,
Since the withstand voltage holding region width is increased as compared with the above configuration, the chip size is increased. Therefore, it is necessary to make a selection depending on whether reduction of the loss of the feedback diode is important or reduction of the chip size is important.

(Embodiment 4) FIG. 12 shows a fourth embodiment of the present invention. In FIG. 12, the same components as those in FIGS. 1 to 11 are designated by the same reference numerals. In FIG. 12, 1200 is a well layer. The feature of this embodiment is that the end of the well layer 1200 is located closer to the conduction region than the junction 1201 at the gate electrode side end of the overvoltage suppressing diode. When the well layer 1200 extends beyond the above junction to the outer periphery of the chip, electric field concentration occurs at the end of the well layer 1200, and the breakdown voltage of the device is lowered. This is shown in FIG.
Shown in In the case of the present invention, the electric field is relaxed as shown in FIG.

(Embodiment 5) FIG. 14 shows a sectional structure of a fifth embodiment according to the present invention. 14, the same components as those in FIGS. 1 to 13 are designated by the same reference numerals. The feature of this embodiment is that the distance L3 from the contact portion between the base layer 103 and the well layer 1200 at the end of the conduction region and the emitter electrode 111 to the end of the well layer 1200 on the breakdown voltage holding region side is 20 μm or more. Is. As described with reference to FIG. 7, element breakdown is likely to occur at the corners of the chip due to current concentration. In addition, other than the chip corner portion, the element is likely to be broken by the positive feedback in the portion where the current is likely to concentrate.

In this embodiment, L3 is set to 20 μm or more to increase the resistance in the well layer 1200 and suppress the positive feedback of the diode. More specifically, the resistance of the well layer 1200 increases as the temperature rises. Therefore, if the resistance of the well layer 1200 is increased, the increase in resistance accompanying the temperature rise also increases. This increase in resistance has the effect of suppressing an increase in current due to the positive feedback of the diode. Therefore, the larger the resistance of the well layer 1200, the more remarkable this effect is. In the case of a well layer of a general IGBT, the impurity concentration is about 1 × 10 ¹⁸ to 1 × 10 ²⁰ , and when this value is taken into consideration and the value of L3 is calculated, L3 ≧ 20.
μm. As a result, it is possible to prevent breakage at the corners of the chip and the portion where the current is concentrated.

(Sixth Embodiment) FIG. 15 is a plan view showing a sixth embodiment to which the present invention is applied. 17, the same components as those in FIGS. 1 to 14 are designated by the same reference numerals. In FIG. 15, the four corners of the chip are defined as corners A to D, the length of one side of the chip is L4, the current flowing through the cathode electrode 113 is I1, and the current flowing through the feedback diode is I2.

The feature of this embodiment is that the relationship between the cross-sectional area A of the cathode electrode 113 and L4 is 0.035 (V) ≧ V1 × 2 = ρ × (2 × L5 / A) × I1 / 2 (( It is a point that satisfies 2). In Expression (2), ρ is the resistivity of the electrode. In the case of IGBT with built-in feedback diode,
In many cases, the connection point between the cathode wiring 114 and the cathode electrode 113 is a corner of the chip. This is because the corner of the tip has a large area of the cathode electrode. Although it is desirable to connect the cathode wiring to each of the four corners, it is necessary to consider the case of one cathode wiring as shown in FIG. 15 due to package restrictions. In this case, at the corner B farthest from the corner C where the connection point of the cathode wiring is located, the electric potential becomes higher than the corner C due to the current I1. The voltage between the corner B and the corner C is small when the cathode wiring is connected to a plurality of corners, but is maximum when there is one wiring as shown in FIG. Therefore, hereinafter, the case of one cathode wiring will be examined. In FIG. 15, the potential of the corner B is higher than the potential of the corner C by V1 × 2. This potential difference causes a distribution in the current I2 of the feedback diode. This is because the corner B has a higher potential than the corner C, so that the voltage applied to the feedback diode becomes the smallest and the current hardly flows, and the corner C most easily flows the current. This potential difference is 5% of the forward voltage drop of the diode of 0.7V, that is, 0.03.
When it exceeds 5 V, the positive feedback due to the current concentration point becomes remarkable, and it causes destruction. Equation (2) is obtained by calculating the relationship between L5, I1, V1, and A at this time. 10A class IGBT
An example of calculation is shown for the case. 10A IGB
In case of T, the current of the feedback diode is also 10A, and I1
Is half this, so it becomes 5A. The chip size is generally about 1 cm × 1 cm, and L5 = 2 cm. Assuming that the cathode electrode is made of aluminum and the resistivity is 5 μΩ · cm, the cross-sectional area A =
It becomes 7.5 × 10 ^-3 cm ² .

The same can be considered when the cathode wiring is provided at each corner. This is shown in FIG. For example, when it is provided in four corners, I1 becomes 1/4 as shown in FIG.
Further, since the path L6 through which I1 flows is also ¼ of L5, the voltage generated in this case is 1/16, which is smaller than that in the case of one cathode wiring.

Therefore, if the formula (2) is satisfied when the number of cathode wirings is one, the condition of the formula (2) is satisfied even when the number of cathode wirings is two or more.

[0038]

According to the present invention, the width of the FLR forming region in the breakdown voltage holding region is set to 4/5 of the distance between the two junction ends of the overvoltage suppressing diode, so that the potential distribution mismatch is eliminated and the device breakdown voltage is reduced. Prevent the decrease of.

According to the present invention, the distance between the end of the well layer on the breakdown voltage holding region side and the contact between the emitter electrode and the contact is set to 20 μm or more, so that the current non-uniformity in the chip of the feedback diode, especially the chip It is possible to prevent damage due to current concentration at the corners.

Further, according to the present invention, the current concentration of the feedback diode is reduced by setting the relationship between the cross-sectional area of the cathode wiring and the chip size to be the relationship expressed by the equation (2),
A feedback diode with high breakdown strength can be realized.

According to these inventions, an IGBT having a built-in feedback diode having a high breakdown resistance can be realized, and a low-cost inverter system having a high breakdown resistance can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing a first embodiment according to the present invention.

FIG. 2 is a circuit diagram of a conventional inverter.

FIG. 3 is a circuit diagram of a conventional IGBT with a built-in overvoltage suppressing diode.

FIG. 4 is a cross-sectional view of a conventional IGBT with a built-in overvoltage suppressing diode.

FIG. 5 is a cross-sectional view of a conventional IGBT with a built-in feedback diode.

FIG. 6 is a cross-sectional view of a conventional IGBT having a built-in overvoltage suppressing diode and a feedback diode.

FIG. 7 is a cross-sectional view showing a potential distribution of a conventional overvoltage suppressing diode and FLR.

FIG. 8 is a sectional view showing a potential distribution of a conventional IGBT having a built-in overvoltage suppressing diode and a feedback diode.

FIG. 9 is a plan view illustrating a problem of a conventional feedback diode.

FIG. 10 is a plan view showing a first embodiment according to the present invention.

FIG. 11 is a sectional view showing a potential distribution according to the first embodiment of the present invention.

FIG. 12 is a supplementary explanatory diagram of the first embodiment according to the present invention.

FIG. 13 is a sectional view showing a second embodiment according to the present invention.

FIG. 14 is a plan view showing a third embodiment according to the present invention.

FIG. 15 is a supplementary explanatory diagram of the third embodiment according to the present invention.

FIG. 16 is a plan view showing a fourth embodiment according to the present invention.

[Explanation of symbols]

100 ... Collector layer, 101 ... Buffer layer, 102 ... Drift layer, 103 ... Base layer, 104 ... Source layer, 10
5 ... FLR layer, 106 ... Cathode layer, 110 ... Gate electrode, 111 ... Emitter electrode, 112 ... Overvoltage suppressing diode gate side electrode, 113 ... Overvoltage suppressing diode collector side electrode, 114 ... Cathode wiring, 115 ... Collector electrode, 120 ... Interlayer insulating film, 121 ... Oxide film, 130 ...
Overvoltage suppression diode, 200, 300 ... IGBT, 2
01 ... Feedback diode, 210, 211 ... DC terminal, 2
12, 213, 214 ... AC terminal, 301 ... Gate-emitter resistance, 400 ... Feedback diode current path, 40
1 ... Feedback diode symbol, 500 ... Equipotential line by overvoltage suppressing diode, 501 ... Equipotential line by FLR, 7
00 ... Current line of feedback diode, 900 ... Gate pad, 901 ... Emitter pad, 902 ... Gate wiring, 1
000 ... Overvoltage suppressing diode adjacent to the gate pad, 1200 ... Well layer.

Claims (5)

[Claims] 1. A first layer of a first conductivity type having a pair of main surfaces, which is in contact with one of the main surfaces, and a second layer of a second conductivity type, which is adjacent to the first layer and the other main surface. Second layer, a semiconductor substrate including a first electrode formed on one main surface, and a first conductivity type first selectively formed in the second layer adjacent to the other main surface. 3 layer, a fourth layer of the second conductivity type selectively formed in the third layer adjacent to the other main surface, and an insulating portion on the exposed portion of the other main surface of the third layer An IGBT region in which an IGBT composed of a second electrode formed through a film and a third electrode formed in contact with the third layer and the fourth layer is repeatedly arranged, and surrounding the IGBT region. Then, a plurality of fifth layers of the first conductivity type selectively formed adjacent to the other main surface in the second layer, and the other main surface in the second layer. The above A sixth layer of the second conductivity type selectively formed adjacent to the end face of the semiconductor substrate, and a fourth layer formed in contact with the sixth layer and electrically connected to the first electrode. Electrode, an oxide film formed on the other main surface excluding the sixth layer, one end connected to the second electrode and the other end connected to the fourth electrode, and between the two ends. In a semiconductor element that is composed of a plurality of layers of the first conductivity type and a second conductivity type that are repeatedly arranged and that has a breakdown voltage holding region having a polycrystalline silicon diode formed on the oxide film, the semiconductor device is closest to the IGBT region. From the fifth layer, the most IGB
The distance L1 from the T region to the fifth layer is 4/5 of the distance L2 from the junction closest to the IGBT region of the polycrystalline silicon diode to the junction farthest from the IGBT.
A semiconductor device characterized by the following. 2. A first conductive type first layer having a pair of main surfaces and being in contact with one main surface, and a second conductive type first layer adjacent to the first layer and the other main surface. Second layer, a semiconductor substrate including a first electrode formed on one main surface, and a first conductivity type first selectively formed in the second layer adjacent to the other main surface. 3 layer, a fourth layer of the second conductivity type selectively formed in the third layer adjacent to the other main surface, and an insulating portion on the exposed portion of the other main surface of the third layer An IGBT region in which an IGBT composed of a second electrode formed through a film and a third electrode formed in contact with the third layer and the fourth layer is repeatedly arranged, and surrounding the IGBT region. Then, a fifth layer of the second conductivity type selectively formed in the second layer adjacent to the other main surface and the end surface of the semiconductor substrate, and in contact with the fifth layer. A fourth electrode formed and electrically connected to the first electrode, an oxide film formed on the other main surface except the fifth layer, and one end portion of the second electrode
The other end of the electrode is connected to the fourth electrode, and is composed of a plurality of first-conductivity-type and second-conductivity-type layers repeatedly arranged between both ends, and is formed on the oxide film. In a semiconductor element comprising a breakdown voltage holding region having a silicon diode, the interval between the first conductive type and the second conductive type repeating arrangement of the polycrystalline silicon diode is wide on the second electrode side and on the fourth electrode side. The semiconductor device is characterized by narrowing. 3. A seventh layer of the first conductivity type, which is in contact with a fourth layer located at an end of the IGBT region and is selectively formed adjacent to the other main surface, The seventh layer is the IGBT of the polycrystalline silicon diode.
3. The semiconductor device according to claim 1, wherein the semiconductor device is formed on the IGBT region side with respect to the junction closest to the region side end portion. 4. The third portion located at the end of the IGBT region.
4. The semiconductor device according to claim 1, wherein the distance L3 from the contact position between the electrode of FIG. 4 and the fourth layer to the end of the seventh layer on the breakdown voltage holding region side is 20 μm or more. 5. At least one connected to the fourth electrode.
1 or more first wirings, and any one of the first wirings
There is a first point on the fourth electrode farthest from the book, a distance L4 between the first point and any one of the first wirings, a cross-sectional area A of the fourth electrode, The current I flowing through the fourth electrode and the resistivity ρ of the fourth electrode satisfy 0.035 ≧ ρ × (L4 / A) × I / 2. Semiconductor device.