JPH0918011A - Thin film semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [Object] To provide a thin-film semiconductor device and a method for manufacturing the same, which are configured by transistors of the same conductivity type and can reduce the cost with a small number of steps. [Structure] A liquid crystal display panel 42 is provided on a glass substrate 46.
The drain driver 44 and the gate driver 45 of the liquid crystal drive circuit are integrally formed. The thin film transistors forming the drain driver 44 and the gate driver 45 and the thin film transistor of the switching element provided in each pixel of the liquid crystal display panel are all of the same conductivity type PMO.
It is composed of S transistors. Therefore, 1
Since the drive circuit and the display portion can be simultaneously formed on one glass substrate 46, and the transistors of the same conductivity type may be formed, the number of times of ion doping can be reduced, so that the manufacturing cost can be kept low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device and a manufacturing method thereof, and more particularly to a thin film semiconductor device composed of thin film transistors of the same conductivity type and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a driver circuit of a liquid crystal display device is provided with a thin film transistor (TFT).
In the case of (1), a CMOS circuit is usually used. In addition, as the driver circuit using the CMOS circuit, there are a print head such as a thermal printer or a driver circuit of a photo sensor, in addition to the driver circuit of the liquid crystal display device. This CMOS circuit is widely used because of its advantages such as low power consumption and proper output.

For example, FIG. 14 is a diagram showing a configuration of a CMOS inverter circuit. As shown in FIG. 14, the CMO
S1 uses two types of transistors, PMOS2 and NMOS3, as a pair. In this CMOS1, when the IN (input) is "0", the NMOS3 turns off and the PMOS
2 is turned on and “1” is output (output) from the power supply Vdd. When the input is "1", the PMOS2 is turned off and the NMOS3 is turned on, so that "0" is input from the ground.
Is output. In this way, the CMOS inverter circuit outputs the logic opposite to the input logic.

In the above-mentioned conventional example, an example in which an inverter circuit is constructed by using CMOS has been shown, but in addition to this, a driver circuit using a latch circuit, an AND circuit, a NAND circuit, a tri-state circuit or the like is constructed. CMOS is used also when doing.

[0005]

However, in such a conventional thin film semiconductor device, C shown in FIG. 14 is used.
Since MOS1 is composed of two types of transistors, PMOS2 and NMOS3, it is necessary to fabricate both PMOS and NMOS when manufacturing a CMOS, which complicates the device structure and increases the impurity implantation process and the number of masks. Therefore, there is a problem that the cost is increased.

Therefore, the present invention has been made in view of the above problems, and by using transistors of the same conductivity type such as PMOS or NMOS, it is possible to reduce the cost with a small number of manufacturing steps. An object of the present invention is to provide a possible thin film semiconductor device and a manufacturing method thereof.

[0007]

According to another aspect of the present invention, there is provided a thin film semiconductor device, wherein all thin film transistors included in a thin film transistor circuit formed on one substrate are transistors of the same conductivity type. And a driver circuit including a plurality of the latch circuits is formed.

Therefore, a thin film transistor circuit including a plurality of latch circuits using thin film transistors and a driver circuit using a plurality of the latch circuits is composed of only n-type or p-type conductive type thin film transistors. Therefore, the number of times of ion doping for implanting impurities and the number of masks are significantly reduced, and the manufacturing cost can be reduced.

The thin film semiconductor device according to claim 1 is
For example, as described in claim 2, a driver circuit may be configured by further forming a shift register including a plurality of the latch circuits.

Further, the thin film semiconductor device according to claim 1 or 2 is, for example, as described in claim 3,
A thin film semiconductor device comprising a liquid crystal display device integrated with a driving circuit in which a switching element for each pixel and a liquid crystal driving circuit are integrally formed on a substrate of a liquid crystal display panel by the thin film transistor, and at least the switching for each pixel is performed. The element may be configured by connecting the sources / drains of a plurality of thin film transistors in series, and the gate electrodes of the plurality of thin film transistors may be connected to the same gate line.

Further, the thin film semiconductor device according to claim 1 or 2 is, for example, as described in claim 4,
A thin film semiconductor device comprising a liquid crystal display device integrated with a driving circuit in which a switching element for each pixel and a liquid crystal driving circuit are integrally formed on a substrate of a liquid crystal display panel by the thin film transistor, and at least the switching for each pixel is performed. A low-concentration impurity diffusion layer may be formed in the source region and the drain region that are inscribed at both ends of the channel region of the thin film transistor forming the element, and high-concentration impurity diffusion layers may be formed on both outer sides thereof.

The thin film semiconductor device according to claim 3 or 4 is, for example, as described in claim 5,
Polysilicon may be used for at least the semiconductor layer of the thin film transistor of the switching element.

According to a sixth aspect of the present invention, there is provided a thin film semiconductor device manufacturing method, in which only a plurality of thin film transistors of the same conductivity type are formed on one substrate, and the plurality of thin film transistors are wired to form a thin film transistor circuit including a latch circuit. It is characterized by

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 13 are views showing an embodiment of a thin film semiconductor device and a manufacturing method thereof according to the present invention. Here, a thin film transistor (TFT: TFT) is provided for each pixel of a liquid crystal drive circuit and a pixel portion on a glass substrate. Thin Film Tran
This is implemented as a drive circuit integrated liquid crystal display device by integrally forming a switching element composed of a sistor). In the present embodiment, the liquid crystal drive circuit and the switching element for each pixel have the same conductivity type TFT (PMO).
S transistor) is used.

(Process for Manufacturing Thin Film Transistor) FIGS. 1 and 2 are views showing a process for manufacturing a thin film transistor of the same conductivity type according to the present embodiment, in which at least a thin film transistor in a pixel portion is provided with a plurality of gates. The structure is adopted.

The feature of the present invention is that by forming a driver circuit including a latch circuit using thin film transistors of the same conductivity type, the number of impurity implantation steps is reduced as compared with the case of manufacturing a conventional CMOS, and the impurity implantation is performed. Since the number of masks required for the process is reduced, the cost can be reduced. In particular, the thin film transistor formed in FIGS. 1 and 2 has a multi-gate structure in the thin film transistor in the pixel portion of the liquid crystal display device.
The S / D (source / drain) withstand voltage is improved to reduce the leak current.

First, as shown in FIG. 1A, after cleaning the glass substrate 10, a silicon oxide film is formed as the underlying transparent insulating film 11 by using a sputtering apparatus to a thickness of about 1000 Å. The base insulating film is not limited to the above-described silicon oxide film, and other films can be used. Then, the base insulating film 1 made of a silicon oxide film
Further, an amorphous silicon film 12 is formed on the substrate 1 by using a plasma CVD apparatus to a thickness of about 500 Å. The method for forming the amorphous silicon film 12 is not limited to this, and other methods can be used.

Next, the amorphous silicon film 12 shown in FIG. 1A is subjected to dehydrogenation treatment in a nitrogen atmosphere at 450 ° C. for about 2 hours. This dehydrogenation treatment step can be omitted. Then, as shown in FIG. 1 (b), an amorphous silicon film 12 is irradiated with laser twice in vacuum at an energy density of about 350 mJ / cm ² by using an excimer laser device, laser annealing is performed, and laser annealing is performed to form poly. Forming polysilicon 12 '. The laser device described above,
The laser irradiation conditions and the poly-izing method (laser annealing method) are not limited to these, and for example, poly-izing may be performed using a solid phase growth method.

Next, as shown in FIG. 1C, a photoresist (PR) is applied on the polysilicon film 12 ', and UV exposure is performed through a mask having a predetermined pattern to form a photoresist mask. 13 is formed. And
Using an ion doping apparatus (not shown), the flow rate ratio of B ₂ H ₆ diluted with 1% hydrogen and hydrogen gas was 5/45 (cc).
m), and 2 × 10 ¹⁵ (ions / c) through the photoresist mask 13 at an acceleration energy of 10 KeV.
Implant impurities of about m ² ). Further, the apparatus, conditions, or implantation method used in the above-described impurity implantation step are not limited to this, and ones other than the above may be adopted.

Next, as shown in FIG. 1D, after selectively implanting boron into the polysilicon film 12 'which is a semiconductor layer, laser annealing is performed to activate the impurity atoms. The P region having a large proportion of is selectively formed. In addition, the region where impurities are not implanted is
The i-region remains as an intrinsic semiconductor, and a channel of a MOS transistor described later is formed.

Then, as shown in FIG. 1E, the polysilicon film 1 which has been activated by selectively implanting impurities is activated.
By selectively etching 2 ', element isolation for forming a source region, a channel region, and a drain region for each MOS transistor is performed. In the element region 13A shown in FIG. 1E, two intrinsic semiconductor regions (i regions) each serving as a channel region are formed between three P regions, and the pixel region of the dual gate structure is formed. It is configured to form a TFT. Further, in the element regions 13B and 13C, the sources and drains of two PMOS transistors are connected in series to form, for example, an inverter circuit in a driver circuit.

Then, as shown in FIG. 2A, a silicon oxide film 14 and a silicon nitride film 15 are formed on the semiconductor layer in which the elements have been separated into respective predetermined film thicknesses,
A gate insulating film is formed.

Next, as shown in FIG. 2B, a metal chromium film 16 is further formed on the silicon nitride film 14 to a predetermined thickness, and this is selectively etched to form a gate electrode or the like. To form. Then, as shown in FIG.
The indium oxide film (ITO: Indi) that forms the pixel electrodes 17 of the pixel portion arranged in a matrix on the liquid crystal display panel.
um Tin Oxide) is patterned and formed with a predetermined film thickness.

Then, as shown in FIG.
A silicon nitride film 18 serving as an interlayer insulating film is formed on the entire surface including the pixel electrode 17 made of TO. Then, FIG.
In (e), a contact hole for making contact with the source region and the drain region of each PMOS transistor is formed by performing selective etching through the interlayer insulating film and the gate insulating film. Then, after forming an aluminum (Al) film in the contact hole and on the surface, it is patterned into a predetermined shape to form an S / D (source / drain) electrode 19.

As described above, on the glass substrate of the liquid crystal display device of the present embodiment, the liquid crystal drive circuit composed of the same conductivity type PMOS transistor and the switching element for each pixel are integrally formed. Therefore, the number of times of ion doping is smaller than that of a conventional liquid crystal drive circuit using a CMOS transistor, and the number of masks for ion doping is small, so that the manufacturing cost can be reduced.

Further, the TF of the pixel portion shown in FIGS.
As shown in FIG. 2 (e), the switching element of T has the source and drain of two PMOS transistors connected in series in the element region 13A, and the gate electrodes 16 and 16 of the two PMOS transistors have a common gate. Since we adopted a dual gate structure that connects to the line,
The S / D (source / drain) withstand voltage is improved, and the leak current can be reduced.

Further, the TF formed in FIG. 1 and FIG.
Since the semiconductor layer of T is composed of polysilicon obtained by converting amorphous silicon into poly, the aperture ratio can be improved and the gate applied voltage can be reduced particularly in the pixel portion, so that the power consumption can be reduced. Become.

FIG. 3 is a diagram for explaining an ion doping process in the case of forming a thin film transistor of the same conductivity type according to this embodiment with an LDD structure. In FIG. 3, in place of the dual gate structure described in FIGS. 1 and 2, the element region 21 portion of the TFT forming the switching element of the pixel portion is replaced with a source region and a drain region which are inscribed at both ends of the channel region 24. Concentration impurity diffusion layers 25 and 26 are formed, and high concentration impurity diffusion layers 27 and 2 are formed on the outer portions of both of them.
8 is formed, that is, when a so-called LDD structure is formed.

The manufacturing process at the front stage of FIG.
Corresponding to FIGS. 1A and 1B, after polycrystallizing the amorphous silicon film 12, between the polysilicon film 12 ′ and the photoresist 30 applied thereon, oxidation of, for example, about 200 angstrom is performed. Silicon film 29
Is provided, and this is selectively etched into the shape shown in FIG.

As shown in FIG. 3, a silicon oxide film 29 'is formed.
Since the width of the photoresist 30 'is smaller than the width of the mask, two types of masks having different ion implantation concentrations can be formed. Then, by implanting impurities with energy of 20 KeV in the state of FIG. 3, an intrinsic semiconductor is formed in which no impurities are implanted in the thick mask portion (channel region 24), and a P-minus region in which a low concentration of impurities is implanted in the thin mask portion. 25 and 26, P-plus regions 27 and 28 into which high-concentration impurities are implanted are formed in the maskless portion, and the LDD structure can be formed by one ion doping step. Manufacturing conditions other than the above may be the same as those in FIGS.

As described above, when the LDD structure is adopted for the TFT of the pixel portion shown in FIG. 3, there is an advantage that the leak current can be reduced without increasing the number of times of ion doping.

(Liquid Crystal Driving Circuit Using Thin Film Transistor) FIG. 4 shows a driving circuit integrated TFT according to the present embodiment.
FIG. 3 is a schematic configuration diagram of LCD 41. This drive circuit integrated TFT-LCD 41 is a liquid crystal display panel (TFT-LC).
D: Thin Film Transistor-Liquid Crystal Display)
As the switching element of each pixel of 42, the TFT 43 of the dual gate structure formed in FIG. 2 is formed, and the liquid crystal drive circuit including the drain driver 44 and the gate driver 45 is integrally formed on the glass substrate 46.

As shown in FIG. 4, a driving circuit integrated TFT
-LCD 41 is a liquid crystal display panel 4 on a glass substrate 46.
A plurality of TFTs 43 are formed for each pixel 2 and a scanning signal is applied to the gate line 47 of each TFT 43 of the liquid crystal display panel 42 to create a selected state and a non-selected state by the gate driver 45, and the gate driver 45. The drain driver 4 is connected to the TFT 43 selected by
A display signal is applied from 4 through the drain line 48 to drive the liquid crystal of each pixel.

(Drain Driver) FIG. 5 is a diagram showing a circuit configuration example of a part of the drain driver 44 of FIG.
The drain driver 44 shown in FIG.
0, and latch circuits 51, 52, 53, ... And and NAND circuits 61, 62 ,.
2 ..., latch circuits 81, 82, ..., Tri-state circuits 91, 92.

In the latch circuits 51, 52 and 53 constituting the shift register 50, a horizontal synchronizing signal (XSCL) input from a controller (not shown) and an inverted horizontal synchronizing signal (_XSCL) are input to the control signal input terminal ( L) and the inverted control signal input end (-L) are alternately input in opposite phases. When "1" enters the control signal input end (L), the input signal is output through, When "0" is entered, the previous input signal is latched.

As the input signal to the latch circuit 51, an XD clock and an inverted XD clock (_XD) are input, and an output signal corresponding to the through state and the latch state is output terminal (O).
Is output from the inverted output end (−O), and is input to the input end of the AND / NAND circuit 61 and the latch circuit 52 of the next stage.

Similarly, the output signal of the latch circuit 52 is the AND / NAND circuits 61 and 62 and the latch circuit 5 of the next stage.
3 is input to the input end. Then, the AND / NAND circuit 61 receives the output (OUT) of the latch circuit 51 and the inverted output (-OUT) of the latch circuit 52, and outputs the logical product and its negation to the control signal input terminal of the latch circuit 71. It is input to the section (L) and the inversion control signal input end (-L). Similarly, the AND / NAND circuit 62 also has a latch circuit 52.
Inverted output (--OUT) and output of latch circuit 53 (OU
T) is input, and the logical product and its negation are input to the control signal input end (L) and the inverted control signal input end (-L) of the latch circuit 72.

The latch circuits 71 and 72 latch the data for each pixel input from a data conversion circuit (not shown) in accordance with the timing of the output signals from the AND / NAND circuits 61 and 62, and The latched data is output to the latch circuits 81 and 82 at the next stage, respectively. The latch circuits 81 and 82 latch the data for each pixel input at the timing of the clock OP and output the outputs to the respective tri-state circuits 91 and 92.

The tri-state circuits 91 and 92 appropriately select three kinds of power source voltages of VH, VC and VL depending on the combination of the input signals from the latch circuits 81 and 82 and the AC signal WF. As a result, an alternating display signal is generated. Tri-state circuit 91
The AC-converted display signal output from the drain line D1 is output to the drain line D1, and the AC-displayed signal output from the tri-state circuit 92 is output to the drain line D2.
Is output to

In FIG. 5, only a part of the structure of the drain driver 44 for supplying the drain lines for two lines is described, and in practice, the above circuits are connected in the horizontal scanning direction according to the number of pixels. Are arranged. This allows
A display signal according to the pixel position can be supplied to each drain line.

As described above, the drain driver 44 composed of the shift register, the latch circuit, the AND / nand circuit and the tri-state circuit has the same conductivity type MO.
It can be configured using an S-transistor (here, PMOS) and a capacitor, etc., and the transistor structure is simpler, the number of times of ion doping is reduced, and the liquid crystal is compared with the conventional example configured by a CMOS transistor. If the drive circuit and the TFT used for the switching element of the pixel are of the same conductivity type, a TFT-LCD integrated with the drive circuit can be simultaneously formed on the glass substrate 46, which is an advantage of further cost reduction. There is.

The drain driver 4 of this embodiment is also used.
The TFT used for No. 4 has the dual gate structure or the LDD structure as described in FIGS. 1 to 3, so that the leak current is reduced and the power consumption is low. Furthermore, "pass transistor logic" and "bootstrap method", which will be described later, are added to the liquid crystal drive circuit logic circuit.
By adopting, the appropriate output level can be obtained and the power consumption can be reduced.

(Latch Circuit) FIG. 6 is a diagram showing one circuit configuration example of the latch circuit 51 which constitutes the drain driver 44 of FIG. First, the configuration will be described. The basic circuit configuration of the latch circuit 51 shown in FIG. 6 includes two-input type inverter circuits 101 and 102.

That is, the inverter circuit 101 is
Two PMOS transistors Q16 and Q1 from the power supply Vdd
The source / drain of 7 is connected in series and grounded to the ground, and the logic input from the input end (I) is PMOS.
The inversion logic input to the gate electrode of the transistor Q16 and from the inverting input end (_I) is input to the PMO via the channel of the PMOS transistor Q15 whose gate is grounded.
It is input to the gate electrode of the S transistor Q17. One end of the capacitor C11 is connected to the connecting portion of the PMOS transistors Q16 and Q17, the other end is connected to the gate electrode of the PMOS transistor Q17, and the connecting portion of the PMOS transistors Q16 and Q17 is an inverting output end portion. It is connected to (O) and outputs the inverted logic of the logic input from the input end (I).

Further, the inverter circuit 102 is constructed similarly to the above-mentioned inverter circuit 101, but the gates of the PMOS transistors Q19 and Q20 are provided for the input end (I) and the inverting input end (-I). Are connected in reverse. Then, the input end (I) and the inverting input end (
The input data input from I) is controlled by switching the PMOS transistors Q11 and Q12 by the inverted clock signal (_clk) from the inverted control signal input end (_L).

The output data of the inverter circuit 101 and the inverter circuit 102 are PMOSed by the clock signal (clk) input from the control signal input terminal (L).
Data feedback is controlled by switching the transistors Q13 and Q14.

That is, the output of the inverter circuit 101 is output to P via the channel of the PMOS transistor Q14.
The output of the inverter circuit 102 is connected to the drain side of the MOS transistor Q12 to form a feedback loop, and the output of the inverter circuit 102 is connected to the drain side of the PMOS transistor Q11 via the channel of the PMOS transistor Q13 to form a feedback loop.

In the latch circuit 51 constructed as shown in FIG. 6, the inversion control signal input end portion (--L) from the outside.
The control signal from the control signal input terminal (L) is used to switch between the through operation and the latch operation of the latch circuit 51.

As described above, the latch circuits 51 to 53 constituting the inverter circuit 50 of FIG. 5 and the other latch circuits 71, 72, 81 and 82 are configured similarly to the latch circuit of FIG. Therefore, since the circuit which has been conventionally composed of CMOS can be composed of PMOS transistors of the same conductivity type, the number of times of ion doping is reduced,
Since the number of masks is reduced, the manufacturing cost can be reduced.

Next, the operation will be described. In the latch circuit 51 shown in FIG. 6, the clock signal (clk) input to the control signal input end (L) is high “1”, and the inverted clock signal (_clk) at the inverted control signal input end (_L). ) Is low “0”, the clock signal (clk) input to the control signal input end (L) is low “0” and the inverted control signal input end (−L). When the inverted clock signal (_clk) of)) is high “1”, the latch state is set.

The above-mentioned through state means the input end (I).
The input signal (IN) from is output as it is as the output signal (OUT) of the output end (O), and the inverting input end (
Inverted input signal (-IN) from I) is output as it is as the inverted output signal (-OUT) of the inverted output end (-O). Further, the above-mentioned latched state means holding the output state before latching.

Specifically, when the clock signal (clk) is high "1" and the inverted clock signal (_clk) is low "0", the through state is established and the PMOS transistors Q13 and Q14 in FIG. 6 are turned off. Then, the PMOS transistors Q11 and Q12 are turned on. Therefore, the input signal (IN) is "0" and the inverted input signal (-IN) is "1".
Then, the PMOS transistors Q17 and Q19 are turned off, and the PMOS transistors Q16 and Q20 are turned on. Therefore, the output state (0) is output as it is and the inverted output signal (-OUT) is displayed as "0". 1 ”is output.

Next, the clock signal (clk) is low "0" and the inverted clock signal (-clk) is high "1".
In the case of, the PMOS transistor Q13 and Q14 of FIG.
11 and Q12 are turned off. Therefore, regardless of the input signals at the input end (I) and the inverting input end (-I), the "0" of the output signal (OUT) in the previous through state is transmitted through the PMOS transistor Q13 and the PMOS transistor Q1.
6 and Q20 are turned on, and "1" of the inverted output signal (_OUT) is transferred to the PMO via the PMOS transistor Q14.
Since the S transistors Q17 and Q19 are turned off, the previous output state is maintained, and the output signal (IN) is "0" and the inverted input signal (-IN) "1" is output as it is.

As described above, the latch circuit shown in FIG.
The gates of the individual PMOS transistors Q11 to Q14 are switched between the through operation and the latch operation according to a control signal from the outside.

The latch circuit of FIG. 6 includes inverter circuits 101 and 102, and capacitors C11 and C12 and PMOS transistors Q15 and Q18 are formed in the inverter circuit to form the PMOS transistor Q.
Since the "bootstrap method" is adopted in which the gate capacitance on the side of 17 or Q20 is increased to perform reliable switching, loss of output level is eliminated, and direct current leakage current is eliminated, so that power consumption can be reduced. In the latch circuit 51, the circuit is configured by the PMOS transistor, but the present invention is not limited to this, and the entire TFT on the substrate may be configured by the NMOS transistor.

(AND-NAND Circuit) FIG. 7 shows an AND-NAND circuit 61 which constitutes the drain driver 44 of FIG.
8 is a diagram showing one circuit configuration example, and FIG. 8 is a diagram showing symbols of the AND / NAND circuit 61 of FIG. 7. First, the configuration will be described. The four PMOS transistors Q21 to Q24 shown in FIG. 7 use a pass transistor logic to generate a logical product of inputs and its negation. That is, when there are two inputs a and b, the inversion a (-a) and the inversion b (-b) which are the negations thereof are also input. The PMOS is connected between the input end of a and the ground.
The transistors Q21 and Q22 are connected in series, and PM is connected between the input terminal of the inversion a and the power supply (Vdd).
The OS transistors Q23 and Q24 are connected in series.

In addition, PMOS transistors Q22 and Q2
B is input to the gate of 4 to perform switching, and inversion b is input to the gates of the PMOS transistors Q21 and Q23 to perform switching. Then, according to the result of the switching, a high level "1" or a low level "0" signal is output between the PMOS transistors Q21 and Q22 and between the PMOS transistors Q23 and Q24.

However, the above-mentioned PMOS transistor Q2
With only 1 to Q24, the low level output is lost by the threshold voltage of the transistor. Therefore, in the AND / NAND circuit 61 of the present embodiment, the output level is corrected by adding the inverter circuits 111 and 112 having the same configuration as the inverter circuit described in FIG. That is, here, it has a function of lowering the low level output through the PMOS transistors Q27 and Q30 until the potential becomes equal to the ground level. FIG. 8 shows the correspondence between the symbols of the AND / NAND circuit 61 of FIG. 7 and the input / output signals at each end.

Next, the operation will be described. When the input a is "0" (inversion a is "1") and b is "0" (inversion b is "1"), the PMOS transistors Q21 and Q
Since 23 is turned off and Q22 and Q24 are turned on, the PMOS transistors Q26 and Q30 on the inverter circuit side are turned off, but the PMOS transistors Q27 and Q29 are turned on and the AND output is "0" and the NAND output is "1". Becomes

Similarly to the above, when the input a is "0" (inversion a is "1") and b is "1" (inversion b is "0"), the AND output is "0", The NAND output becomes "1".

If the input a is "1" (inversion a is "0") and b is "0" (inversion b is "1"),
The AND output is "0" and the NAND output is "1". Further, when the input a is “1” (inversion a is “0”) and b is “1” (inversion b is “0”), the AND output is “1” and the NAND output is “0”. Becomes

As described above, the AND / NAND circuit 61 shown in FIG. 7 has a predetermined logical product (AND) and its negation depending on the combination of the input a, the inversion a, the input b, and the inversion b. (NAND) is output. When the low level is output by the AND output and the NAND output, the output level can be corrected by combining the inverter circuits 111 and 112 as in the present embodiment, so that the ground level (0V) is surely obtained. Equivalent potential can be output.

Further, the AND / NAND circuit 61 described above.
Since the inverter circuits 111 and 112 adopting the "bootstrap method" are adopted, the DC leakage current is eliminated and the power consumption can be reduced. In the AND-NAND circuit 61, the circuit is formed by using the PMOS transistor.
The entire circuit may be configured by NMOS transistors.

(Tri-State Circuit) FIG. 9 shows a tri-state circuit 91 which constitutes the drain driver 44 of FIG.
10 is a diagram showing one circuit configuration example, and FIG. 10 is a diagram showing symbols of the tri-state circuit of FIG. 9. The tri-state circuit 91 is used, for example, when an alternating drive voltage is generated because the liquid crystal deteriorates when a direct current voltage is applied to the liquid crystal when the liquid crystal drive device drives the liquid crystal.

First, the structure will be described. As shown in FIG. 9, the eight PMOS transistors Q21 to Q28 are
A logic generation unit 12 that generates a predetermined logic based on four input signals of a, inversion a (-a), b, and inversion b (-b).
Make up one. In this tri-state circuit 91,
By inputting the positive logic / negative logic to each of a and b, an alternating voltage generated by switching the three kinds of power source voltages VH, VC, and VL is output from the output c (however, VH
>VC> VL). Here, the pass transistor logic method is used similarly to the AND-NAND circuit 61 described above.

When this tri-state circuit is used in a liquid crystal driving device, for example, a of the input signal represents presence / absence of write data, that is, liquid crystal is driven or not, and b is liquid crystal driven. It can be used to represent the positive / negative of voltage.

Next, six PMOS transistors Q39
To Q44 and capacitors C31 and C3 form the two inverter circuits described in FIG. 6, and capacitors C33 and C34 are further added here. In this way, the inverter circuits 122 and 123 are connected to the power source voltage VH.
, VL are switched and output, so that the voltage level of the gate signal applied to the gates of the PMOS transistors Q45 and Q46 is optimized. Therefore, each transistor can be sufficiently driven to perform on / off control, and the output voltage value can be optimized. Further, the PMOS transistors Q45, Q46, Q47 are
It is a switching transistor for switching and outputting the power supply voltages VH, VL and VC.

Next, the operation will be described. In the tri-state circuit 91 shown in FIG. 9, by inputting either positive logic or negative logic to a and b, respectively, c to VH,
Either VC or VL is output. In fact, the input a,
A desired AC signal can be generated by changing b.

First, when the input signals a and b are "0", the PMOS transistors Q45 and Q46 are turned off and the PMOS transistor Q47 is turned on, so that the voltage Vc is output from c. In addition, when a of the input signal is “0”,
Even when b is "1", Vc is output from c similarly to the above. This is because when a is "0", the PMOS transistors Q31, Q33, Q35, Q37 in the logic section are turned off, so that the PMOS transistor Q47 is turned on without being influenced by the input signal of b, and This is because Vc is output.

When the input signal a is "1", the switching transistor Q47 is turned off, and the logic section P47 is turned off.
The MOS transistors Q32, Q34, Q36, and Q38 are turned off, and conversely, the PMOS transistor Q3 is turned on.
1, Q33, Q35 and Q37 are turned on. Therefore, b
The output voltage from c changes based on the input signal of.

Therefore, when b is "0", the PMOS transistor Q46 turns on and Q45 turns off, so that VL is output from c. If b is “1”, PM
Since the OS transistor Q45 is turned on and Q46 is turned off, VH is output from c.

The capacitor C34 holds the charge accumulated in the gate of the PMOS transistor 46 and acts so that the potential of the gate becomes equal to or higher than the power supply voltage by capacitive coupling. Therefore, the PMOS transistor Q46 can be surely turned off.

On the contrary, when the positive logic is applied to the gate of the PMOS transistor Q44, the PMOS transistor Q4
When the negative logic is applied to the gate of 3, the PMOS transistor Q43 is turned on, and the ground voltage (0V) is applied from the ground to the gate of the PMOS transistor Q46. At this time, the capacitor C34 charges the charge accumulated in the gate of the PMOS transistor 46 to the PMOS.
Releasing all at once through the transistor Q34 acts to sufficiently lower the gate potential of the PMOS transistor Q46. Therefore, the PMOS transistor Q46 can be turned on.

As described above, the tri-state circuit 91 of the present embodiment can be composed of only the PMOS transistor and the capacitor, so that the structure is simple and can be manufactured in a small number of steps, so that the cost can be reduced. Although the tri-state circuits 71 and 81 are configured by using PMOS transistors, they may be configured by using NMOS transistors.

(Gate Driver) FIG. 11 is a diagram showing a circuit configuration example of a part of the gate driver 45 of FIG. The gate driver 45 shown in FIG. 11 includes a latch circuit 131,
132, 133 ... And-and-nand circuits 141, 14
2 ..., Inverter circuits 151, 152 ...

The latch circuits 131, 132, 133 are provided with vertical synchronizing signals (Y
SCL) and the inverted vertical synchronizing signal (-YSCL) are input to the control signal input end (L) and the inverted control signal input end (-L) in alternate phases, and the control signal input end When "1" enters the part (L), the input signal is output through,
When "0" is entered, the previous input signal is latched.

As the input signal to the latch circuit 131, the YD clock and the inverted YD clock are input, and the output signal corresponding to the through state and the latch state is output from the output end (O) and the inverted output end (-O). Is output, and the NAND circuit 14
1 and the input terminal of the latch circuit 132 at the next stage.
Similarly, the output signal of the latch circuit 132 is input to the input terminals of the AND / NAND circuits 141 and 142 and the latch circuit 133 at the next stage.

The AND / NAND circuit 141 outputs the output (OUT) of the latch circuit 131 and the latch circuit 13 to each other.
The inverted output (-OUT) of 2 is input, and the logical product and the negation thereof are input to the input end (IN) and the inverted input end (-IN) of the inverter circuit 151. Then, from the output end of the inverter circuit 151, the scan signal which is negated in the logic input from the input end (IN) is supplied to the gate line G.
It is output to 1. Further, from the output end of the inverter circuit 152, a scan signal which is negated in the logic input from the input end (IN) is output to the gate line G2.

FIG. 11 only illustrates a part of the configuration of the gate driver 45 which supplies the gate lines for two lines, and the above-mentioned circuits are arranged according to the number of lines arranged in the vertical direction. There is. Thereby, by line scanning each gate line by a predetermined scanning method,
Each gate line is brought into a selected state or a non-selected state.

As described above, the gate driver 45 composed of the latch circuit, the AND circuit and the inverter circuit.
Can be configured by using PMOS transistors of the same conductivity type as in the case of the drain driver 44 described above, so that the number of times of ion doping is reduced and the number of masks is also reduced as compared with the case of using CMOS transistors. Therefore, the cost can be reduced.

(Inverter Circuit) FIG. 12 is a diagram showing a circuit configuration example of the inverter circuit 151 constituting the gate driver 45 of FIG. 11, and FIG. 13 is a diagram showing symbols of the inverter circuit 151 of FIG. is there. First, the configuration will be described. As shown in FIG. 12, the inverter circuit 15
1 is an inverter circuit 161 composed of PMOS transistors Q1, Q2, Q3 and a capacitor C1, and PM
This is a combination of an inverter circuit 162 composed of OS transistors Q4, Q5, Q6 and a capacitor C2.

In the inverter circuit 161, the input (IN) is input to the gate of the PMOS transistor Q2, and the inverting input (-IN) is input to the gate of the PMOS transistor Q3 via the PMOS transistor Q1. Further, in the inverter circuit 162, the input (IN) and the inverting input (−IN) are input to the gates of the PMOS transistors Q5 and Q6 in reverse to the input of the inverter circuit 161.

Next, the operation will be described. The inverter circuit 151 of FIG. 12 has, for example, a negative logic “0” at the input (IN).
When a positive logic "1" is input to the inverting input (-IN), the PMOS transistor Q2 of the inverter circuit 161 is turned on, and "1" is output from the power supply Vdd (OU
T) and the PMOS transistor Q3 is turned off. On the contrary, the inverter circuit 162 includes the PMOS transistor Q.
5 is turned off, the PMOS transistor Q6 is turned on, and the ground level "0" is output as an inverted output (_OUT).

Further, in the inverter circuit 151, when the logics of the input (IN) and the inverted input (_IN) are opposite to the above, "0" is output from the output (OUT) side,
"1" is output from the inverted output (-OUT) side.

As described above, in the inverter circuit 151 of the present embodiment, when both positive logic and negative logic are input as the input and the inverted input, the logic negating them is output as the output and the inverted output.

Further, the inverter circuit 15 of the present embodiment
1 is a PMOS transistor Q of the inverter circuit 161
3 or the PMOS transistor Q6 of the inverter circuit 162 is turned on, the ground level is output as an output or an inverted output, but as shown in FIG.
PMO is applied to the gates of the PMOS transistors Q3 and Q6.
S-transistors Q1 and Q4 are provided for this PMO
Between the S transistor Q1 and the output end, and the PMOS
Capacitors C1 and C2 each having a predetermined capacitance are arranged between the transistor Q4 and the inverting output terminal.

Therefore, when a low level is output as an output or an inverted output, it is possible to prevent the low level from rising, and an appropriate Vdd level of "1" and a ground level of "0" are set. Can be output or as an inverted output.

FIG. 13 shows the inverter circuit 151 of FIG.
FIG. 3 is a diagram showing a symbol of “(IN)” and an inverting input (−) negating it on the input side of the inverter circuit 151.
IN), the logic of the input is inverted from the output side (OUT) and the inverted output that negates it (-O
UT) is output.

As described above, in the inverter circuit 151 shown in FIG. 12, even when a plurality of inverter circuits are connected in series, for example, there is no output level loss such that the low level rises, and the output level is always constant. Output proper ground level (0V) and power supply level (Vdd) (OU
T) or inverted output (-OUT).

Further, the inverter circuit 15 of the present embodiment
No. 1 has no output level loss as described above, and has no direct current leakage current, so that power consumption can be reduced. In the above-mentioned inverter circuit 151,
Although an example in which the circuit is composed of PMOS transistors is shown,
However, the present invention is not limited to this, and the entire TFT on the substrate can be configured by an NMOS transistor.

As described above, in the thin film semiconductor device of this embodiment, the driver circuit including the latch circuit and the shift register is formed by using the TFTs of the same conductivity type.
Since the number of times of ion doping is smaller than that of the conventional CMOS, the manufacturing cost can be reduced.

Further, since the TFT of the switching element formed in the pixel portion has a multi-gate structure, S / D
Since the withstand voltage can be increased, the leak current can be reduced and the power consumption can be reduced. Furthermore, the TFT of the switching element formed in the pixel portion is replaced with a multi-gate structure, and L
By adopting the DD structure, the leak current can be similarly reduced. This LDD structure can be formed by one-time ion doping if a double mask is used as in the above embodiment.

In the above embodiment, the TFT adopting the multi-gate structure or the LDD structure is
Although the FT is used, of course, the invention is not limited to this, and a multi-gate structure or an LDD structure may be adopted for the TFT that constitutes the liquid crystal drive circuit in order to prevent deterioration of the circuit transistor. Further, in the above-described embodiments (FIGS. 1 and 2), the transistor structure is implemented as a top gate coplanar structure, but a bottom gate inverted stagger structure or another structure can be adopted.

[0094]

According to the thin film semiconductor device of the present invention, all thin film transistors included in a thin film transistor circuit formed on one substrate are composed of transistors of the same conductivity type, and the thin film transistor circuit is composed of a plurality of thin film transistors. A driver circuit including a plurality of latch circuits, and further including a plurality of the latch circuits is formed.

Therefore, a thin film transistor circuit including a plurality of latch circuits using thin film transistors and a driver circuit using a plurality of the latch circuits is composed of only n-type or p-type conductive type thin film transistors. Therefore, the number of ion doping steps for implanting impurities is significantly reduced, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a thin film transistor of the same conductivity type according to the present embodiment.

FIG. 2 is a diagram showing a manufacturing process of a thin film transistor of the same conductivity type according to the present embodiment.

FIG. 3 is a diagram illustrating an ion doping step in the case of forming a thin film transistor of the same conductivity type according to the present embodiment with an LDD structure.

FIG. 4 is a drive circuit integrated type TFT-L according to the present embodiment.
The schematic block diagram of CD.

5 is a diagram showing a circuit configuration example of a part of the drain driver of FIG.

6 is a diagram showing a circuit configuration example of a latch circuit that constitutes the drain driver of FIG. 5;

FIG. 7 is a diagram showing a circuit configuration example of an AND / NAND circuit that configures the drain driver of FIG. 5;

8 is a diagram showing symbols of the AND / NAND circuit of FIG. 7. FIG.

9 is a diagram showing a circuit configuration example of a tri-state circuit that constitutes the drain driver of FIG.

FIG. 10 is a diagram showing symbols of the tri-state circuit of FIG.

11 is a diagram showing a circuit configuration example of a part of the gate driver of FIG.

FIG. 12 is a diagram showing a circuit configuration example of an inverter circuit which constitutes the gate driver of FIG. 11.

13 is a diagram showing symbols of the inverter circuit of FIG.

FIG. 14 is a diagram showing a configuration of a CMOS inverter circuit.

[Explanation of symbols]

10 Glass Substrate 11 Underlying Transparent Insulating Film 12 Amorphous Silicon Film 12 ′ Polysilicon Film 13 Photoresist Mask 13A, 13B, 13C Device Region 14 Silicon Oxide Film 15 Silicon Nitride Film 16 Metal Chromium Film (Gate Electrode) 17 Pixel Electrode 18 Silicon Nitride Membrane 19 S / D (source / drain)
Electrode 21 Element region 24 Channel region 25, 26 Low concentration impurity diffusion layer (P minus region) 27, 28 High concentration impurity diffusion layer (P plus region) 29, 29 'Silicon oxide film 30, 30' Photoresist 41 Driving circuit 1 Body type TFT-LC
D 42 Liquid crystal display panel 43 TFT 44 Drain driver 45 Gate driver 46 Glass substrate 50 Shift register 51, 52, 53 Latch circuit 61, 62 AND / NAND circuit 71, 72, 81, 82 Latch circuit 91, 92 Tri-state circuit 101, 102 Inverter circuit 151 Inverter circuit 161, 162 Inverter circuit

Claims (6)

[Claims] 1. A thin film transistor circuit formed on one substrate, wherein all thin film transistors included in the thin film transistor circuit are transistors of the same conductivity type, a latch circuit including the plurality of thin film transistors, and a driver including a plurality of the latch circuits. A thin film semiconductor device having a circuit formed therein. 2. The thin film semiconductor device according to claim 1, further comprising a shift register including a plurality of the latch circuits to form a driver circuit. 3. The thin film semiconductor device according to claim 1 or 2, wherein the thin film transistor is a driving circuit integrated type in which a switching element for each pixel and a liquid crystal driving circuit are integrally formed on the substrate of the liquid crystal display panel. A thin film semiconductor device comprising a liquid crystal display device, wherein at least a switching element for each pixel is configured by connecting sources / drains of a plurality of thin film transistors in series, and the gate electrodes of the plurality of thin film transistors are the same. A thin film semiconductor device characterized by being connected to a gate line. 4. The thin film semiconductor device according to claim 1 or 2, wherein the thin film transistor is a driving circuit integrated type in which a switching element for each pixel and a liquid crystal driving circuit are integrally formed on the substrate of the liquid crystal display panel. A thin-film semiconductor device comprising a liquid crystal display device, wherein a low-concentration impurity diffusion layer is formed in at least a source region and a drain region inscribed at both ends of a channel region of a thin film transistor which constitutes a switching element for each pixel, A thin-film semiconductor device having a high-concentration impurity diffusion layer formed on the outside. 5. The thin film semiconductor device according to claim 3 or 4, wherein polysilicon is used for at least a semiconductor layer of the thin film transistor of the switching element. 6. A method of manufacturing a thin film semiconductor device, wherein only a plurality of thin film transistors of the same conductivity type are formed on one substrate, and the plurality of thin film transistors are wired to form a thin film transistor circuit including a latch circuit. .