JPH09199850A - Multilayer printed circuit board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed circuit board of a structure, wherein the bonding strength of an external layer conductor pattern with the surface, which is a flat surface, to an outermost insulating layer is good and the external layer conductor pattern and other conductor patterns can be formed in a high density. SOLUTION: When a multilayer printed circuit board is manufactured into a structure, wherein conductor patterns are respectively laminated on both surfaces of a base material 12 in a multilayer via insulating layers and the laminated conductor patterns are electrically connected with each other through vias, an internal layer conductor pattern 20, which is positioned on the side of the internal layer of said base material, is formed by a method, wherein after a metal layer is formed on an insulating layer 18 formed by coating an insulative resin by a plating or the like, a patterning, such as an etching, is performed on this metal layer. Then, a metal foil 32 with a resin, which is formed by providing an insulative resin layer 23, is compression-bonded on one surface of a metal foil 25, such as a copper foil, via the layer 23 in such a way that the surface of the foil 25 becomes a flat surface to laminate the metal foil 25 on the pattern 20 and thereafter, a patterning, such as an etching, is performed on the foil 23 and an outermost conductor pattern, which is positioned on the side of the outermost layer of the base material 12, is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a method of manufacturing the same, and more specifically, a conductor pattern is laminated in multiple layers on one or both surfaces of a base material with an insulating layer interposed therebetween, and the conductor pattern is laminated. The present invention relates to a multilayer wiring board in which spaces are electrically connected via vias and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a multilayer wiring board used for a semiconductor device or the like is manufactured by a build-up method shown in FIG. In the buildup method shown in FIG. 3, first, the base material 100
After forming a metal layer of copper or the like on the base material surface of the substrate by plating or the like, the first conductor pattern 102 having a desired pattern is formed on the base material surface of the base material 100 by a photolithography method or the like (FIG. 3A).
Process). In this step, a metal layer is formed on the inner wall surface of the through hole 104 formed in the base material 100 to form a via, and the via hole is filled with a resin 106 such as a resist. Further, a concave portion 110 for forming a via is formed by etching or the like at a position where a via of a resist layer 108 formed by applying a photosensitive resist is formed on the base material surface of the base material 100 on which the first conductor pattern 102 is formed. To form. The first conductor pattern 102 is exposed on the bottom surface of the recess 110 [step of FIG. 3B]. On the surface of the resist layer 108 in which the recess 110 is formed, a second conductor pattern 112 is formed by a photolithography method on a metal layer such as copper formed by plating or the like (step of FIG. 3C). In this step, a metal layer is formed on the inner wall surface of the recess 110 for forming a via, and a via 114 that electrically connects the first conductor pattern 102 and the second conductor pattern 112 is formed.

After that, the third conductor pattern 116 is formed by repeating the steps of FIGS. 3B and 3C [steps of FIGS. 3D and 3E]. That is, after forming the recess 120 for forming a via in the resist layer 118 formed on the second conductor pattern 112 [step of FIG. 3D], a metal layer such as copper formed by plating or the like is formed on the photolithographic layer. Forming the third conductor pattern 116 by
A metal layer is formed on the inner wall surface of the via forming recess 120, and a via 122 is formed to electrically connect the second conductor pattern 112 and the third conductor pattern 116 [FIG. 3 (e)].
Process).

[0004]

According to the build-up method shown in FIG. 3 as described above, a multilayer wiring board in which electrical continuity is established between conductor patterns by only vias formed of through holes penetrating the entire board. Compared with, it is possible to obtain a high-density multilayer wiring board. However, in the build-up method shown in FIG. 3, since the insulating layer between the conductor patterns is formed by applying a resist, as shown in FIG.
Recesses are likely to be formed on the surface of the resist layer corresponding to the vias 114 and 122, and the surface of the outermost insulating layer 124 is likely to be an uneven surface. Therefore, the surface of the outer layer conductor pattern formed on the uneven surface of the outermost insulating layer 124 also becomes an uneven surface following the surface of the outermost insulating layer 124. In this way, the multilayer wiring board including the outermost insulating layer 124 having the uneven surface and the outer layer conductor pattern is
For example, when it is used for a substrate of a semiconductor device, the adhesiveness between the mounted semiconductor element and the outermost insulating layer is likely to be insufficient, and the bonding property between the mounted semiconductor element and the outer conductor pattern is likely to be poor. Therefore, the finally obtained semiconductor device is likely to be a defective product.

Further, in the multilayer wiring board formed by the build-up method shown in FIG. 3, the bonding strength (peel strength) between the conductor pattern and the outermost insulating layer is weak, and when this multilayer wiring board is used as a semiconductor device. , The mounted semiconductor element and the outer layer conductor pattern formed on the outermost insulating layer,
When wire bonding is performed by the bonding apparatus, the outer conductor pattern may be separated from the outermost insulating layer when the bonding wire whose one end is bonded to the bonding portion of the outer conductor pattern is pulled by the bonding apparatus.
Therefore, even if a semiconductor element is mounted on this multilayer wiring board by a flip chip method that does not require wire bonding, the bonding strength of the semiconductor element is insufficient, and the mounted defective semiconductor element is a good product. When a defective semiconductor element is peeled off during repair for replacement with a semiconductor element, the conductor pattern formed on the substrate may also be peeled off. Furthermore, when this multilayer wiring board is used as a BGA board, the solder ball has insufficient bonding strength, and when the package mounted on the mounting board is removed and replaced with another package, it is removed. In some cases, peeling occurred in the conductor pattern of the package.

On the other hand, when a multilayer wiring board is manufactured by laminating a metal foil with a resin in which an insulating resin layer is formed on one surface of a metal foil such as a copper foil while forming vias and conductor patterns, a multilayer wiring board is manufactured. The surface of the outermost insulating layer formed of the insulating resin of the metal foil can be made flat, and the bonding strength between this outermost insulating layer and the outer conductor pattern is also good. However, in the multilayer wiring board formed by laminating resin-coated metal foils, the recess for forming a via must be formed by a drill, a laser, etc., which complicates the manufacturing process of the multilayer wiring board and The formation density of the conductor pattern is lower than that of the multilayer wiring board formed by the build-up method shown. Therefore, an object of the present invention is to provide a multilayer wiring board which has good bonding strength between the outer-layer conductor pattern having a flat surface and the outermost insulating layer and which can form a conductor pattern with high density, and a method for manufacturing the same. is there.

[0007]

Means for Solving the Problems As a result of studies to solve the above problems, the present inventors formed an inner layer conductor pattern located on the inner layer side of the substrate by the build-up method shown in FIG. A metal foil with a resin, which is formed by forming an insulating resin layer on one side of a metal foil such as a copper foil, is laminated on a conductor pattern, and then the metal foil is patterned to form the insulating resin layer of the metal foil with a resin. By forming the outer layer conductor pattern from the metal foil of the resin-coated metal foil on the outer insulating layer,
It has been found that a multilayer wiring board in which the inner layer conductor pattern is formed at a high density and the surface of the outer layer conductor pattern is a flat surface can be easily manufactured. Furthermore, the bonding strength between the outermost insulating layer of the multilayer wiring board and the outer layer conductor pattern is the same as the bonding strength between the outermost insulating layer and the outer layer conductive pattern of the multilayer wiring board formed by the conventional build-up method shown in FIG. In comparison, they found that they were improved and arrived at the present invention. That is, the present invention, on one surface or both surfaces of the base material, a multilayer wiring board in which conductive patterns are laminated in multiple layers via insulating layers, and the stacked conductive patterns are electrically connected via vias, The inner layer conductor pattern located on the inner layer side of the substrate is formed by forming a metal layer by plating or the like on an insulating layer formed by applying an insulating resin, and then performing patterning such as etching on the metal layer. In addition, the outermost conductor pattern located in the outermost layer is a resin-coated metal foil formed by laminating an insulative resin layer on one surface of a metal foil such as copper on the inner layer conductor pattern. The outermost conductor pattern is formed by performing patterning such as etching on the metal foil laminated via the surface of the outermost conductor pattern portion located on the via formed on the inner layer side. In the multilayer wiring board, characterized by being formed as a flat surface to the same extent as the other portion surface of the outermost conductor pattern.

Further, the present invention provides one or both sides of the substrate,
When manufacturing a multilayer wiring board in which conductor patterns are laminated in multiple layers via insulating layers and the laminated conductor patterns are electrically connected via vias, an inner layer conductor positioned on the inner layer side of the substrate A pattern is formed by forming a metal layer on the insulating layer formed by applying an insulating resin by plating or the like, and then performing patterning such as etching on the metal layer, and then forming a copper layer on the inner layer conductor pattern. A metal foil with resin formed by providing an insulating resin layer on one surface of a metal foil, etc., is laminated so that the surface of the metal foil becomes a flat surface via the insulating resin layer, and then the metal foil is etched. And the like to form the outermost conductor pattern positioned in the outermost layer. In the present invention, by using a photosensitive resin as the insulating resin to be applied, it is possible to easily form a recess for forming a via in the insulating layer by a photolithography method. Further, by roughening the surface of the inner layer conductor pattern formed by patterning the metal layer, the bonding strength with the insulating layer covering the inner layer conductor pattern can be improved.

According to the present invention, the inner layer conductor pattern located on the inner layer side of the substrate is formed on the inner layer conductor pattern on the lower layer side by applying an insulating resin to the insulating layer to form a metal layer by plating or the like. Since it is formed by a build-up method in which the inner layer conductor patterns are patterned, vias that electrically connect the inner layer conductor patterns can be easily formed, and a fine inner layer conductor pattern can be easily formed. Therefore, the inner layer conductor pattern can be formed with high density. Further, after the resin-coated metal foil having an insulating resin layer provided on one surface of the metal foil on the inner conductor pattern is pressure-bonded through the insulating resin layer so that the surface of the metal foil becomes a flat surface. By patterning the metal foil, the outer conductor pattern can be formed from the metal foil of the resin-coated metal foil on the outermost insulating layer formed of the insulating resin layer of the resin-coated metal foil. For this reason, the surface of the outermost conductor pattern portion located on the via formed on the inner layer side can be made as flat as the surface of the other portion of the outermost conductor pattern, and the outermost layer conductor pattern and the outermost conductor pattern can be formed. The adhesion level with the insulating layer can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail with reference to the drawings. FIG. 1 is a partial sectional view showing an example of a multilayer wiring board according to the present invention. The multilayer wiring board 1 shown in FIG.
0 has first conductor patterns 14, 14 ... As inner layer conductor patterns formed on both surfaces of a base material 12 made of an insulating material such as resin or ceramic. The first conductor patterns 14, 14 ... Are electrically connected by vias 16 ... Such first conductor patterns 14, 14
.. are formed on the insulating layers 18, 18 formed by applying an insulating resin so as to cover the. The second conductor pattern 20 is formed by a build-up method in which a metal layer formed by plating or the like on the insulating layers 18, 18 is patterned by etching or the like, and a fine conductor pattern can be formed. The second conductor pattern 20 and the first conductor pattern 14 are the insulating layer 1
Electrical connection is made by vias 22, 22 ... In which a metal layer is formed on the inner wall surface of the recess for forming vias provided in Nos. 8 and 18. The vias 16 and 22 are filled with resin, and the resin filled in the vias 16 is an insulating resin that forms the insulating layer 18.

Outer conductor patterns 26, 26, ... Are formed on the outermost insulating layer 24 that covers the second conductor pattern 20. The outer layer conductor pattern 26 and the second conductor pattern 20 are the via 2 in which the metal layer is formed on the inner wall surface of the via forming recess provided in the outermost insulating layer 24.
It is electrically connected by 8 ... These vias 2
.. may be filled with resin or the like, if necessary, and external connection terminals such as solder balls 30 may be mounted. In such a multilayer wiring board 10, by forming the outermost insulating layer 24 and the outer layer conductor pattern 26 from a resin-coated metal foil having a metal foil such as a copper foil formed on one surface, the outermost insulating layer 24 is formed. The surface of the outer conductor pattern 26 and the outer conductor pattern 26 can be formed into a flat surface, and the bonding strength between them can be improved. The resin-coated metal foil can increase the bonding strength between the metal foil and the insulating resin layer in advance, and as described later,
The second metal foil with resin is applied so that the surface becomes a flat surface.
This is because they can be stacked on the conductor pattern 20 of. An insulating material such as a solder resist may be applied on the outer conductor patterns 26 ,.

The multilayer wiring board 10 shown in FIG. 1 can be manufactured by the method shown in FIG. The multilayer wiring board 10 shown in FIG.
Although the conductor patterns are simultaneously formed on both surfaces of the base material 12, FIG. 2 shows a procedure for forming the conductor pattern on one surface side of the base material 12 and forming the conductor pattern on the other surface side of the base material 12. The procedure was omitted. In the present invention, first, first conductor patterns 14 are formed on both surfaces of a base material 12 made of an insulating material such as resin or ceramic [FIG.
Step (A)]. When forming the conductor pattern 14, first, through holes are formed at predetermined positions of the base material 12, and then metal layers having a predetermined thickness are formed on both side surfaces of the base material 12 by plating or the like. At this time, a metal layer is also formed on the inner wall surface of the through hole. Then, a desired resist pattern is formed by a photolithography method on a photosensitive resist such as an epoxy type or a polyimide type applied on the metal layer, and then a first conductor pattern 14 is formed by a so-called subtractive method or an additive method. To do. Here, when the first conductor pattern 14 is formed by the subtractive method, a desired resist pattern is formed on the photosensitive resist applied on the metal layer by the photolithography method, and then the metal layer except the conductor pattern portion is formed. By etching the portion, the first conductor pattern 14 can be formed. When the first conductor pattern 14 is formed by the additive method, a desired resist pattern is formed on the photosensitive resist applied on the metal layer by the photolithography method, and then metal is plated on the conductor pattern portion by metal plating. The first conductor pattern 14 can be formed by stacking up to a predetermined height and then etching the metal layer portion excluding the conductor pattern portion. In order to form a desired resist pattern by the photolithography method, when the photosensitive resist is applied to the base material surface of the base material 12, the photosensitive resist filled in the through holes may be left without being removed. preferable.

A second conductor pattern 20 is formed on the first conductor pattern 14 formed in FIG. 2A by a build-up method. According to this build-up method, first, a photosensitive resist is applied on the first conductor pattern 14 to form the insulating layer 18 [step of FIG. 2 (B)]. The insulating layer 18 is exposed to light to form a via at a predetermined position.
By developing, a recess 32 for forming a via is formed. The first conductor pattern 14 is exposed on the bottom surface of the recess 32. Then, the second conductor pattern 20 electrically connected to the first conductor pattern 14 by the via 22 is formed on the insulating layer 18 in which the via forming recess 32 is formed [FIG.
Step (C)]. The second conductor pattern 20 is formed by forming a metal layer on the entire upper surface of the insulating layer 18 including the inner wall surface of the recess 32 for forming a via by plating or the like, and then forming a photosensitive resist on the metal layer. A desired resist pattern is formed by the photolithography method, and then the second conductor pattern 20 is formed by the subtractive method or the additive method described above. Thus, in FIG. 2, the recess 32 for forming a via can be formed by exposure and development, and a fine via can be easily formed in the inner layer as compared with a through hole formed by a drill or the like, so that the inner layer conductor pattern can be formed with high density. It is possible to form. The second conductor pattern 20
By roughening the surface of the above with roughening processing such as etching, it is possible to improve the bonding strength with the outermost insulating layer 24 covering the second conductor pattern 20.

In the present invention, the outermost insulating layer 24 and the outer layer conductor pattern 26 covering the second conductor pattern 20 formed by such a build-up method are provided on one surface of a metal foil such as copper with an epoxy type or a polyimide type. It is formed by a metal foil with resin formed by forming an insulating resin layer such as. Therefore, the metal foil 3 with resin is formed on the second conductor pattern 20.
2 is pressed and laminated so that the surface of the metal foil 25 becomes a flat surface [step of FIG. 2 (D)]. At this time, the resin-coated metal foil 32, the insulating layer 18, and the second conductor pattern 20.
Adhesion with the adhesive may be performed via an adhesive, but the prepreg made of a thermosetting resin semi-cured to such an extent that the insulating resin layer 23 of the resin-coated metal foil 32 is substantially extinguished in fluidity. It is preferably a layer. According to the resin-coated metal foil 32 in which the prepreg layer is the insulating resin layer 23, the resin-coated metal foil 32 is heated and pressure-bonded to be bonded onto the second conductor pattern 20 by the adhesive force of the prepreg layer itself. can do. In addition, even if the surface of the insulating layer 18 is formed into an uneven surface, the insulating resin layer 23 absorbs the resin-coated metal foil 32 by pressing and laminating so that the surface becomes flat. Thus, the surface of the metal foil 25 can be formed into a flat surface. The unevenness formed on the surface of the insulating layer 18 is minute compared to the thickness of the insulating resin layer 23, and the unevenness of the insulating resin layer 2 with the metal foil 25 is small.
The boundary surface of 3 is also a flat surface.

On the resin-coated metal foil 32 that is pressure-bonded onto the second conductor pattern 20, a via-forming recess 2 is formed at a predetermined position.
9 is formed by etching or laser processing [step of FIG. 2 (E)]. The second conductor pattern 20 is exposed on the bottom surface of the recess 29 for forming the via. After forming a via 28 by forming a metal layer on the inner wall surface of the recess 29 for forming a via by plating or the like, the outer conductor pattern 26 is formed.
To form The outer conductor pattern 26 is a metal foil 25.
A desired resist pattern can be formed on the photosensitive resist applied above by a photolithography method, and then can be formed by the subtractive method or the additive method described above. The outer layer conductor pattern 26 thus formed is formed.
Is formed from the metal foil 25 of the resin-coated metal foil 32 that is pressure-bonded and laminated so that the surface becomes flat, so that the surface can be made flat. In particular, in the outermost conductor pattern 26, the surface of the portion located on the via 22 formed on the inner layer side can also be formed as flat as the surface of the other portion of the outermost conductor pattern 26. Further, the portion of the metal foil 25 except the outer conductor pattern 26 is removed to expose the surface of the insulating resin layer 23. Since the surface of the insulating resin layer 23 is also a flat surface, the surface of the outermost insulating layer 24 made of the insulating resin layer 23 is also a flat surface. In FIG. 2, the conductor patterns are simultaneously laminated on both surfaces of the base material 12. However, the conductor patterns may be laminated on only one surface of the base material 12 as long as the base material 12 is not deformed such as warped. Good.

The resulting multilayer wiring board 10 shown in FIG.
The surfaces of the outermost insulating layer 24 and the outer conductor pattern 26 are both flat surfaces. Therefore, the multilayer wiring board 10 shown in FIG.
When, for example, is used as a substrate for a semiconductor device, the mounted semiconductor element can be brought into close contact with the outermost insulating layer 24, and the bondability between the mounted semiconductor element and the outer layer conductor pattern 26 is also good. . Further, since the outermost insulating layer 24 and the outer layer conductor pattern 26 have good bonding strength, when the semiconductor element mounted on the multilayer wiring board 10 and the outer layer conductor pattern 26 are wire-bonded by a bonding device, When the bonding wire joined to the bonding portion of the outer conductor pattern 26 is pulled by the bonding apparatus, the concern that the outer conductor pattern 26 is separated from the outermost insulating layer 24 can be eliminated. Even if a semiconductor element is mounted on the multilayer wiring substrate 10 by the flip chip method, which requires such wire bonding, the bonding strength of the semiconductor element is sufficient, and the mounted semiconductor element is a defective product, which is a good product. When repairing for replacement with a semiconductor element, a defective semiconductor element can be peeled from the multilayer wiring board 10 without peeling the outer layer conductor pattern 26. Also, when the multilayer wiring board 10 is used as a BGA board, the bonding strength between the solder balls and the board is good, and the package mounted on the mounting board is removed, and the replace for replacing with another package is removed. This can be done without peeling the outer layer conductor pattern 26 of the package.

The outer layer conductor pattern 26 of the multilayer wiring board 10 described above can be gold-plated if necessary, and the outer layer conductor pattern 26 and the second conductor pattern 14 are electrically connected. The concave portion of the via 28 can also be filled with solder resist or the like. Further, in the multilayer wiring board 10 shown in FIGS. 1 and 2, the conductor patterns are laminated in three layers, but it goes without saying that the conductor patterns may be laminated in four layers or more. Further, a metal base material can be used as the base material 12. In this case, the first conductor pattern 14 is formed on the metal base material via the insulating film. In the multilayer substrate 10 shown in FIG. 1, after the conductor patterns 14, 20, and 26 are laminated in multiple layers on both sides of the base material 12, the base material 12,
You may form the through hole which penetrates the insulating layers 18 and 28 and the conductor patterns 14, 20 and 26, and may electrically connect the outermost conductor patterns 26 and 26 formed on both surfaces of the base material 12.

[0018]

According to the present invention, the bonding strength and flatness between the outermost insulating layer and the outer conductor pattern can be improved as compared with the multilayer wiring board formed by the conventional build-up method. Therefore, when a semiconductor device is manufactured using such a multilayer wiring board, it is possible to reduce the defect rate due to insufficient bonding strength between the outermost insulating layer and the outer layer conductor pattern and poor flatness of the outer layer conductor pattern surface. be able to. Further, since the inexpensive metal foil with resin is used, it is possible to reduce the manufacturing cost of the obtained multilayer wiring board.

[Brief description of drawings]

FIG. 1 is a partial sectional view showing an example of a multilayer wiring board according to the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process for manufacturing the multilayer wiring board shown in FIG.

FIG. 3 is an explanatory diagram illustrating a conventional build-up method.

FIG. 4 is a partial cross-sectional view for explaining a surface state of an outermost insulating layer of a multilayer wiring board manufactured by a conventional build-up method.

[Explanation of symbols]

10 Multilayer Wiring Board 12 Base Material 14 First Conductor Pattern (Inner Layer Conductor Pattern) 16 Vias Comprising Through Holes 18 Insulating Layer 20 Second Conductor Pattern (Inner Layer Conductor Pattern) 22 First Conductor Pattern and Second Conductor Pattern Via 24 for electrically connecting with and 24 Outermost insulating layer 26 Outer layer conductor pattern 28 Via for electrically connecting the second conductor pattern and the outer layer conductor pattern 32 Metal foil with resin

Claims (6)

[Claims] 1. A multilayer wiring board in which conductor patterns are laminated in multiple layers on one surface or both surfaces of a base material via insulating layers, and the laminated conductor patterns are electrically connected via vias, The inner layer conductor pattern located on the inner layer side of the substrate is formed by forming a metal layer on the insulating layer formed by applying an insulating resin by plating or the like, and then performing patterning such as etching on the metal layer. Together with the outermost conductor pattern located in the outermost layer, a resin-coated metal foil formed by forming an insulating resin layer on one surface of a metal foil such as copper on the inner layer conductor pattern is laminated, and the insulating resin layer is formed. The outermost conductor pattern is formed by performing patterning such as etching on the metal foil laminated through the outermost conductor pattern, and the surface of the outermost conductor pattern portion located on the via formed on the inner layer side is the outermost conductor pattern. A multilayer wiring board, which is formed as flat as the surface of the other part of the conductor pattern. 2. The multilayer wiring board according to claim 1, wherein the insulating resin to be applied is a photosensitive resin. 3. The multilayer wiring board according to claim 1 or 2, wherein the surface of the inner conductor pattern formed by patterning the metal layer is roughened. 4. A multilayer wiring board in which conductor patterns are laminated in multiple layers on one surface or both surfaces of a base material via insulating layers, and the laminated conductor patterns are electrically connected via vias. At this time, the inner layer conductor pattern located on the inner layer side of the substrate is formed by coating a metal layer on the insulating layer formed by applying an insulating resin, and then patterning such as etching is performed on the metal layer. Then, on the inner layer conductor pattern, a metal foil with resin formed by providing an insulating resin layer on one surface of a metal foil such as copper,
After laminating so that the surface of the metal foil becomes a flat surface via the insulating resin layer, patterning such as etching is performed on the metal foil to form the outermost conductor pattern positioned in the outermost layer. Method for manufacturing multilayer wiring board. 5. The method for manufacturing a multilayer wiring board according to claim 4, wherein the insulating resin to be applied is a photosensitive resin. 6. The method for manufacturing a multilayer wiring board according to claim 4, wherein the surface of the inner conductor pattern formed by patterning the metal layer is roughened.