JPH09205187A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile storage device using a vertical channel type semiconductor and also to provide a method for manufacturing the storage device. SOLUTION: A semiconductor substrate 11 is etched to form a protrudent portion 12 on it. The protrudent portion 12 is covered with a first conductive coating 15 and then subjected to an anisotropic etching process to form a coating as a floating gate on side faces of the protrudent portion 12. The structure is then subjected to an element separating or isolating process based on a selective oxidizing technique to form a second conductive coating 21, and then to the anisotropic etching process to form a control gate 23 on the side faces of the protrudeut portion 12. At this time, a mask is formed for necessary parts of the protrudent portion 12, and the etching of the second conductive coating 21 causes formation of the gate and wiring pattern of a planar MOS transistor. In this way, there is formed a nonvolatile storage which, in particular, comprises a NAND circuit made up of the planar MOS transistors as select transistors and vertical channel type transistors as storage cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for highly integrating a semiconductor integrated circuit. In the present invention, a semiconductor device suitable for high integration is proposed especially regarding a field effect element, and a manufacturing method thereof will be described. The semiconductor device according to the present invention is used especially for a nonvolatile semiconductor memory device having a floating gate.

[0002]

2. Description of the Related Art A conventional semiconductor device is formed in a plane. For example, a field effect element (MOS type (or MI
In the example of (S type) field effect transistor (FET),
The source, drain, and channel are arranged in a substantially planar manner so that the drain current flows parallel to the substrate.
However, in such a planar (planar type) element, there is a limit to the reduction of the element area. Therefore, in order to achieve higher integration, a technique for forming a planar type element in multiple layers and making the element structure itself non-planar have been studied. As an example of the latter, a vertical channel MOSFET proposed by the present inventors (Japanese Patent Laid-Open No. 6-13 / 1994).
627) and so on. In this, the drain is arranged above (or below) the source so that the drain current flows substantially vertically. With such a structure, high integration of the device can be achieved.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
27 relates to a non-volatile semiconductor memory.
That is, the floating gate and the control gate are formed on the side surface of the convex portion formed on the semiconductor substrate by the anisotropic etching method. However, only the basic device structure was shown. It is an object of the present invention to provide a more optimal structure and manufacturing method for an element having such a structure, and to disclose a preferable mode for a NAND type nonvolatile memory.

[0004]

A method of manufacturing a semiconductor device according to the present invention has the following steps. Step of etching semiconductor substrate to form convex portion Step of forming insulating coating on exposed surface of semiconductor substrate Step of forming first conductive coating Step of forming first conductive coating by anisotropic etching method A step of forming a film to be a floating gate on the side surface of the convex portion by etching

Step of forming an insulating coating on the surface of the floating gate Step of selectively oxidizing the semiconductor substrate and / or the first conductive coating to obtain an oxide for element isolation Forming a second conductive coating The step of selectively forming a mask on the second conductive film, the second conductive film is etched by an anisotropic etching method to cover the floating gate on the side surface of the convex portion, Step of forming control gate and obtaining gate of planar type MOS transistor at the same time

[0006] Here, the steps are
It may be between steps. Further, it is desirable that the step of diffusing the impurity imparting one conductivity type (doping step) is performed after the step. By doing so,
This is because the source / drain (impurity region) of the planar MOSFET can be formed in self-alignment with the gate. Further, in order to carry out the multi-layer wiring as in the known technique, after the step, an interlayer insulating material may be formed to form the upper wiring. In the process, a so-called local oxidation method (LOCOS) may be used, or a technique developed from it may be used. As the method of forming the insulating coating in the steps and, a thermal oxidation method, a thermal nitriding method may be used, or a vapor phase film forming method may be used.

The first conductive film formed by the process is a film which becomes a floating gate after the etching process. Generally, as a result of anisotropic etching in the process, a continuous first conductive film is left on one side surface of one protrusion. However, when forming a plurality of elements on this one side surface, the floating gate needs to be separated (insulated) for each element. The step is for forming an oxide for element isolation and at the same time isolating the floating gate for each element.

Although it has been described above that the steps may be between the steps and between the steps, each case will be briefly discussed below. First, when it is between the step and the oxide for element isolation, the first film is divided first, and then, by the step, is formed on the side surface of the convex portion, and as a result, It is possible to obtain a floating gate divided for each element.
Also, when it is between the steps, in the selective oxidation,
Since the oxidation mask (usually made of silicon nitride) is in direct contact with the semiconductor substrate and the first conductive film, there is a risk of peeling, but this is not impossible. For this reason, the position of the process may be between the process and the process.

The above is a description of the general manufacturing method of the present invention. Next, a special case will be described. When applying the manufacturing process of the present invention to the configuration of the NAND type nonvolatile memory which is a promising application example of the present invention, attention must be paid to the element isolation technique. Japanese Unexamined Patent Publication No. 6-13627 was not limited to the NAND type circuit. The NAND type circuit has an upper layer wiring (N
In the case of the AND type, it is possible to reduce the number of contacts with the bit line and, if necessary, the ground line.

In a normal NAND type circuit, a unit memory block is composed of four or more, preferably eight or more memory cells (memory transistors), which are connected in series. Further, each block is provided with at least two selection transistors with the memory cell interposed therebetween. The number of contacts with the bit line is one for each source of each select transistor, that is, two for each block. It is also possible to make one for each block by sharing a contact with an adjacent block. 4 of 1 block,
When the memory cell is composed of eight memory cells, the number of contacts is 1/4 and 1/8 per memory cell.

On the other hand, in a usual matrix type memory circuit, at least one contact is required for each memory cell. Such a large number of contacts is disadvantageous from the viewpoint of high integration of the circuit. In order to apply the present invention to a NAND type circuit, first, in a process, it is required to form a plurality of oxides for element isolation in a direction substantially perpendicular to a word line. Of course, in the process, it is necessary to form a groove in a direction parallel to the word line, that is, to obtain a linear convex portion.

Element isolation is not necessary between memory cells or select transistors in series, but is necessary between transistors that are not. Therefore, the insulator for element isolation in the process is formed at the same interval for each transistor row. Further, in the present invention, two elements are formed on the side surface of one linear convex portion, so that two word lines are formed for each linear convex portion. Then, since the word line and the transistor array intersect, the insulator for element isolation and the linear convex portion (or groove) intersect.

Next, in the NAND type circuit, a selection transistor (a transistor having a normal structure having no floating gate) is required in addition to the memory cell. In the present invention, a planar MOSFET may be used as the selection transistor. Planar type MOSFE
Since the first conductive film in the portion where T is formed is etched by the process, the planar MOSFET
Are all normal transistors (transistors without floating gates).

The impurity region of the select transistor is required to contact the bit line and the ground line. Therefore, it is more advantageous to provide the select transistor on the surface of the convex portion than on the groove portion in order to form the contact hole. The planar type MOSFET may be manufactured according to the method described later. By using the planar transistor as the selection transistor, it is not necessary to form a contact in the convex portion where the vertical channel element is formed. This is advantageous in the following points. That is, the width of such a convex portion that does not require a contact may be designed according to the minimum design rule. If you need to contact us ,. Its width will be required at least twice the minimum design rule.

In the case of manufacturing a semiconductor device using the present invention, in addition to the selection transistor, it may be considered that some elements such as peripheral circuits are required to be configured by the conventional planar type. Further, in principle, in the present invention, the second conductive film other than the side surface of the convex portion is entirely etched, so that it is difficult to form a contact between the control gate and the upper layer wiring as it is. Therefore, a process is required for such purpose.

If, after that step, anisotropic etching is performed by the step, the portion where the mask is formed is not etched. That is, as a result of the process, the side surface of the convex portion,
Alternatively, the second conductive film other than the mask portion is etched. The gate / wiring of the planar MOSFET and the contact formation portion at the final end of the control gate are portions to be masked.

The formation of the source and drain of the planar MOSFET is performed after the formation of the gate.
That is, it may be performed after the step. In the doping process, the effective depth of the source and drain δ
And the etching depth (groove depth) d in the process, it is necessary to satisfy the following conditions. d> δ If this is not satisfied, the impurities will diffuse even under the convex portions, and a vertical channel cannot be substantially formed.

As described above, one photolithography process is added to manufacture a planar type MOSFET in addition to the vertical channel type element. In the step, the first conductive film formed on the plane is entirely etched unless a mask is provided, so that the planar MO film is formed.
A floating gate cannot be formed in the SFET.

[0019]

【Example】

[Embodiment 1] FIG. 1 shows an embodiment of the present invention. This example is for explaining the basics of manufacturing a semiconductor device such as a nonvolatile memory device using the present invention. FIG. 1 shows fabrication cross sections of three typical parts.
That is, from the left, a portion where a planar element is provided, a portion where an oxide for element isolation is provided, and a portion where a vertical channel element is provided.

First, as shown in FIG. 1 (A), a plurality of grooves (or recesses) 13 are formed on a semiconductor substrate 11 to form projections 12. The height of the protrusion 12 is the same as the surface of the semiconductor substrate at the beginning. The depth of the groove 13 has a great relationship with the channel length of the vertical channel element to be formed. In the figure, in order to make the boundary with the semiconductor substrate easy to understand,
Although the surface portion is shaded, this does not mean that the composition, conductivity, etc. of the portion are different from those of the other portions. The above steps correspond to steps. Next, the oxide film 14 is formed on the semiconductor surface formed as described above by a known method such as thermal oxidation (corresponding to a step).
(Fig. 1 (A))

Then, the first conductive film 15 is formed using a semiconductor material or the like by a known film forming technique (corresponding to a step). In that case, it is necessary to adopt a film forming technique having a high covering property such that a film is sufficiently formed on the side surface of the convex portion. The thickness of the coating is 1/5 to 1 / the depth of the groove 13.
2 is preferred. (FIG. 1B) Next, the film 15 is etched by a known anisotropic etching method (corresponding to a step). As a result, the film 16 to be the floating gate is left only on the side surface of the convex portion, and the other portions are etched. This coating 16 is continuous along the groove. (Fig. 1 (C))

Further, an insulating film 17 is formed on the surface of the film 16 by a known film forming technique such as a thermal oxidation method (corresponding to a step). (FIG. 1D) Next, a selective oxidation step (corresponding to a step) is performed. At this time, first, a silicon nitride film is used as an oxidation resistant mask. That is, as shown in the drawing, the oxidation resistant mask 18 is formed except for the portion where the oxide is formed (that is, the portion where the element is formed on the semiconductor). (FIG. 1 (E))

Thereafter, the oxide film 1 is applied to the unmasked portion by a thermal oxidation method, preferably a steam thermal oxidation method.
9 is formed thick. After the oxidation step, the oxidation resistant mask 18 is etched, and the selective oxidation step is completed. (Figure 1
(F))

Then, the second conductive coating film 20 is formed by using a known film forming technique using a semiconductor material or a metal material (corresponding to a step). Also in this case, it is necessary to adopt a technique having excellent step coverage, and the thickness of the coating is preferably 1/5 to 1/2 of the depth of the groove 13. Then, the mask 21 is selectively formed on the second conductive film 20 by a known photolithography method (corresponding to a step). The mask is formed at the portion where the wiring is formed by using the gate of the planar type MOS transistor and the second conductive film. (Fig. 1 (G))

Further, the second conductive film 20 is etched by a known anisotropic etching method (corresponding to a step). As a result, the control gate 2 is attached to the side surface of the protrusion.
3 is left, and at the same time, the gate of the planar type MOS transistor is also formed. The other parts are etched. In particular, the control gate 23 is formed on the floating gate 16 as is apparent in the right part of the figure, and the control gate 23 is formed on the side surface of the convex portion even in the part without the floating gate as in the center part of the figure. It is formed. That is, the control gate 23 is formed along the groove 13. (Fig. 1 (H))

Further, an impurity region is formed by a known impurity diffusion technique such as an ion implantation method. As a result, the impurity region 25 is formed on the top of the protrusion 12 and the impurity region 26 is formed on the bottom of the groove 13. Further, the impurity region 24 of the planar type MOS transistor is also formed. (FIG. 1I) In this way, a semiconductor device having memory cells of a non-volatile memory device can be formed.

[Embodiment 2] This embodiment relates to a manufacturing process and a circuit configuration of a NAND type nonvolatile memory device using the present invention. This embodiment will be described with reference to FIGS. 2A to 2C show a state in which the main part of the semiconductor device of this embodiment is viewed from above in the order of manufacturing steps. A rectangular portion surrounded by a dotted line in the figure is a unit memory block. In this embodiment, two selection transistors and four select transistors are provided.
It consists of two memory cells. 3 and 4 are shown in FIG.
In the figure, the states of the cross sections of the portions indicated by XX ′ and YY ′ in FIG. Further, FIG. 6 shows an example of the arrangement of bit lines and ground lines in this embodiment, and FIG. 5 is a circuit diagram corresponding thereto. Less than,
The steps will be described in order.

First, like the first embodiment, the groove 33 is formed in the semiconductor substrate 31 to obtain the convex portion 32. Further, the oxide film 34 is formed on the semiconductor surface by a known method such as thermal oxidation. In FIG. 2, only the portion having the same height as the initial semiconductor substrate is shown as a shaded portion. In addition, in FIGS. 3 and 4, the boundary with the semiconductor substrate and the surface are shaded for the same reason as in FIG. (FIG. 2 (A), FIG. 3 (A), FIG. 4 (A))

Then, a first conductive film is formed using a semiconductor material or the like by a known film forming technique, and this is etched by a known anisotropic etching method as in Example 1. As a result, the film 36 to be the floating gate is obtained only on the side surface of the convex portion. The coating 36 is continuous along the groove 33. (FIG. 3 (B), FIG.
(B))

Further, an insulating film is formed on the surface of the film 36 by a known film forming technique such as a thermal oxidation method.
Then, as in Example 1, selective oxidation is performed using a silicon nitride film as an oxidation resistant mask. That is, FIG.
As shown in (B), the oxidation-resistant mask 38 is perpendicular to the groove 33.
To form (FIG. 2 (B), FIG. 3 (C), FIG. 4 (C))

Thereafter, the oxide film 3 is applied to the unmasked portion by a thermal oxidation method, preferably a steam thermal oxidation method.
9 is formed thick. No oxide is formed in the XX 'section (FIG. 3) because it was masked, but an oxide is formed in the YY' section (FIG. 4). Although it is not clear in FIG. 2, as is clear from FIG.
9 is also formed in the groove 33. That is, FIG.
In, the upper and lower elements can be separated. Further, by this oxidation step, the coating film 36 which has been continuous along the groove 33 until then is divided. (FIG. 2 (C), FIG. 3 (D),
Figure 4 (D))

Next, the second conductive film 40 is formed by using a known film forming technique using a semiconductor material or a metal material. Then, masks 41a and 4 are selectively formed on the second conductive film 40 by a known photolithography method.
1b is formed. The mask is formed in a portion where the gate of the selection transistor (planar type MOS transistor) is formed. (Fig. 3 (E), Fig. 4 (E))

Further, the second conductive film 40 is etched by a known anisotropic etching method. As a result, the control gates 43a to 43d are left on the side surface of the convex portion, and the gates 42a and 42 of the selection transistor are
b is formed. The other parts are etched.
(FIG. 3 (F), FIG. 4 (F)) Then, an impurity region is formed by a known impurity diffusion technique such as an ion implantation method. As a result, impurity regions 45a to 45d and 44a, 44b are formed on the tops of the protrusions, and impurity regions 46a, 46b are formed on the bottoms of the grooves. (Fig. 3 (G))

Thereafter, the interlayer insulator 4 is formed by using a known technique.
7 are formed, contact holes 48a and 48b communicating with the impurity regions 44a and 44b are formed therein, and upper layer wirings (here, ground lines) 49a such as bit lines and ground lines are formed.
49b is formed. Figure 2 shows the contact holes
It is shown in (D). In this way, the selection transistor and the memory cell can be formed. (Fig. 2 (D), Fig. 3
(H), FIG. 4 (G))

There are two possible methods for arranging the upper layer wiring such as the bit line and the ground line. The first is FIG.
As shown in (A), the upper-layer wiring is provided with an oxide 39 for element isolation.
It is a method to arrange on this in parallel with. Circuit diagram is Figure 5
It is shown in (A). However, in this method, as shown in the figure, from the concern of contact with the adjacent upper layer wiring,
The distance from other upper layer wiring cannot be less than the minimum design rule. Therefore, it is difficult to form a contact by completely covering the contact hole. (FIG. 5
(A), FIG. 6 (A))

To solve this problem, the upper layer wiring may be arranged diagonally as shown in FIG. 6 (B). The circuit diagram in this case is shown in FIG. Alternatively, the upper layer wiring may be arranged in a zigzag. Thus, the wiring can be arranged so as to completely cover the contact hole.
(FIG. 5 (B), FIG. 6 (B))

In this way, a non-volatile memory device can be formed. In the above example, the ground line is formed in parallel with the bit line, but the ground line may be an impurity region formed on the substrate. That is, when the oxide for element isolation is formed, as shown in FIG.
It suffices if c is formed.

FIG. 7 shows a state in which a gate, a control gate and the like have been removed in the element after the doping is completed. The impurity region 44d corresponds to the impurity region 44b in FIG. A contact with the wire is provided. On the other hand, the impurity region 44c is not provided with a contact for each memory block, and the impurity region connected from the top to the bottom of the drawing serves as a ground line. By doing so, the resistance of the ground wire is increased, but the number of contacts can be halved. (FIG. 7)

[0039]

According to the present invention, a highly integrated semiconductor device can be manufactured. The invention is particularly applicable to NAND
Type of non-volatile memory device will bring significant technological advances. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment.

2A to 2D show steps of manufacturing a semiconductor device of Example 2.
(View from above)

3A to 3C show steps of manufacturing a semiconductor device of Example 2.
(Cross section)

FIG. 4 shows a manufacturing process of a semiconductor device according to a second embodiment.
(Cross section)

FIG. 5 is a circuit diagram of a semiconductor device according to a second embodiment.

FIG. 6 is a diagram showing an arrangement of upper layer wirings of a semiconductor device of Example 2;

FIG. 7 is an element isolation insulator of the semiconductor device of Example 2;
FIG. 6 is a diagram showing an arrangement of impurity regions and contacts.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... Convex part 13 ... Groove (or recessed part) 14 ... Insulator film 15 ... 1st conductive film 16 ... Etching of 1st conductive film 17 ... Insulator film 18 ... Oxidation resistant mask 19 ... Element isolation oxide 20 ... Second conductive film 21 ... Mask 22 ... Planar type MOS transistor Gate 23 ... Control Gate 24, 25, 26 ... Impurity region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/792

Claims (6)

[Claims] 1. A step of forming a convex portion on a semiconductor substrate, a step of forming a first conductive film, and a step of anisotropically etching the first conductive film. And leaving a floating gate or a conductive coating to be the floating gate on the side surface of the convex portion (4) forming a second conductive coating (5) selecting on the second conductive coating (6) Anisotropic etching is performed on the second conductive film to cover the floating gate on the side surface of the convex portion to form a control gate, and at the same time, a planar type mask is formed. Forming the gate of the MOS transistor of (7) In the method of manufacturing a semiconductor device, including the step of introducing an impurity imparting one conductivity type into the semiconductor substrate, A method for manufacturing a semiconductor device, comprising a step of selectively oxidizing a semiconductor substrate and / or the first conductive film to form an oxide for element isolation between the steps (2) and (4). . 2. The convex portion is obtained by forming a plurality of grooves in one direction on a semiconductor substrate, and the oxide for element isolation is formed substantially perpendicular to the groove. The method for manufacturing a semiconductor device according to claim 1, wherein 3. The method for manufacturing a semiconductor device according to claim 1, wherein the planar MOS transistor is a semiconductor device formed on a convex portion. 4. A NAND-type non-volatile memory device, wherein a unit block has a plurality of memory cells that have a floating gate and are connected in series, and are connected to each other with the memory cells connected in series interposed therebetween. And at least two selection transistors, wherein the memory cell has a top of a convex portion obtained by a plurality of grooves formed on a semiconductor substrate, and an impurity region in the groove existing between the convex portions, The floating gate has a control gate and a control gate formed by an anisotropic etching method on the side surface of the protrusion, the floating gate is divided by an oxide formed for element isolation, the selection transistor, The gate of the select transistor is formed on the convex portion of the semiconductor substrate, and the gate of the select transistor is the same as the control gate of the memory cell. Simultaneously formed and arranged in parallel with the control gate, the impurity region of the select transistor is formed at the same time as the impurity region of the memory cell, and the bit line or the ground line formed on the interlayer insulator is the select region. A semiconductor device having a contact with one of impurity regions of a transistor. 5. The semiconductor device according to claim 4, wherein the element isolation oxide is substantially orthogonal to the convex portion. 6. The semiconductor device according to claim 4, wherein the oxide for element isolation is substantially orthogonal to the control gate.