JPH09218859A - Multiprocessor control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of the whole system by receiving a processing starting instruction from a central processor, writing the processing result in a response buffer through a response buffer mediation circuit and reading the processing result of a task from the response buffer. SOLUTION: Each of all the subprocessors SPU 4-1 to 4-n in idle states in which no processings are not executed performs a read access to an instruction buffer 2 through an instruction buffer mediation circuit 5, receives a processing starting instruction from a central processor 1 and writes the processing result in a response buffer 3 through a response buffer mediation circuit 6. The central processor 1 reads the processing result of a task from the response buffer 3 after the processor 1 writes the processing starting instruction in the instruction buffer 2. As a result, the improvement of the throughput of the whole system can be expected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having a general purpose or a specific purpose, and more particularly to a multiprocessor control system using a plurality of processors.

[0002]

2. Description of the Related Art Conventionally, in a computer system using a multiprocessor, in addition to a central processing processor, one or a plurality of subprocessors dedicated to a specific processing are provided in order to increase the processing capacity of the system. The processing processor and these sub-processors are operated in parallel. This has increased the throughput of the system.

Here, the central processor is referred to as MP
U (Master Processing Unit) and sub processors are called SPU (Slave Processing Unit). The MPU 1 controls the entire system including the control of the SPU. The SPU performs various kinds of arithmetic processing based on the instructions of the MPU. CMD / B between MPU and SPU
The UF and the RPS / BUF are provided as relay buffers. The CMD / BUF (Command Buffer) is used to instruct an operation from the MPU to the SPU, transfer parameters required when the SPU performs an operation, and the like. RPS / BU
F (Response Buffer) is S, which is the opposite of CMD and BUF.
As a communication means from PU to MPU, it is used for notification of calculation completion and transfer of calculation results. CMD / BUF and RPS / B
One set of UF is provided for each SPU. C
The MD / BUF and the RPS / BUF are composed of a RAM and a FIFO memory.

The contents of the processing performed by the SPU are predetermined, and a state in which the SPU is not performing the calculation is called an idle state. When a process for operating the SPU occurs, the MPU determines which SPU is to perform the process, and gives an instruction to start the process through the CMD / BUF of the SPU. When there are a plurality of processes to be performed by the SPU, the SPUs that are idle are determined one after another and a process start instruction is sent. The SPU, which has received the processing start instruction, performs a predetermined calculation and then sends a processing end notification to the MPU.
Through UF. After the processing ends, the SPU returns to the idle state.

[0005]

By the way, the conventional multiprocessor control system as described above has the following problems to be solved. In the multiprocessor control system with the above configuration, the MPU must manage the idle state of each SPU because the MPU controls the operation of each SPU. For this reason, the processing related to the control becomes complicated, and the processing that the MPU must perform, such as magnetic disk control, is delayed. This allows
There was a problem that it hindered the improvement of the throughput of the entire system. Especially, when the number of SPUs increases, the problem becomes remarkable. Therefore, even if the number of SPUs is increased to increase the processing speed,
There is also a problem that the throughput cannot be further improved due to the limit of the processing capacity of the MPU.

[0006]

The present invention employs the following structure to solve the above problems. <Structure 1> A central processing processor that controls the processing of an arbitrary task, a plurality of sub-processors that execute the above processing upon request from the central processing processor, and a processing start instruction of the central processing processor are accepted, An instruction buffer that holds this processing start instruction until one of the sub-processors reads it, a response buffer that holds the processing result of the sub-processor that has executed the processing and holds this processing result until the central processing processor reads it, An instruction buffer arbitration circuit arranged between the instruction buffer and all the sub-processors, which performs contention adjustment when a plurality of sub-processors simultaneously read-accesses the instruction buffer, and between all the sub-processors and the response buffer. Inserted in between, multiple sub-processors respond simultaneously The a response buffer arbitration circuit running a competition adjustment when the write access, nothing all sub-processor idle not running processing,
The instruction buffer arbitration circuit performs read access to the instruction buffer, receives a processing start instruction from the central processing processor, writes the processing result in the response buffer through the response buffer arbitration circuit, and the central processing processor A multiprocessor control system characterized by reading a processing result of a task from the response buffer after writing a processing start instruction in the instruction buffer.

<Explanation> The central processing processor is expressed as MPU and the sub-processor is expressed as SPU. The MPU requests one of the SPUs to process the generated task. Each of the plurality of SPUs simultaneously executes the requested processing in parallel. SPUs that are not idle cannot accept new task requests. The SPU in the idle state voluntarily reads and accesses the instruction buffer, so that the MPU does not need to recognize which SPU is in the idle state. The instruction buffer arbitration circuit is provided because contention occurs when a plurality of idle SPUs read-access the instruction buffer at arbitrary timings. Further, the response buffer arbitration circuit is provided for each S
This is because the PU causes conflict when the task processing result is write-accessed to the response buffer at an arbitrary timing.

<Structure 2> In Structure 1, a plurality of central processing processors are provided, and each central processing processor includes
A set of an instruction buffer and an instruction buffer arbitration circuit and a response buffer and a response buffer arbitration circuit are connected to each other, and each instruction buffer arbitration circuit and a response buffer arbitration circuit are connected to all sub-processors and read by each sub-processor. A multiprocessor control system characterized by arbitrating contention between access and write access.

<Explanation> When there are not one MPU but a plurality of MPUs and each controls the processing of a predetermined task, an instruction buffer for accepting the processing start instruction of each MPU and a response buffer for accepting its response. And are provided for each MPU. Arbitration circuits for competitive arbitration are also provided individually. At this time, the plurality of SPUs are
Task may be processed. That is, each MPU is
PU can be shared.

<Structure 3> A central processing processor for controlling the processing of an arbitrary task and a plurality of sub-processors for executing the above processing upon receiving a request from the central processing processor are provided. The sub processors are connected to each other in a ring shape via a data bus, and the processing data output by the central processing processor, which requests the task processing, is transferred in order from the first sub processor to the last sub processor. When it is transferred back to the central processing processor, and the sub processor in the idle state receives the transfer of the processing data, the processing is executed, and the sub processor which finished the processing writes the processing result to the processing data and transfers it. When the processing result is written in the transferred processing data, the central processing processor Receives the processed data, when the content of the as-requested processing, multi-processor control system, characterized in that to transfer the processed data again.

<Explanation> The ring shape means a loop shape or a chain shape in which both ends are connected.
The first SPU is connected via the data bus, all the SPUs are connected in turn via the data bus, and the last SPU is connected to the MPU via the data bus. A processing request by the MPU or a processing result by the SPU is written in the processing data and transferred in order. The non-idle SPU transfers the processed data as it is to the succeeding SPU. If the last SPU is not idle, the processed data returns to the MPU. Since the processing request of the MPU is sequentially transferred to all the SPUs via the data bus, the MPU does not need to be aware of the SPU in the idle state.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to specific examples. SPECIFIC EXAMPLE 1 FIG. 1 shows a block diagram of a first specific example of the system of the present invention. MPU1 and SPU4-1 to 4-n
Respectively form a central processor and a sub-processor as in the prior art. CMD / BUF (Comman
The d Buffer) 2 is used to instruct an operation from the MPU 1 to the SPUs 4-1 to 4-n, transfer parameters required when the SPUs 4-1 to 4-n perform an operation, and the like. CMD B
Instructions and the like are written in the UF2 by the MPU1, and the SPU4-1 is sent via a CMD / BUF arbitration circuit 5 described later.
Read to 4-n. RPS / BUF (Response B
3) is used as a communication means from the SPUs 4-1 to 4-n to the MPU 1 to notify the end of calculation, transfer the calculation result, and the like. RPS / BUF3 is an RPS / BUF described later.
Notifications and the like are written by the SPUs 4-1 to 4-n via the SPU 6 and read by the MPU 1.

CMD / BUF2 and RPS / BUF3
Is provided for one MPU regardless of the number of SPUs. CMD / BUF2 and RPS / BUF3 are
It is composed of a RAM and a FIFO memory and can store a plurality of data. The CMD / BUF arbitration circuit 5 exists between the CMD / BUF2 and the SPUs 4-1 to 4-n, and arbitrates access competition when each SPU reads the CMD / BUF2. Therefore, C
The MD / BUF arbitration circuit 5 includes all SPUs 4-1 to 4-
n. As the arbitration method, the well-known competitive arbitration technology such as the fixed priority method and the round robin method is used.

The RPS / BUF arbitration circuit 6 is
It exists between the UF3 and the SPUs 4-1 to 4-n, and performs arbitration of access competition when each SPU writes the RPS / BUF3. Therefore, the RPS / BUF arbitration circuit 6 is connected to all the SPUs 4-1 to 4-n.
As an arbitration method, a known technology such as a fixed priority method or a round robin method is used as in the CMD / BUF arbitration circuit 5. In addition, in this system,
There is a memory, a display controller, a keyboard controller, and a magnetic disk controller (not shown), and the MPU 1 also controls these.

<Operation of Concrete Example 1> SPUs 4-1 to 4-n
The contents of the processing performed by the
A state in which U is not performing the processing is called an idle state. It is assumed that the system is now in operation. Immediately after the system is started, it is assumed that the tasks to be processed by SPU4-1 to 4-n have not occurred. Therefore, CMD and BUF
The content of 2 is empty because the MPU 1 has not issued a processing start request to the SPUs 4-1 to 4-n. On the other hand, when the operation of the system is started, each SPU 4-1 to 4-n reads the CMD / BUF 2 in order to know whether or not a task to be processed has occurred. At this time, since a plurality of SPUs 4-1 to 4-n check the CMD / BUF2, a read access conflict occurs. CMD
The BUF arbitration circuit 5 includes the Cs from the SPUs 4-1 to 4-n.
For read access to MD / BUF2, read access permission is given to any one of the SPUs by a predetermined contention arbitration method. Also, in this case,
Since the contents of CMD / BUF2 are empty, the status of no data is returned to the SPU. Each SPU4-1 to 4-n
Always checks the CMD / BUF2 in the idle state. Therefore, in this case, the no-data status is returned to the SPUs 4-1 to 4-n one after another.

It is assumed that a task to be processed by one of the SPUs 4-1 to 4-n has occurred during the processing of the MPU 1 after the passage of time. Then, the MPU 1 makes the SPUs 4-1 to 4-n
A processing start instruction is issued to. At this time, MPU1
Does not manage which SPU among a plurality of SPUs is idle or busy. When a task to be processed by the SPUs 4-1 to 4-n occurs, the MPU 1 sends an SPU to the CMD / BUF2.
Write the processing start instruction code. Each SPU4-1 to 4-
Since n always checks CMD / BUF2, MPU1 sends the processing start instruction code to CMD / BUF2.
Immediately after writing to, any one of the SPUs performing the CMD / BUF check at that time will receive this processing start instruction. SPU that received the processing start instruction
Performs processing according to the instruction. The content of the CMD / BUF2 becomes empty again after a certain SPU reads the processing start instruction code.

When a task to be processed by the SPUs 4-1 to 4-n is generated, the MPU 1 can write the processing start instruction code in the CMD BUF 2 one after another. Since the idle SPUs start processing one after another by checking CMD / BUF2, the number of tasks is S
Parallel processing can be performed at the same time as the number of PUs. The SPU that has completed the process sends the result and the process completion code to the RPS /
Write to BUF3. At this time, the RPS / BUF arbitration circuit 6 arbitrates by a predetermined competitive arbitration method,
RPS / BUF write permission is given to any one SPU. A plurality of processing results can be stored in the RPS / BUF3. The MPU 1 can obtain the processing result of the SPU by reading the result from the RPS / BUF3.

<Effect of Concrete Example 1> As described above, according to this concrete example, since the MPU 1 does not manage the operating states of the SPUs 4-1 to 4-n, the time conventionally involved in the processing is Can be used for processing. Therefore, the MPU 1 can concentrate on other system control processing, such as magnetic disk control (not shown), and can be expected to improve the throughput of the entire system. Further, according to this specific example, since the management of the SPUs 4-1 to 4-n is removed from the management of the MPU, the software change of the MPU 1 due to the addition of the SPU can be minimized. Further, it goes without saying that new development of software for the added SPU is unnecessary. For the same reason, since it is relatively easy to increase or decrease the number of SPUs, there is an advantage that the system configuration can be flexibly configured according to the performance, cost and size of the target system.

<Second Embodiment> FIG. 2 shows a block diagram of a second embodiment of the system of the present invention. In this specific example, M
There are two PUs. That is, MPU1-1 and MPU1-
There are two. CMD / BUF2-1, 2-2, CMD
-BUF arbitration circuits 5-1 and 5-2, RPS-BUF3-
1, 3-2, RPS / BUF arbitration circuit 6-1, 6-2
Are provided for each MPU. A corresponding R is assigned to each RPS / BUF3-1 and 3-2.
SPU4 via PS / BUF arbitration circuits 6-1 and 6-2
Notifications and the like are written by -1 to 4-n, and read by the corresponding MPUs 1-1 and 1-2.

Each CMD / BUF arbitration circuit 5-1 to 5-2
Are CMD / BUF2-1, 2-2 and SPU4-1-4
Exist between -n and SPU4-1 to 4-n are CMD · B.
Arbitration of access contention when reading UF2-1, 2-2. Therefore, the CMD / BUF arbitration circuits 5-1 to 5-1
5-2 is connected to all SPUs 4-1 to 4-n. As the arbitration method, similarly to the first specific example, a known technology such as a fixed priority method or a round robin method is used. RPS / BUF arbitration circuit 6-1,
6-2 is RPS / BUF3-1, 3-2 and SPU4-
1 to 4-n exist, and SPU4-1 to 4-n are RP
Arbitration of access conflict when writing S-BUF3-1 and 3-2. Therefore, the RPS / BUF arbitration circuit 6
-1, 6-2 are connected to all the SPUs 4-1 to 4-n. The arbitration method is the same as in the first specific example.

CMD ・ BUF2-1, 2-2, CMD ・
BUF arbitration circuits 5-1 and 5-2, and RPS / BUF3
-1, 3-2, RPS / BUF arbitration circuits 6-1, 6-2
Is provided for one MPU regardless of the number of SPUs. CMD / BUF2-1, 2-2 and RPS /
Each of the BUFs 3-1 and 3-2 is composed of a RAM or a FIFO memory and can store a plurality of data. The other parts are the same as those in the first specific example.

<Operation of Concrete Example 2> SPUs 4-1 to 4-n
The content of the processing performed by is predetermined. It is assumed that the system is now in operation. The MPU 1-1 and 1-2 operate independently. SPU4 immediately after system start
The tasks to be processed by -1 to 4-n are MPU1-1, M
It is assumed that it has not occurred in either of PU1-2. Therefore, the contents of CMD BUF2-1, 2-2 are both M
It is empty because PU1-1 and 1-2 have not issued a process start request to SPU4-1 to 4-n.

On the other hand, when the operation of the system is started, each of the SPUs 4-1 to 4-n recognizes whether or not a task to be processed has occurred.
Alternate two leads. At this time, since a plurality of SPUs check both CMD / BUF2-1 and 2-2, contention for read access occurs. Two CMDs
The BUF arbitration circuits 5-1 and 5-2 have the SPUs 4-1 to 4 respectively.
With respect to the read access to the CMD / BUF2-1, 2-2 from -n, the read access permission is given to any one of the SPUs by a predetermined contention arbitration method. In this case, CMD BUF2-1,2-
Since the content of 2 is empty, a status of no data is returned to the SPU. In the idle state, each SPU 4-1 to 4-n always alternately checks CMD / BUF2-1 and 2-2. Therefore, in this case, the no-data status is sequentially returned to each SPU.

It is assumed that a task to be processed by the SPU has occurred during the processing of the MPU 1-1 after the passage of time. Then M
The PU 1-1 will issue a processing start instruction to the SPU. At this time, the MPU 1-1 has a plurality of SPUs 4
It does not manage which SPU among -1 to 4-n is idle and busy. When a task to be processed by the SPU occurs, the MPU 1-1
The SPU process start instruction code is written to BUF2-1. Each of the SPUs 4-1 to 4-n has a CM in the idle state.
Since the D.BUF2-1 and 2-2 are checked, the MPU1-1 sends the processing start instruction code to the CMD.BU.
Immediately after writing to F2-1, any one of the SPUs that was performing the CMD / BUF check at that time receives this processing start instruction. The SPU that has received the processing start instruction performs processing according to the instruction. CMD / BUF
The content of 2-1 becomes empty again because one SPU has read the processing start instruction code.

On the other hand, the MPU1-2 operates completely independently of the MPU1-1, and when a task to be processed by the SPU occurs, the SPU is used by using the CMD / BUF2-2.
Send instructions to. MPU1-1 and 1-2 are SPU
When a task to be processed by CMD occurs, CMD BU
Processing start instruction codes can be written in F2-1 and 2-2 one after another. Idle SPU is CMD B
Since the processing is started one after another by alternately checking UF2-1 and UF-2, two MPU1-1 and
The number of tasks requested by 1-2 can be simultaneously processed by the number of SPUs 4-1 to 4-n.

The processed SPU writes the result and the processing end code into the corresponding RPS / BUF3-1 and 3-2. For example, the processing performed in response to the processing instruction from the MPU 1 is written in the RPS / BUF3-1.
At this time, the RPS / BUF arbitration circuits 6-1 and 6-2 perform arbitration by a predetermined contention arbitration method and give RPS / BUF write permission to any one of the SPUs. A plurality of processing results can be stored in the RPS / BUF3-1 and 3-2. MPU1-1 and 1-2 are R
The processing result of the SPU can be obtained by reading the results from the PS / BUF 3-1 and 3-2. Although two MPUs are described in this example, exactly the same operation can be realized even if there are two or more MPUs.

<Effect of Concrete Example 2> As described above,
According to this specific example, since the plurality of MPUs do not manage the operating states of the SPUs, the SPUs are not assigned to a specific MPU.
Since it is not necessary to assign it to the SPU, effective use can be achieved with a small number of SPUs, and the throughput of the entire system can be increased.

<Embodiment 3> FIG. 3 shows a block diagram of a third embodiment of the system of the present invention. Here, one M
A computer system including PU1 and n SPUs 4-1 to 4-n will be described as an example. The arrows in the figure indicate the direction of data transfer. The transmission data bus 13 of MPU1 is connected from MPU1 to SPU4-1. The transmission data bus 3 of the MPU 1 simultaneously transmits the SPU 4
It becomes a reception data bus of -1. The transmission data bus 15-1 of the SPU4-1 is connected from the SPU4-1 to the SPU4-2. Transmission data bus 15-1 of SPU4-1
Simultaneously serves as a reception data bus of SPU4-2. Similarly, the transmission data bus 15-2 of the SPU4-2 is connected to the SPU4-3 (not shown), and the transmission data bus 15-n of the final stage SPU4-n is connected to the MPU1. S
The transmission data bus 15-n of the PU4-n simultaneously receives the MPU.
1 reception data bus.

The interrupt signal 6 from MPU1 to SPU4-1 is connected from MPU1 to SPU4-1. S
Interrupt signal 17-1 from PU4-1 to SPU4-2
Is connected from SPU4-1 to SPU4-2. Similarly, interrupt signal 1 from SPU4-2 to SPU4-3
7-2 is connected from SPU4-2 to SPU4-3, and an interrupt signal 17-from SPU4-n to MPU1.
n is connected from SPU4-n to MPU1. As described above, in this system, the data bus and the interrupt signal connect the processors to each other, and have a loop-like configuration as a whole.

<Operation of Concrete Example 3> The function of the MPU 1 controls the entire system in the same manner as the functions up to now.
The SPUs 4-1 to 4-n perform various types of arithmetic processing based on the instruction from the MPU 1. Also in this specific example, the MPU 1 does not manage the states of the SPUs 4-1 to 4-n. MPU1
When a task to be processed by the SPUs 4-1 to 4-n occurs, the transmission data bus 3 is used to transfer the data required for the processing, and the interrupt signal 6 is used to send the SP.
Notify U4-1 accordingly.

In FIG. 2, the MPU 1 has SPUs 4-1 to 4-n.
Shows an example of the format of processing data for requesting a task. The processed data 20 is composed of a data string of several words, and the first data is an ID code 21 indicating the type of the data. The contents are, for example,
It is determined in advance that process A is performed when ID = 00, process B is performed when ID = 01, process C is performed when ID = 02, and so on. Further, it also serves as an ID code at the time of transfer of a processing result from the SPU, which will be described later. When ID = 80, the result of processing A, when ID = 81, the result of processing B, I
When D = 82, the result of the process C is determined as follows.

The second word of the processing data 20 stores the number of words 22 of the transfer data 23-1 to 23-t.
The third and subsequent words of the processing data 20 are the transfer data string used for the processing or the transfer data string of the processing result. Now, the SPU 4-1 uses the interrupt signal 16 from the MPU 1 as a trigger to process data 20 from the MPU 1.
Receive. If the SPU 4-1 is busy at this time, the SPU 4-1 cannot accept the processing request from the MPU 1, and therefore transfers the processing data from the MPU 1 using the transmission data bus 15-1 to the SPU 4-2. , SPU4-2 using the interrupt signal 17-1
Notify.

When the SPU4-1 is in the idle state, SPU4-1
PU4-1 is the ID code 2 of the processing data from MPU1.
Check 1 and perform processing according to the code. A corresponding ID code 21 is added to the processing result, and SP is added.
The process data is transferred using the transmission data bus 15-1 to the U4-2, and S is transmitted using the interrupt signal 17-1.
Notify PU4-2. SPU4-2 to 4- (n-1)
Receives data by using an interrupt signal from the SPU in the preceding stage as a trigger. If the self is busy or if the data sent as a result of the ID code check is the processing result of the previous processor, the data is passed to the next processor as it is, and the self is idle. And the ID code 21 is MPU1
If it is a processing request from, the processing is performed. The processing result is transferred by using the transmission data bus to the processor at the next stage and is notified by using the interrupt signal.

The processed data from the SPU4-n at the final stage is sent to the MPU1. The MPU 1 checks the ID code 21, confirms that it is the result of the processing requested by itself, and stores the result in a memory or the like not shown.
If each SPU 4-1 to 4-n is busy, M
The processing requested by PU1 may return to MPU1 without being processed by any SPU. In this case, MPU1 is I
The D code 21 determines that the transferred data is unprocessed, and requests the SPUs 4-1 to 4-n to process again.

<Effect of Concrete Example 3> As described above, according to this concrete example, since the MPU 1 does not manage the operating states of the SPUs 4-1 to 4-n connected in series on the bus, the conventional method is not used. The time that was involved in processing can be used for other processing. Therefore, the MPU can concentrate on other system control processing, such as magnetic disk control (not shown), so that the throughput of the entire system can be expected to improve. Further, according to this specific example, since the management of the SPU is removed from the management of the MPU, it is possible to minimize the software change of the MPU accompanying the addition of the SPU. Similarly, new development of software for the added SPU is unnecessary. Further, for the same reason, since the number of SPUs can be relatively easily increased and decreased, there is an advantage that the system configuration can be flexibly configured according to the performance, cost and size of the target system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first specific example of a system of the present invention.

FIG. 2 is a block diagram showing a second specific example of the system of the present invention.

FIG. 3 is a block diagram showing a third specific example of the system of the present invention.

FIG. 4 is an explanatory diagram of an example of a processing data format used in a third specific example.

[Explanation of symbols]

 1 MPU 2 CMD / BUF 3 RPS / BUF 4-1 to 4-n SPU 5 CMD / BUF arbitration circuit 6 RPS / BUF arbitration circuit

Claims (3)

[Claims] 1. A central processing processor that controls the processing of an arbitrary task, a plurality of sub-processors that execute the processing upon request of the central processing processor, and a processing start instruction of the central processing processor. ,
An instruction buffer that holds this processing start instruction until one of the sub-processors reads it, a response buffer that receives the processing result of the sub-processor that has executed the processing and holds this processing result until the central processing processor reads it, An instruction buffer arbitration circuit arranged between the instruction buffer and all the sub-processors, which performs contention adjustment when a plurality of sub-processors simultaneously read-accesses the instruction buffer, and between all the sub-processors and the response buffer. And a response buffer arbitration circuit that is inserted between them and performs contention adjustment when a plurality of subprocessors simultaneously write-access the response buffer. Read the instruction buffer through the instruction buffer arbitration circuit. Access, receives a processing start instruction from the central processing processor, writes the processing result to the response buffer through the response buffer arbitration circuit, and the central processing processor writes the processing start instruction to the instruction buffer. A multiprocessor control system for reading the processing result of a task from the response buffer. 2. The plurality of central processing processors according to claim 1, wherein a set of an instruction buffer and an instruction buffer arbitration circuit, and a response buffer and a response buffer arbitration circuit are connected to each of the central processing processors. The instruction buffer arbitration circuit and the response buffer arbitration circuit are
A multiprocessor control system, which is connected to all subprocessors and arbitrates competition between read access and write access of each subprocessor. 3. A central processing processor that controls the processing of an arbitrary task, and a plurality of sub-processors that execute the processing when requested by the central processing processor, the central processing processor and the plurality of sub-processors. Is
They are connected to each other in a ring shape via a data bus,
The processing data requesting task processing output from the central processing processor is transferred in order from the first sub-processor, and from the last sub-processor back to the central processing processor. Upon receiving the transfer, the sub-processor, which executes the process and ends the process, writes the process result to the process data and transfers it, and the central processor writes the process result in the transferred process data. A multiprocessor control system characterized by receiving the processing data when the processing is in progress, and transferring the processing data again when the processing is still requested.