JPH09213895A - High voltage horizontal semiconductor device - Google Patents

Abstract

(57) Abstract: A high withstand voltage lateral MOS formed on a junction separation substrate.
Prevent the breakdown voltage of the device from decreasing due to the influence of wiring,
At the same time, the size and cost of the semiconductor chip are reduced. A p-embedded layer and an n-embedded layer are formed on a p-substrate, an n-type epitaxial layer is formed thereon, and then a p-isolation region is selectively formed from the surface of the epitaxial layer. n drain region 6 is formed,
An n-epi layer 2 serving as an element formation region and an n-epi layer 2a serving as an isolation region, which are connected to each buried layer, are formed, a p low-concentration region 20 is formed in a surface layer of the n-epi layer 2a, and an n-drain region 6 is formed. And LOCO on the p isolation region 5
Field plates A15 and B1 through the S oxide film 16
9 is formed, and each field plate is connected to the drain electrode 11 or the ground electrode 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a withstand voltage design of a semiconductor switching element, and more particularly to a high withstand voltage lateral semiconductor device having a structure in which the influence of electrode wiring and the like is reduced.

[0002]

2. Description of the Related Art A high breakdown voltage output circuit and a control circuit for driving it (generally, the applied voltage of the control circuit is 5 V with respect to the ground potential) are integrated on one semiconductor chip. In the field of so-called "power IC", a semiconductor substrate in which a junction separation technique is applied to an epitaxial wafer having a buried layer is widely used in a device withstand voltage range of 100 to 200 V in an output stage. (The semiconductor substrate described here is silicon (Si),
Silicon carbide (SiC) may be used). Also, if the element breakdown voltage of the output stage is about 100 V, it is cheap and the simplest C
A semiconductor substrate using a bonding and separating technique is often used on a Z wafer. On the other hand, when the element breakdown voltage of the output stage is 200 V or more, it is ideal to use an SOI wafer and a semiconductor substrate in which each element is separated by a dielectric isolation technique.
The I-wafer is more than 3 times as expensive as the CZ wafer and twice as much as the epitaxial wafer, and the manufacturing cost of the dielectric isolation technology is about 5 times that of the junction isolation, and its output current is 250 mA. It is used only for special purposes that exceed.

As a specific application example of the "power IC" manufactured by using the junction separation technique on the buried epitaxial wafer, a scan side driver IC for a plasma display (for writing image data to a pixel on the display) IC), and the rated voltage is 150 V / maximum output current 40 mA. FIG. 5 is a cross-sectional view of essential parts of a general high withstand voltage lateral semiconductor device. In the figure, an n-channel MOS-FET (hereinafter,
FIG. 6 is a cross-sectional view of a case where an n-ch MOSFET is built in, particularly focusing on a diffusion layer and an electrode arrangement.

An n epitaxial layer having a high specific resistance is provided above the p substrate 1 whose specific resistance is set in consideration of the element isolation breakdown voltage. Further, p or n described before the name of each part indicates the conductivity type of the corresponding part. A p-embedded layer 3 and an n-embedded layer 4 are partially present at the boundary between the p-substrate 1 and the n-type epitaxial layer, and a p-isolation region 5 is selectively formed on the upper portion of the p-embedded layer 3 and the n-embedded layer from the surface of the epitaxial layer. The n drain regions 6 are formed by thermal diffusion and are connected to the respective buried layers, and this epitaxial layer is divided into an n epi layer 2 forming an element and an n epi layer 2a serving as an isolation region. Here, the epi layer means an epitaxial layer after diffusing the n drain region 6 and the p isolation region 5. In this thermal diffusion step, the p-type and n-type impurities diffuse from the p-embedded layer 3 and the n-embedded layer 4 into the epitaxial layer, and the buried layer expands. As a result, the n epi layer 2 forming the device has a structure divided by the p isolation region 5 and the p buried layer 3. A p-well region 7 is provided on the surface of the n-epi layer 2 surrounded by the n-drain region 6, and an n-source region 8 is formed without penetrating the p-well region 7. A gate electrode 9 is disposed above the semiconductor with the n-epi layer 2 and the n-source region 8 interposed therebetween via a thin gate insulating film (not shown), and the p-well region 7 and the n-source region 8 are in contact at the same time. A drain electrode 11 in contact with the electrode 10 and the n drain region 6 is arranged. A ground electrode 12 is in contact with the p isolation region 5 in order to fix the potential of the p substrate 1.

The n-ch MOSFET shown in FIG. 5 is used on the high side in an electric circuit, and the drain electrode 11 and the ground electrode 12 are fixed to the power supply potential VdH and the ground potential (earth), respectively. (In some cases, an electrode is provided on the exposed surface of the p substrate 1 to drop it to the ground potential). The source electrode 10 is connected to a circuit or the like formed in another isolation region, and similarly, the gate electrode 9 is electrically connected to a control circuit formed in another isolation region. The potentials of the gate electrode and the source electrode can be changed by switching the gate signal between the ground potential and the power supply potential VdH, although it depends on the connected circuit configuration (as a matter of course, the gate-source voltage is a performance of a thin gate insulating film). Must be considered so that it does not deteriorate). For the sake of clarity, the low potential state is called the L level and the high potential state is called the H level.

When the drain electrode 11 is at the H level applied to the power supply potential VdH, the pn junction formed by the p isolation region 5, the p buried layer 3, the p substrate 1 and the n epi layer 2a and the n buried layer 4 is reversed. Since it is in a biased state, a depletion layer is formed inside the semiconductor and a breakdown voltage is secured. Even when the gate electrode 9 and the source electrode 10 are at the L level, the pn junction formed by the n epi layer 2 and the p well region 7 surrounded by the n drain region 6 and the n buried layer 4 is in a reverse biased state. Become. Therefore, when designing a breakdown voltage, it is necessary to pay attention to the impurity concentration, the interval, the shape, and the breakdown voltage structure of the semiconductor surface portion that determine the conductivity type of these portions.

[0007]

The elements formed in the same chip are connected to each other by a wiring material over the respective isolation regions (p isolation region 5 and n epi layer 2a). Naturally, the interlayer insulating film is arranged so that the semiconductor portion and the wiring material do not come into inadvertent contact with each other. A "power IC" including the element shown in FIG. 5 was designed and prototyped in consideration of various breakdown voltage structures of the portion where the wiring material is arranged over the isolation region, and a breakdown voltage of 180 V can be obtained. It was

However, when an accelerated test of the prototype IC at a high temperature of 125 ° C. is performed, it takes about 300 hours to reach 20 V.
It turned out to be reduced to some extent. As a result of investigating the phenomenon of lowering the breakdown voltage from various viewpoints, it was found to be a so-called "degradation phenomenon due to the gate control diode structure".
For this phenomenon, refer to Electronics Technology Complete Manual 3 "M
OS device ”(written by Shiba Tokuyama, first edition August 20, 1973, published by the Industrial Research Board), Chapter 7,“ pn junction and M ”
OS structure ". The contents of this report are as follows. When a MOS structure is formed on the upper surface of the pn junction, if the reverse bias is applied to the pn junction for a long time under the influence of the gate potential, for example, in the state where the inversion layer is formed on the surface of the p region, the leakage current increases. (Since the breakdown voltage is defined by the magnitude of the reverse current, it is judged that the breakdown voltage decreases when the leak current increases). In the prototype device, it was found that the gate and source lead wirings were similar to the "gate control diode structure" in that the portion arranged above the isolation region was located.

FIG. 6 is a main part configuration diagram of a portion that causes a problem of lowering the withstand voltage in a high withstand voltage lateral semiconductor device. FIG. 6A is a plan view and FIG. 6B is an A- line in FIG. 6A. It is sectional drawing cut | disconnected by the A line. In FIG. 6, a normal gate electrode 9 is poly-Si (having a sheet resistance of 30 to 80Ω) having good conductivity.
/ □), and the gate wiring 14 electrically connected thereto via the contact hole 13e crosses the upper portion of the p isolation region 5 and is connected to the control circuit. p
The isolation region 5 and the n drain region 6 are also connected to the ground electrode 12 and the drain electrode 11 via the respective contact holes 13b and 13c. The drain electrode 11 is also connected to a field plate A15 on the drain side, which is provided to obtain a breakdown voltage, through a contact hole 13d. Since the field plate A15 is usually formed at the same time as the gate electrode 9, it is made of the same material and has the same thickness. The drain electrode 11, the ground electrode 12, and the gate wiring 14 are usually made of Al-Si.
These three electrodes and the like are also formed at the same time. The cross-sectional view of FIG. 7B shows a state of being cut along the line AA. A LOCOS oxide film 16 is disposed on the surface of the semiconductor, then a field plate A15 on the drain side, an interlayer insulating film 17 (usually a BPSG film is formed using a low pressure CVD apparatus), and a gate wiring 14 are stacked. ing. The actual device is further covered with a final passivation film, but it is omitted here because it is not directly related here. A p offset region 18 is provided in the semiconductor surface layer so as to overlap the p isolation region 5. This is also introduced for the purpose of ensuring the breakdown voltage. Before forming the LOCOS oxide film 16, impurities are selectively introduced by an ion implantation method using a resist mask. This step is also necessary to form a high breakdown voltage p-channel MOS-FET formed on the n-epi layer 2a surrounded by the p-isolation region 5 at another location (not shown). Although it does not increase, if combined, it is impossible to select the optimum impurity introduction amount and diffusion depth for the breakdown voltage design. Here, holes on the surface
The concentration was 1 × 10 ¹⁶ [atm / cm ³ ] and the depth was 2.0 μm. Therefore, the design element is only the dimension that is protruding from the p isolation region.

The thicknesses of the LOCOS oxide film 16 and the interlayer insulating film 17 are 0.7 μm and 1.3 μm, respectively. The gate wiring 14 is also disposed above the p offset region 18 via these insulating films, and this portion has a MOS structure. Moreover, even when a high reverse bias voltage is applied between the drain electrode 11 and the ground electrode 12, the gate wiring 9 repeats the potentials of the L level and the H level, and it is considered that the deterioration phenomenon occurs.

As a measure against the deterioration, first, the thickness of the LOCOS oxide film 16 and the interlayer insulating film 17 may be increased, but the deterioration is observed even in the acceleration test at 100V which is two-thirds of the rated voltage 150V. Therefore, simply,
The total film thickness has to be made larger than 3 μm, and it is practically impossible to manufacture it on a mass production level. As a next measure, the field plate B19 on the ground side as well.
It is assumed that

FIG. 7 is a sectional view in which field plates are provided on both the drain electrode side and the ground electrode side. The field plate B19 is connected to the ground electrode 12 and the p isolation region 5, which are not shown, and is always at the same potential as the p isolation region 5,
No inversion layer is formed by the MOS structure (the semiconductor surface is shielded from the upper gate wiring 14 by the field plates A and B). With this structure, a withstand voltage design was performed again, the conditions were narrowed down, and a second prototype was made.

FIG. 8 shows the device simulation used for the breakdown voltage calculation.
An example of the basic model of the solution and the calculation results.
A cross-sectional view of the element used in the calculation.
(C) is the calculated hole concentration distribution.
You. The figure (a) shows the calculation area, and the whole semiconductor
The width of the region is 30 μm and the thickness is 35 μm.
From the surface of the layer 2, the p isolation region 5 and the n
Rain regions 6 are arranged at an interval of 15.2 μm,
Each has a ground potential (earth potential) and VdH
An electrode was provided to give the position. The thickness of the semiconductor surface is 2μ
through the insulating film of m (assuming silicon oxide film)
A pole 9 is provided. This is similar to gate wiring in an actual device
The potential VGL of the gate electrode 9 can be set freely.
I made it possible. Also, the thickness of the n-epi layer 2a is 14 μm
Each embedding layer was arranged in the part. The thickness of the p substrate 1 is 21
μm, this value is very different from the actual value, but the depletion layer
It is already known that it does not spread so much,
It has no effect. 8B and 8C show the B visual field direction.
And HO in thermal equilibrium state (temperature 300K)
This shows the distribution of the density. Maximum electron density is 5.0 x 1
0¹⁹(Atm / cm^Three], The maximum hole density is 5.0 × 10
¹⁹[atm / cm^Three] Also, the electron density of the n-epi layer 2, 2a
Is 1.0 × 10^Fifteen[atm / cm^Three], And the hole density of the p substrate 1
Is 5.5 × 10 ¹⁴[atm / cm^Three] Less than the thickness of p substrate 1
The outside is the same as the prototype device.

FIG. 9 is a carrier concentration distribution diagram when there is no field plate. FIG. 9A is a bird's eye view of the potential at the L level of VGL = 0, and FIG. 9B is the L potential level of VGL = 0. A potential diagram, (c) is a bird's-eye view of the potential at the H level of VGL = VdH, and (d) is an equipotential diagram at the H level of VGL = VdH. The range of potential shown in the bird's eye view is 0
˜200V, and the equipotential line per line is 20V. In the figures (a) and (b), VGL is fixed to 0V and VdH is set to 1
It is a state immediately before the avalanche current starts to flow up by the V step. At this time, VdH = 113V, and this value was set as the design value of the isolation breakdown voltage. Similarly, FIG.
(D) shows the case where VGL = VdH, and VdH = 118V is the design withstand voltage. From the bird's-eye view, it can be seen that VGL is rising similarly to VdH. Also, the area where the equipotential line is blocked is n
It can be seen that the surface is moving from the surface boundary between the epi layer 2a and the n drain region 6 to the surface boundary between the n epi layer 2 and the p isolation region 5.

FIG. 10 shows a calculation example in the case where the field plates A and B corresponding to FIG. 7 are installed. FIG. 10A shows a cross-sectional view of the device and a two-dimensional potential distribution diagram at the L level of VGL = 0. FIG. 3B is a device sectional view and a two-dimensional potential distribution diagram at the H level of VGL = VdH. The number of equipotential lines increases,
Further, it can be seen that it has moved to the surface of the n-epi layer 2a. Also, it can be seen that the field plate A is effective mainly when VGL is at the L level, and the field plate B is effective when VGL is at the H level.

FIG. 11 is a diagram showing the relationship between the length of the field plates A and B and the isolation breakdown voltage. From the calculation as described above, the length of the field plate is determined by the length L _FPD , p which is the length protruding from the n drain region 6 to the n epitaxial side 2a as shown in FIG.
The length protruding from the isolation region 5 was defined as L _FPI . As the conditions, when L _FPD = 4 μm and V GL = VdH, L _FPI is taken on the horizontal axis and the isolation breakdown voltage is taken on the vertical axis, and the calculation results are shown by circles. For reference, the results when the field plate B is not provided and when the p offset region is provided as in the first trial production are also shown. It was found from the calculation result that when L _FPI = 3 to 6 μm, the value was almost VdH = 180 V, and the level of the first prototype was obtained. Field plate B
Since the inversion layer cannot be formed in the pn junction as can be seen from the equipotential lines in FIG. 9, it is expected that the breakdown voltage can be prevented from lowering. Therefore, based on the above results, L _FPI
= 4 μm, L _FPD = 4 μm A second trial production was carried out with a field plate, and the results are shown by the X mark (average value) in FIG. 10 and the maximum and minimum values by error bars. As can be seen from the figure, the average value is almost the same as the design value, but it is found that the variation is larger than that in the first prototype. 160
Since V and above are good products, about 10% are defective products.
It was found that the yield decreased at this point. It is considered that the reason for the difference in the variation is that the variation in the specific resistance of the p-type substrate 1 causes a difference in how the depletion layer in the substrate expands, resulting in a slight influence on the surface voltage distribution. When the p offset region 18 is provided, it is considered that the redundancy is high with respect to this fluctuation.

In the field plate structure, this problem can be avoided by increasing the gap, but it is disadvantageous because the chip area increases. In addition, JP-A-3-2117
As disclosed in Japanese Patent Publication No. 71, etc., in order to obtain the same effect as in the case where the p offset region 18 is arranged also in the field plate, high resistance poly-Si,
An example of doing this is shown, and it is conceivable to apply this structure, but in this case, since it cannot be manufactured at the same time as the gate electrode 9, there is a problem that the manufacturing cost increases.

An object of the present invention is to solve the above problems and to provide a high breakdown voltage lateral semiconductor device having a high breakdown voltage and no deterioration without increasing the manufacturing cost. Further, in some cases, it is one of the purposes to downsize the high breakdown voltage lateral semiconductor device.

[0019]

In order to achieve the above-mentioned object, a first region of a first conductivity type and a first region of a higher concentration than the first semiconductor layer are formed on one main surface of a first semiconductor layer of a first conductivity type. Second regions of the second conductivity type are formed at a predetermined interval, and second semiconductor layers of the second conductivity type are collectively stacked on the respective surfaces of the first semiconductor layer, the first region and the second region, A first conductivity type isolation region reaching the first region from the surface of the second semiconductor layer and a second conductivity type third region reaching the second region are formed,
A fourth semiconductor layer surrounded by the first semiconductor layer, the isolation region and the third region
A second region, a third region and a fifth region of the junction separation substrate in which a fifth region surrounded by the region, the second region and the third region is formed.
In a lateral semiconductor device in which a MOS device is formed in a region, an insulating film is selectively formed on the surface of the junction separation substrate, and metal wiring is formed on the surface of the insulating film on the fourth region,
The first conductive film and the second conductive film are embedded in the insulating film on the isolation region and the third region, respectively, and the first conductive film penetrates the insulating film and is selectively fixed to the isolation region. Penetrates through the insulating film and is selectively fixed to the third region, and at least the first layer is formed on the surface layer of the fourth region under the metal wiring.
A sixth region of conductivity type is formed. The sixth region may be formed over the entire circumference of the fourth region. Also the fifth
When a plurality of MOS devices are formed in the area,
It is effective that the sixth region is formed separately. Further, by setting the potential of the sixth region to a floating potential, the electric field strength in the fourth region can be weakened.

According to this structure, by arranging the field plate having a fixed electric potential at least up to the region located above the pn junction, the influence of wiring or the like which is located further above and in which the electric potential changes greatly is blocked. At the same time, since the phenomenon such as the formation of an inversion layer at the pn junction is eliminated, deterioration can be prevented. Further, in order to make the voltage distribution on the surface of the n-epi layer uniform, a p-region having a floating potential is provided. The function of both the field plate and the p- region has the effect of shortening the separation distance applicable to high breakdown voltage.

Further, by arranging the p-regions in the separation region in a circular shape discontinuously, the voltage distribution of the corresponding portion is always determined so as to be self-aligned with itself, so that the redundancy is excellent. . Further, by utilizing this characteristic, a plurality of elements can be formed in one isolation region even with a high breakdown voltage element, and the area of the isolation region can be reduced as a whole.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic view of the essential part of a first embodiment of the present invention, in which FIG. 1 (a) is a plan view and FIG. 1 (b) is a line AA in FIG. 1 (a). It is sectional drawing cut | disconnected by. The numbers in the figure are the same as those in the conventional structure, and the interlayer insulating film is omitted in FIG.
The main difference from the conventional structure of FIG.
It is formed on the surface layer of the n epi layer 2 sandwiched between the drain region 6 and the p isolation region so that the gate wiring crosses over the p low concentration region 20, and the field plate A15 and the field plate B19 are n. The point is that they are arranged so as not to protrude from the upper part of the drain region 6 and the upper part of the p isolation region 5 to the n-epi layer 2a of the isolation region. The ground electrode 12 is connected to the p isolation region 6 through the contact hole 13a,
It is connected to the field plate B through the contact hole 13b. In this embodiment, the p low concentration region is the n epi layer 2
7 is arranged over the entire circumference, but when the p low-concentration region 20 is provided only under the gate wiring 14, the field plate A15 and the field plate B19 arranged other than under the gate wiring 14 are as shown in FIG. It is necessary to optimize the length by arranging it so as to protrude to the n-epi layer 2a.
Naturally, the p low-concentration region is arranged over the entire circumference of the n epi layer 2a, and the field plate A15 and the field plate B19 are arranged so as to protrude into the n epi layer 2a as shown in FIG. Of course, it may be optimized. On the n-epi layer 2a having the gate electrode 9, a p-well region and a source region (not shown) of the MOS device are formed.

FIG. 2 shows the results of the breakdown voltage calculation according to the present invention. FIG. 2A is a bird's eye view of the potential when VGL = 0 [V], and FIG. 2B is the view when VGL = 0 [V]. Potential diagram, (c) is a distribution diagram of the amount of avalanche carriers generated when VGL = 0 [V], (d) is a bird's eye view of the potential when VGL = VdH, and (e) is An equipotential diagram in the case of VGL = VdH, and FIG. 6F is a distribution diagram of the avalanche carrier generation amount in the case of VGL = VdH. The potential range shown here in a bird's-eye view is 0 to 200 V, the equipotential line per line is 20 V, and the range of carrier generation amount is 10 ^17.
It is about 10 ²² [atm / cm ³ ].

In FIG. 2, in the case of VGL = 0 [V] in FIGS. 7A to 7C, there is almost no difference from the case where the conventional p offset region is provided and optimized, and the same applies to the floating potential. It turns out that there is a great effect. This is the same as, for example, a guard ring that is widely used for a pressure resistance concept in a vertical device. It has been found that avalanche carriers are generated at two places, that is, the surface part of the n-drain region 6 and the n-epi layer 2a and each boundary part between the n-buried layer 4 and the p-substrate 1, and the surface structure is optimized. The design value of the isolation breakdown voltage at this time is 192V.

Next, VGL = V in FIGS.
In the case of dH, the avalanche carrier is generated at the surface of the p isolation region 5 and the n epi layer 2, and at the boundary between the n buried layer 4 and the p substrate 1. The design value of the isolation breakdown voltage at this time was 189V. In detail, it can be seen that the peak portion of the surface portion corresponds to the n-epi layer 2a and the field plate B19 is arranged to weaken the electric field intensity in the p-isolation region 5. On the other hand, the p low concentration region 20 has a potential between approximately 120V and 180V. Therefore, the potential difference from the upper gate wiring 9 is 9 to 69V. It is considered that this cannot form a sufficient inversion layer in the surface layer of the p isolation region through the 2 μm insulating film. Incidentally, if the p-offset region 18 is continuous with the p-isolation region 5 as in the structure having the conventional p-offset region, the potential difference becomes large, and it can be inferred that the inversion layer is formed somewhere.

The structure shown in this embodiment has the p low concentration region 2
The width of 0 and the distance from the p isolation region 5 are design points, and the width of the p low concentration region 20 is set to 4.5 μm
In the case of making a prototype by changing the range of 5.5 μm, the width of the p low-concentration region 20 is 5 μm and the diffusion position is designed to be 11 μm from the end of the p isolation region to satisfy the characteristics as a whole. done. First, the average breakdown voltage of the device is L
It was 195V at the level and 187V at the H level. In addition, the range of device breakdown voltage within one lot is 165V to 2
At 05V, it was found that there was no problem because the degree of variation was about the same as the first prototype (conventional p-offset structure product).

FIG. 3 shows the results of an accelerated test at a high temperature of 125 ° C. comparing the conventional structure product and the present invention product. 5 for each prototype with an initial withstand voltage of about 180V
This is a plot of the average value of the breakdown voltage depending on the test time prepared individually (Ld with VdH = 150V applied during the test).
Level and H level were repeated, and the breakdown voltage was plotted when the breakdown voltage was set to L level at room temperature). First prototype (×
As described above, in the mark (), a withstand voltage decrease of about 20 V is observed in 300 hours. On the other hand, a secondary prototype (L _FLI = 4 μm, Δ mark) that hinders the “gate control diode structure” by the field plate and the product of the present invention (L _FPI =
0 μm, ◯ mark), no significant decrease in withstand voltage was observed even after 1000 hours. However, it is not possible with the second prototype because the initial breakdown voltage varies widely. In addition, design specifications are L
_FPI = 0.5 μm, and the distance between the p isolation region 5 and the n drain region 6 is 24 μm on the diffusion mask and after diffusion 1
4.2 μm (25 μm on the diffusion mask when L _FPI = 0 μm
After diffusion at 15.2 μm), the width of the p low concentration region is 4 μm
(5 μm when L _FPI = 0 μm) was changed to a prototype, and a similar acceleration test was attempted. As a result, no decrease in device breakdown voltage was observed. The mask accuracy when manufacturing the device is ± 0.3 or less.

In the first embodiment, when one high side n-ch MOSFET is formed in one isolation region, the p isolation region 5 is formed so as to surround the n drain region 6.
Must be located, and therefore the n drain region 6-
The area occupied by the p isolation regions 5 also increases. Generally, in a 5 V driven logic circuit, a relatively large p isolation region 5 is secured, and a plurality of elements are formed in the p isolation region 5 to minimize the area. In this case, since the voltage is as low as about 5 V, the “degradation phenomenon due to the gate control diode structure” is not observed in the isolation region without special consideration. An example in which a structure similar to this is applied to a high breakdown voltage lateral semiconductor device will be described below.

FIG. 4 is a plan view of the essential portions of the second embodiment of the present invention. Regarding the numbers in the figure, the same numbers are used for the same numbers as described above. Further, the field plates A and B are not shown for the sake of clarity, but they are actually arranged. Two n-ch MOSFETs are incorporated in the upper and lower parts of the drawing, but since they are used on the high side, the drain electrode 11 and the n-drain region 6 may be common. The p isolation region 5 is arranged so as to surround the n drain region 6, and the p low concentration region 2 is formed on the surface portion of the n epi layer 2a between the n drain region 6 and the p isolation region 5.
0 is arranged. The difference from the first embodiment is that the p low-concentration region 20 does not continuously surround the surroundings, but is intermittently provided in consideration of how the potential of the wiring located in the upper part actually changes. It is a point. A contact hole 13g for connecting the drain electrode 11 to the n drain region 6 and the field plate A15 (not shown)
Also serves as the contact holes 13c and 13d in FIG. Similarly, the contact hole 13h is 13a,
Also serves as 13b.

Initially, the continuous low p-concentration region 20 was provided as in Example 1, but this caused the following problems.
When the average isolation breakdown voltage was measured for the gate wiring 14 and the source electrode 10 of the upper and lower two n-ch MOSFETs at the L level or the H level, 19
The same results as in Example 1 could be obtained at 5 V and 187 V. However, in reality, two upper and lower n-ch MOSFETs are used.
Have different switching states. 1 n-ch MOSFET
The gate wiring and the source electrode inside are set to the same level, and the isolation withstand voltage is measured at the upper and lower n-ch MOSFETs with different L level / H level.
It may be about 6V lower than V. This is because even if two n-ch MOSFETs are arranged adjacent to each other, if the p isolation region 5 is provided in each n-ch MOSFET, the influence of the adjacent element can be completely cut off and the breakdown voltage is reduced. Does not occur, the p low concentration region 2 made up of two n-ch MOSFETs
It is considered that the potentials in 0 interfere with each other.

Therefore, as shown in FIG. 4, in order to suppress the mutual interference of the potentials in the p low concentration region 20, a separated structure can prevent the separation breakdown voltage from decreasing. At this time, it is effective to separate the p low concentration region 20 below the drain electrode 11 having a high potential and the p low concentration region 20 below the source electrode 10 and the gate wiring 14 having a low potential. Further, the drain electrode 11, the source electrode 10 and the p low concentration region 20 under the gate wiring may be separated from each other. In this case, p
The interval between the low-concentration regions 20 is also important, and it is preferable that the part of the n-epi layer 2a having the lowest impurity concentration share the part in which the potential greatly changes. As a result of trial manufacture, good results were obtained when this interval was 5 μm. By doing so, when the isolation withstand voltage was measured for the upper and lower n-ch MOSFETs with different L level and H level, the isolation withstand voltage was 185 V, and the isolation withstand voltage improved from the previous time. As can be seen from the second embodiment, the p isolation region 5 is formed even when a plurality of devices are integrated.
The area occupied by the semiconductor chip can be significantly reduced, and the semiconductor chip can be downsized.

In the first and second embodiments, the lateral withstand voltage element of 100 to 200 V is described with reference to the isolation withstand voltage design, but the present invention can be applied to an element with higher withstand voltage. In such a case, the width of the breakdown voltage design portion may exceed 100 μm. Therefore,
An application in which a plurality of p low-concentration regions 20 are arranged along the lower portion of the upper wiring is also conceivable. At this time, the design points to keep in mind are (1) depending on the fluctuation range of the potential of the upper wiring (in the case of another power supply, it may be higher than the designed breakdown voltage, or the potential may be inverted between plus and minus). To determine the width, interval and number of the p low concentration regions 20. (2) A field plate having the same potential as the p low concentration region is arranged at a necessary position to avoid the deterioration phenomenon. This is different from the design policy in which the electric field is always high at one edge of the p low-concentration region 20, as in the guard ring design used in the conventional vertical element. Further, the arrangement is not limited to the design of the isolation region such as the p isolation region 5, the n epi layer 2a, and the p low concentration region 20, and even if the device is placed in a three-dimensional device having a laminated structure in the future, the placement is located above the breakdown voltage structure. In such a case, the development and application of partially providing a p low concentration region (like a zakkadan) can be inferred.

[0033]

According to the present invention, the field plates A and B mainly serve to prevent the potential on the semiconductor surface from largely changing, thereby improving reliability.
Further, in the p low-concentration region which is the floating potential, mainly the function of automatically relieving the electric field concentration is taken to reduce the manufacturing variations. In addition, by combining these, it becomes possible to reduce the occupied width (area) of the breakdown voltage structure portion.

When manufacturing the elements having these configurations, it is possible to supply an inexpensive high breakdown voltage lateral semiconductor device because it is not necessary to introduce a new process and can be dealt with only by changing the design.

[Brief description of drawings]

FIG. 1 is a main part configuration diagram of a high breakdown voltage lateral semiconductor device according to a first embodiment of the present invention, in which (a) is a plan view and (b) is a sectional view taken along line AA of (a).

FIG. 2 is a diagram showing a calculation example of a breakdown voltage design optimized by the present invention.

FIG. 3 is a diagram showing a characteristic example improved by the present invention.

FIG. 4 is a plan view of a high breakdown voltage lateral semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a general high breakdown voltage lateral semiconductor device.

6A and 6B are diagrams showing a problematic portion in a conventional high withstand voltage lateral semiconductor device, in which FIG. 6A is a plan view and FIG. 6B is A in FIG.
-Cross section taken along line A

FIG. 7 is a sectional view showing another breakdown voltage structure according to the prior art.

FIG. 8 is a basic model used for breakdown voltage calculation, (a) is a sectional view, (b) is an electron concentration distribution diagram, and (c) is a hole concentration distribution diagram.

FIG. 9 is a calculation example of a withstand voltage design in the case where there is no field plate in the conventional technique, (a) and (b) show VGL = 0V, (c) and (d) show VGL = VdH.

FIG. 10 is a calculation example of a breakdown voltage design when a field plate is optimized by a conventional technique, (a) is a potential distribution diagram when VGL = 0V, and (b) is a potential distribution diagram when VGL = VdH.

FIG. 11 is a diagram showing a problem caused by the conventional technique, and is a relational diagram of the field plate length (L _FPI ) and the isolation breakdown voltage (VdH).

[Explanation of symbols]

 1 p substrate 2 n epi layer 2a n epi layer 3 p buried layer 4 n buried layer 5 p isolation region 6 n drain region 7 p well region 8 n source region 9 gate electrode 10 source electrode 11 drain electrode 12 ground electrode 13a contact Hole 13b Contact hole 13c Contact hole 13d Contact hole 13e Contact hole 13f Contact hole 13g Contact hole 13g Contact hole 14 Gate wiring 15 Field plate A (drain side) 16 LOCOS oxide film 17 Interlayer insulation film 18 p Offset area 19 Field plate B ( Ground side) 20p Low concentration area

Claims (4)

[Claims] 1. A first semiconductor layer of the first conductivity type has a first surface on a first main surface thereof.
A first region of the first conductivity type and a second region of a higher concentration than the semiconductor layer;
Second regions of the conductivity type are formed with a predetermined interval, and second semiconductor layers of the second conductivity type are collectively stacked on the respective surfaces of the first semiconductor layer, the first region and the second region. A first conductivity type isolation region reaching the first region from the surface of the semiconductor layer and a second conductivity type third region reaching the second region are formed, and surrounded by the first semiconductor layer, the isolation region and the third region. In a lateral semiconductor device in which MOS devices are formed in the second region, the third region and the fifth region of the junction separation substrate in which the fifth region surrounded by the fourth region, the second region and the third region is formed, the junction separation is performed. An insulating film is selectively formed on the surface of the substrate, a plurality of metal wirings are formed on the surface of the insulating film on the fourth region, and the first conductive film and the first conductive film are formed in the insulating film on the isolation region and the third region. Two conductive films are embedded respectively, and the first
The conductive film penetrates the insulating film and is selectively fixed to the isolation region, the second conductive film penetrates the insulating film and is selectively fixed to the third region, and at least the fourth region under the metal wiring. A high withstand voltage lateral semiconductor device, wherein a sixth region of the first conductivity type is formed on the surface layer of. 2. The high breakdown voltage lateral semiconductor device according to claim 1, wherein the sixth region is formed over the entire circumference of the fourth region. 3. The high breakdown voltage lateral semiconductor device according to claim 1, wherein the sixth region is formed separately. 4. The high breakdown voltage lateral semiconductor device according to claim 1, wherein the potential of the sixth region is a floating potential.