JPH09226585A - Speed check device - Google Patents

Abstract

(57) [Abstract] [Problem] To enable running suitable for the speed range of train speed,
It is intended to surely absorb a large error in the speed input in the high speed range and reduce the train interval in the low speed range. SOLUTION: Train speeds 5 and 6 and speed limit patterns 3,
4 is compared and compared, and when the train speed exceeds the speed limit pattern, in the speed verification device in which the systems 1 and 2 that output the brake commands 23 and 24 to decelerate or stop the train are configured in multiple, When the brake operation of the system is detected and the speed limit pattern of the own system is lowered by a predetermined value (brake sync width), and the brake output is synchronized, the brake sync width that reduces the speed limit pattern is set according to the train speed, that is, , The brake synchronization width is multiplied by the proportional coefficient to the speed limit pattern, and the speed check delay compensation is added to this. When the train speed exceeds the speed limit pattern, the speed limit pattern is limited to the calculated brake synchronization width. It is characterized by lowering.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed checking device which is composed of a multiple system and synchronizes brake outputs.

[0002]

2. Description of the Related Art A speed check device such as an automatic train control device (ATC) generates a speed limit pattern from a speed limit signal, compares the speed limit pattern with a train speed, and checks that the train speed exceeds the speed limit pattern. When this occurs, it has a function of detecting this and outputting a brake to safely run or stop the train. Conventionally, since the speed check device is concerned with the safety of trains, it is necessary to surely detect the occurrence of a failure, and it is configured by a multiple system. In the failure detection by the multiple system, the output of each system is compared and the abnormality of the device is detected.

As shown in FIG. 4 (a), the conventional speed checking device has train speeds Vt1 input to the system 1 and the system 2 (explained as a double system) even when the device is normal.
When Vt2 is a value close to the speed limit pattern Vp, the train speed Vt1 exceeds the speed limit pattern Vp and brake output 23 occurs in one system 1 due to an error in the train speed input, but the train speed in the other system 2 Vt2 may fall below the speed limit Vp, and the brake 24 may not be output. In other words, the other system 2 outputs the brake output 24 when the train speed Vt2 exceeds the speed limit Vp,
There is a discrepancy in the brake output over time. In order to prevent such failure detection due to the discrepancy of the brake outputs, as shown in FIG. 4B, the systems 1 and 2 input the brake outputs of the other systems to each other, and the system 2 which does not output the brake, The brake output of the system 1 is detected by the brake synchronization signal 25, and the speed limit pattern Vp is set to a predetermined brake synchronization width ΔV.
By lowering it, the system 2 also performs the brake output 24 to synchronize the outputs so that the outputs do not become inconsistent. Similarly, when the brake is released, as shown in FIG. 4C, when the train speed Vt2 is lower than the release pattern Vr in the system 2, when the brake is released, the system 1 is activated by the brake synchronization signal 26.
Detects the brake release of the system 2 and raises the release pattern Vr to the brake synchronization width ΔV to release the brake and synchronize the output. A synchronization system of this type of multiple system brake control is disclosed in Japanese Patent Application Laid-Open No. 52-77313.

[0004]

Since a recent vehicle is equipped with vehicle information equipment and a plurality of maintenance devices, a large number of speed signals are used. Therefore, the speed input of the speed checking device also has different windings and different speed inputs. The case where it is taken from the axle is becoming inevitable. This is because train speed Vt
This is a factor that the error of 1 and Vt2 becomes large. Since this error is proportional to the speed, this effect is large in trains that run in the high speed range such as the Shinkansen. In this case, it is necessary to increase the brake output synchronization width ΔV to absorb a speed input error. Therefore, the conventional speed checking device generally gives the brake synchronization width ΔV as a large constant value that absorbs the speed error in the high speed range. However, due to the higher density of trains, there is a demand to reduce the train interval by making the speed as close as possible to the speed limit even in the low speed range during running or when entering a station. In this case, if the brake synchronization width ΔV is large, there is a problem that the brake of the speed checking device acts at a speed close to the speed limit, the train interval cannot be reduced, and the demand cannot be satisfied.

An object of the present invention is to enable speed running suitable for the speed range of the train speed, to reliably absorb a large error in the speed input in the high speed range, and to suitably check the train interval in the low speed range. To provide a device.

[0006]

[Means for Solving the Problems] The above problem is to detect a braking operation of another system at the time of a braking operation and reduce the speed limit pattern of the own system by a predetermined value (brake synchronization width) to synchronize the brake output. Set the brake synchronization width that lowers the speed pattern according to the train speed, that is, multiply the brake synchronization width by the proportional coefficient to the speed limit pattern, and add it to the speed check delay compensation to calculate the train speed. When the limit pattern is exceeded, it is solved by lowering the limit speed pattern by the calculated brake synchronization width. In addition, when the braking operation of another system is detected during braking operation, the speed limit pattern of the own system is reduced by a predetermined value (brake synchronization width), and when synchronizing the brake output, the maximum train speed and maximum speed of the system configured in multiple This can be solved by obtaining the speed input error range from the error, and using this speed input error range as the brake synchronization width to lower the speed limit pattern of the other system. Further, when the brake is released during the braking operation in the low speed range of the train, it is solved by setting the difference between the speed limit pattern and the brake release pattern as the brake synchronization width.

According to the present invention, when the train speed of one system exceeds the speed limit pattern of the other system in the multiple system in the speed checking device, the train speed of this system is the maximum value of the speed input of each system. Can be considered to be. Here, the brake synchronization width is calculated by multiplying the speed limit pattern by the proportional coefficient and adding the delay compensation amount for speed check to this, so the value obtained by subtracting the brake synchronization width from the speed limit pattern is the minimum train speed of each system. Less than the value. Therefore, it can be said that the train speed of each system is in the range of the value obtained by subtracting the speed limit pattern from the train speed.
Therefore, when the train speed is in the high speed range, even if the relative error of the train speed of each system becomes large, it is within the range of the brake synchronization width, so that the brake synchronization of each system can be reliably performed. Also, in the low speed range, the value of the brake synchronization width decreases in proportion to the train speed, so while ensuring the brake synchronization,
The brake relaxation pattern can be brought close to the speed limit pattern. In this way, traveling suitable for the high speed region or low speed region of the train becomes possible.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a speed checking device showing an embodiment of the present invention. FIG. 1 shows a dual system of a speed checking device, the system 1 is composed of a pattern generator 3, a speed input circuit 5 and a brake output comparator 7, and the system 2 is composed of a pattern generator 4 and a speed. It comprises an input circuit 6 and a brake output comparator 8. The pattern generators 3 and 4 are ATs
Train speed input 1 from speed generators 9 and 10 that input the ATC signal 14 from the C signal receiver 11 and detect the speed of the train
5 and 16 are received, and speed limit patterns 17 and 1 are received, respectively.
8. The brake relieving patterns 19 and 20 are generated, and the brake synchronizing signals 25 and 26 are input from other systems, respectively. The speed input circuits 5 and 6 receive the train speed inputs 15 and 16 from the speed generators 9 and 10 and receive the train speeds 21 and 2, respectively.
2 is output. The brake output comparators 7 and 8 have the speed limit patterns 17 and 18 and the brake relieving patterns 19 and 2, respectively.
0, train speed 21, 22 to system brake output 23, 24
Is output. The mismatch detection comparator 12 compares the system brake outputs 23 and 24 of the system 1 and the system 2 and outputs a failure detection 28. The brake output logic unit 13 uses the system brake output 2
3 and 24 are input and a brake command 27 is output.

Next, the principle of determining the brake synchronization width ΔV of the present invention will be described. In the present embodiment, the brake synchronization width ΔV is a value given by (Equation 1) proportional to the speed limit pattern Vp. ΔV = A × Vp + α (Equation 1) Here, A is a wheel diameter error rate and is given by (Equation 2). Also, α is a delay compensation amount for speed check. In the case of a system that has a time element for speed check, in order to achieve the exact brake synchronization, the delay check amount α for speed check is added as in (Equation 1). A = ΔD ÷ D (Equation 2) Here, D is the average wheel diameter of the axle on which the speed generator is attached, and when the speed generator is taken from n axles, the respective wheel diameters are Let D1, D2, ..., Dn be given by (Equation 3). D = (D1 + D2 + ... + Dn) / n (Equation 3) Further, ΔD is a wheel diameter relative error (management accuracy) of the axle on which the speed generator is attached, and D1, D2, ..., Dn
It is the difference between the maximum and minimum values. ΔD = (maximum value of D1, D2, ..., Dn)-(minimum value of D1, D2, ..., Dn) (Equation 4) These (Equation 1), (Equation 2), (Equation 3), (Equation 3) 4) is
This is realized by the internal processing of the pattern generators 3 and 4, and the brake synchronization width ΔV is obtained.

The operation of this embodiment will be described below with reference to FIGS. FIG. 2 shows the input error of the train speed Vt in the high speed region and the low speed region at the time of brake output and the brake synchronization width ΔV.
The relationship (a) and the braking operation (b) at the time of speed check in the brake synchronization width ΔV are shown. Here, it is assumed that the train speed 21 (Vt1) of the system 1 is the maximum value among the train speeds of the respective systems due to the relative error of the wheel diameters, and the α term of (Equation 1) is 0. By substituting the train speed Vt for the speed limit pattern Vp in (Equation 1), the maximum speed error ΔVe is obtained. A value obtained by subtracting ΔVe from Vt1 which is the maximum value of the train speed is the minimum value of the train speed. Therefore, in FIG. 2A, if the vertical axis represents train speed input and the horizontal axis represents train speed, 21 (Vt1) and Vt1−ΔV
The hatched portion in FIG. 2 (a) sandwiched by e is the velocity input error range 30. In addition, in FIG.
With the vertical axis as the speed limit pattern and the horizontal axis as the train speed, the brake synchronization width ΔV of the speed limit pattern 31Vph in the high speed range and the speed limit pattern 32Vpl in the low speed range is calculated by (Equation 1).
In the low speed range, h is 34ΔVl. In each speed range,
31Vph and Vph-ΔVh, 32Vp1 and V, respectively
The range sandwiched by p1-ΔV1 is the speed input error range 30
Therefore, as shown in FIG. 1B, the train speed 22 (Vt2) of the other system is equal to the brake synchronization width 33Δ.
It exists in the range of Vh and 34ΔVl.

Therefore, in the high speed range of FIG. 2 (b), the train speed 21 (Vt) of system 1 which is the maximum train speed of each system
1) is detected by the speed generator 9, and the speed input circuit 5
Is input to the brake output comparator 7 via
Speed limit pattern (17) 31V generated from the pattern generator 3 based on the ATC signal 14 of the C signal receiver 11
When ph is input to the brake output comparator 7, the two are compared and the train speed 21 (Vt1) is the speed limit pattern 3
When it exceeds 1 Vph, the brake output 23 of the system 1 becomes a brake. At the same time, the brake synchronization signal 25 from system 1 is sent to other system 2
Input to the pattern generator 4 of No. 2 and the speed limit pattern generated by the pattern generator 4 of the other system 2 is applied to the brake synchronization width 3
Decrease by 3ΔVh. In this case, train speed of other system 22
Since (Vt2) exists within the range of the brake synchronization width 33ΔVh, the train speed of another system 22 (Vt2)
2) exceeds Vph-ΔVh, and brake output 24 is performed. In this way, since each system outputs the brakes at the same time, the brake output 27 is output from the brake output logic unit 13, and the speed check can be performed without causing the output inconsistency. Here, for some reason, both systems 1, 2
When the brake outputs 23 and 24 of No. 2 do not match, the mismatch detection comparator 12 outputs a failure detection signal 28. Further, in the low speed range of FIG. 2B, as in the high speed range, the train speed 21 of the system 1 which is the maximum value among the train speeds of the respective systems.
When (Vt1) exceeds the speed limit pattern 32Vpl and the brake output 23 of the system 1 becomes a brake, the speed limit pattern 32Vpl of the other system 2 is simultaneously set to the brake synchronization width 34.
Decrease by (ΔVl). In this case, train speed of other system 22
Since (Vt2) exists within the range of this brake synchronization width 34ΔVh, the train speed 22 (Vt
2) exceeds Vpl-ΔVl, and brake output 24 is performed. In this way, since each system outputs the brakes at the same time, the speed check can be performed without causing the output inconsistency.

As described above, in this embodiment, since the brake synchronization width ΔV is proportional to the train speed, even if the relative error of the train speed of each system becomes large when the train speed is in the high speed range, each system Since the speed limit pattern is within the range of the brake synchronization width ΔV, the brake synchronization of each system can be reliably performed, and in the low train speed range, the value of ΔV decreases in proportion to the train speed. The brake synchronization pattern can be brought close to the speed limit pattern in the low speed range, and while ensuring the brake synchronization, the train interval can be reduced during low speed running of the train, and the train density can be increased. In this way, according to the present embodiment, it is possible to travel in a high speed range or a low speed range of the train.

FIG. 3 shows the braking operation at the time of speed checking in the low speed range when the brake is released. Here, conventionally, since the brake synchronization width is set to the speed limit pattern 35Vp regardless of the speed range, when the difference is 42ΔV between the speed limit pattern 35Vp and the brake relieving pattern 37Vrl. , When the train speed Vt exceeds the speed limit pattern 35Vp, the brake 41 does not relax until it falls below the brake relief pattern 37Vrl. Therefore, the train speed 39Vt fluctuates greatly and the train speed 3
It becomes difficult to drive 9Vt close to the speed limit pattern 35Vp. For this reason, conventionally, in the low-speed range at the time of entering a station, the train interval cannot be reduced to increase the density of the train, and the riding comfort is also deteriorated.

In this embodiment, the speed limit pattern 35V
Assuming that the difference between p and the brake relieving pattern 37Vrl is the brake synchronization width 43ΔV, the brake synchronization width 43ΔV is
Since it decreases in proportion to the train speed Vt from (Equation 1),
The brake release pattern 36Vr1 shown in FIG. 3 is obtained. Therefore, brake relaxation pattern (19) 36Vr1
Is the brake output comparator 7 from the pattern generator 3 of the system 1.
On the other hand, the train speed (5) Vt from the speed input circuit 5 is input to the brake output comparator 7, and both are compared, and the train speed (5) Vt falls below the brake relaxation pattern (19) 36 Vrl. And the brake output comparator 7
The brake output 23 is brake released 41 as shown in FIG. As a result, the train runs at a train speed of 38 Vt, which is closer to the speed limit pattern 35 Vp as compared with the conventional brake relief pattern 37 Vrl described above. At the same time, the brake synchronization signal 25 of the system 1 is input to the pattern generator 4 of the other system 2, and the system 2 detects the brake relaxation of the system 1 by the brake synchronization signal 25 so as to relax the brake and synchronize the output. I have to.

As a result, in the case of the present embodiment, the speed difference from the brake output to the remission can be made smaller than in the conventional case, and the train can be operated by approaching the speed limit pattern accordingly, and the low speed range when entering the station Then, the train interval can be shortened to increase the density of trains, and the ride comfort is also improved. Further, when comparing the difference between the conventional and the present embodiment with respect to the relieving from the brake output, this difference is the brake synchronization width, and therefore corresponds to the ratio of the maximum speed of the train and the speed limit pattern 35Vp at the low speed. This embodiment is more effective for trains with the highest maximum speed such as the Shinkansen.

[0016]

As described above, according to the present invention,
Since the speed verification by the brake synchronization width corresponding to the train speed can be realized, even if the relative error of the speed input of each system becomes large in the high train speed range, the speed limit pattern of each system is within the range of the brake synchronization width. Yes, the brake synchronization of each system can be performed reliably during speed check, and in the low speed range of the train speed, the brake synchronization width decreases in proportion to the train speed. You can get closer to the pattern, reduce the train interval during low-speed running of the train while surely performing brake synchronization,
Higher train density can be achieved. In this way,
According to the present embodiment, it is possible to travel in a high speed range or a low speed range of a train. Further, according to the present embodiment, in the low speed range of the train speed, since the brake synchronization width becomes smaller in proportion to the train speed, while reliably performing the brake synchronization,
Since the brake relieving pattern can be brought close to the speed limit pattern, as a result, it is possible to run the train closer to the speed limit, and in particular, to increase the density of high-speed trains and train operation when entering a station. In addition, the ride comfort can be improved.

[Brief description of drawings]

FIG. 1 shows a speed checking device according to an embodiment of the present invention.

FIG. 2 shows a relationship between a train speed input error and a brake synchronization width (a) and a brake operation (b).

FIG. 3 shows a braking operation during speed check in a low speed range when the brake is released.

FIG. 4 is an explanatory view of a brake synchronization system of a conventional technique.

[Explanation of symbols]

 1 System of speed checking device 1 2 System of speed checking device 2 3 4 Pattern generator 5 6 Speed input circuit 7 8 Brake output comparator 9 10 Speed generator 11 ATC signal receiver 12 Mismatch detection comparator 13 Brake output logic

Claims (5)

[Claims] 1. A speed checker comprising a system in which a train speed is compared with a speed limit pattern, and when a train speed exceeds the speed limit pattern, a train is output to output a brake command to decelerate or stop the train. When the brake operation of another system is detected during operation, the speed limit pattern of the own system is reduced by a specified value (brake synchronization width), and when synchronizing the brake output, the brake synchronization width that reduces the speed limit pattern is set according to the train speed. A speed check device characterized by: 2. A speed checker comprising a system in which a train speed is compared with a speed limit pattern, and when the train speed exceeds the speed limit pattern, a train is output to output a brake command to decelerate or stop the train. When the brake operation of another system is detected during operation, the speed limit pattern of the own system is lowered by a predetermined value (brake synchronization width), and when synchronizing the brake output, the speed is determined from the maximum train speed and the maximum speed error of the multiplex system. A speed checking device characterized in that an input error range is obtained, and the speed input error range is used as a brake synchronization width to lower a speed limit pattern of another system. 3. A speed check device comprising a system in which a train speed is compared with a speed limit pattern, and when the train speed exceeds the speed limit pattern, a train is output to output a brake command to decelerate or stop the train. When the brake operation of another system is detected during operation, the speed limit pattern of the own system is lowered by a specified value (brake sync width), and when synchronizing the brake output, the speed limit pattern is lowered. The brake sync width is small at low speed and at high speed. A speed check device characterized by increasing the size. 4. The brake synchronization width according to claim 1, wherein when the brake is released during braking operation in a low speed range of a train, the difference between the speed limit pattern and the brake release pattern is used as the brake synchronization width. Speed check device. 5. The speed checking device according to claim 1, wherein the brake synchronization width is obtained by the following equation. ΔV = A × Vp + α where Vp: speed limit pattern, A: wheel diameter error rate,
α: Compensation for speed check delay