JPH09252240A - Multiplexer - Google Patents

Abstract

(57) Abstract: A multiplexer capable of significantly reducing the chip size of a driver IC of a liquid crystal display device. SOLUTION: PFET switch units 3-1 to 3-8 by decoding the upper 3 bits by a decoder 1 of 8-bit digital data input from the outside.
And one of the NFET switch units 4-1 to 4-8
Select the FET switch unit and NFET switch unit. Then, the selected PFET switch unit and NFET switch unit output one of the 32 kinds of gradation voltages input to each of them to the liquid crystal cell based on the lower 5 bits of the 8-bit digital data. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer that outputs one input signal in accordance with a selection signal from a plurality of input signals, and more particularly to a multiplexer suitable for use in a drive circuit of a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, a TFT (Thin Film Transistor) is one of the driving methods for liquid crystal display devices capable of displaying gradation.
There is a drive system. The TFT driving method has the characteristics of high gradation display quality, excellent screen brightness and contrast, and high display image quality. It is also excellent in performance other than image quality such as fast response speed and wide viewing angle.

The principle of this TFT driving system will be described with reference to FIG. In this figure, reference numeral 50 is a thin film transistor, and when a voltage is input from the outside through a source line 51 and a voltage is applied to the gate line 52, the source line 51
The voltage input to is applied to the liquid crystal layer 53. As a result, the liquid crystal molecules of the liquid crystal layer 53 change the angle and allow light from a backlight (not shown) to pass through. When performing gradation display, the voltage input to the source line 51 is changed to change the liquid crystal layer 5
3 by controlling the angle of the liquid crystal molecules.

There are analog type and digital type in the above-mentioned gradation control method, but at present, in the liquid crystal display device for OA (office automation) equipment such as a notebook type personal computer, digital gradation control is often performed. It is being appreciated. In this digital gradation control, different specific gradation voltages are prepared in advance by the number of gradations to be controlled, and one specific gradation voltage is selected from among them by a selection signal and output to the source line of the thin film transistor. It is done by doing.

A multiplexer is usually used as the gradation voltage selecting means. here,
FIG. 5 shows the configuration of a conventional multiplexer. The multiplexer shown in FIG. 5 is for controlling one liquid crystal cell with 256 gradations, and the voltage VEE has 25 resistance values R.
The gradation voltage V1 obtained by dividing the voltage into 256 levels by the resistance array 110 composed of 6 resistors and dividing the voltage
One of V256 to V256 is selected and output according to 8-bit digital data input from the outside.

Reference numerals 101 to 108 denote a latch circuit and a level shift circuit, which level-shift each bit signal of 8-bit digital data to be input into a bit signal of a predetermined voltage system so that each input bit signal has the same phase. The signal and its inverted signal are output, and the state of each output bit signal is held according to the clock signal CLK. Here, when the clock signal CLK is at a high level (hereinafter referred to as “1”),
The input bit signals DL0 to DL7 (DL0 is the least significant bit) represented by voltages of 0V (“0”) and 3V (“1”) are set to 0V.
(0) and the output bit signals DH0 to DH7 in phase with the input bit signal by level-shifting to the digital signal represented by the voltage of 5V ("1") and the inverted output bit signal * DH0 ~ * DH7 is output. Further, when the clock signal CLK is at a low level (hereinafter referred to as “0”),
The state of each output bit signal immediately before becoming "0" is held.

Numerals 109-1 to 109-256 are switch sections, which correspond to the input bit signals DL0 to DL7, respectively.
Two N-channel field effect transistors (hereinafter NFET
, And eight P-channel field effect transistors (hereinafter referred to as PFETs). Further, the gradation voltages V1 to V256 obtained by dividing the voltage VEE into 256 levels by the resistor array 110 are input to the switch units 109-1 to 109-256, respectively, and the outputs of the switch units are connected to each other. And is connected to a liquid crystal cell (not shown). Further, one of the gates of the FETs is selected depending on the value of the input digital data.
Only one switch section is properly connected to each output of the latch circuit and the level shift circuits 101 to 108 so that all the FETs are turned on.

For example, in the case of the switch section 109-1, the in-phase output bit signals DH0 to D are respectively applied to the gates of the PFETs.
H7 is input, and the inverted output bit signals * DH0 to * DH7 are input to the gates of the respective NFETs. As a result, when all the input bit signals DL0 to DL7 input to the latch circuits and level shift circuits 101 to 108 are “0”, the switch unit 109-1 turns on all the FETs and inputs the gradation voltage. V1 is output to the liquid crystal cell.

In the case of the switch unit 109-2, the in-phase output bit signal DH0 is input only to the gate of the NFET corresponding to the input bit signal DL0, and the inverted output bit signals * DH1 to * DH7 are input to the gates of the other NFETs. Has been entered. For PFET, input bit signal DL0
The inverted output bit signal * DH0 is input only to the gates of the PFETs corresponding to, and the in-phase output bit signals DH1 to DH7 are input to the gates of the other PFETs. As a result, the switch unit 109-2 causes the input bit signal D input to the latch circuit and the level shift circuits 101 to 108.
When only DL0 of L0 to DL7 is "1", all the FETs are turned on and the inputted gradation voltage V2 is output to the liquid crystal cell.

As described above, the multiplexer shown in FIG. 5 decodes 8-bit digital data input to the latch circuits and level shift circuits 101 to 108, and based on the result, one of the grayscale voltages V1 to V256 is decoded. Is selected and output to the liquid crystal cell to perform 256 gradation control.

When the multiplexer as described above is used in a driving circuit of a liquid crystal display device, it is necessary to provide the same number of source lines as the thin film transistors arranged in the liquid crystal display device. For example, since three multiplexers corresponding to each of the three primary colors are required per pixel, for example, VGA (video graphics arra)
In the case of y), 3 × 640 = 1920 multiplexers are required. A driving circuit for a liquid crystal display device including a large number of multiplexers is usually a C-MOS (compleme
The IC chip is mounted on a lead frame and then sealed with resin, mounted on a TAB tape, or directly mounted on a glass plate of a liquid crystal display device. , Used as a driver IC. Then, as shown in FIG. 6, the driver IC 115 generally includes the liquid crystal display device main body 1
In the frame portion of 16 (hatched portion in the figure), X in the figure
It is mounted in a line in the direction.

[0012]

By the way, today, the miniaturization of the liquid crystal display device main body is strongly desired in the portable electronic equipment represented by the notebook personal computer. In order to meet this demand, the length of the frame portion of the liquid crystal display device main body 116 shown in FIG. 6 in the Y direction is shortened as much as possible, and the width of the driver IC 115 (the length in the X direction) of the liquid crystal display portion 117 is reduced. It is necessary to make the width of the frame portion of the liquid crystal display device main body 116 as narrow as possible by arranging the liquid crystal display device without arranging it significantly.

In particular, in order to shorten the length of the frame portion in the Y direction, the size of the driver IC chip corresponding to the Y direction must be shortened as much as possible, and the drive circuit of the liquid crystal display device is integrated into an IC. For this, various contrivances have been made in the layout. For example, in the case of the multiplexer shown in FIG. 5, since a large number of multiplexers are required for one liquid crystal display device as described above, the multiplexers corresponding to each liquid crystal cell should be arranged in the X direction in the IC chip. become. In addition, it is convenient that the input and output of the multiplexer are arranged in the Y direction in terms of layout. For this reason, in the case of the multiplexer of FIG. 5, the horizontal direction corresponds to the X direction and the vertical direction corresponds to the Y direction in the figure.

Here, since the multiplexer of FIG. 5 has two rows of FETs in the Y direction for each switch section, the length in the Y direction becomes long. Further, if such a multiplexer is integrated into an IC, the p-type well and the n-type well are complicated, and the layout efficiency is reduced. For the purpose of improving these, for example, it is conceivable to make the switch unit a circuit as shown in FIG.

The switch units 120-1 to 120 shown in FIG.
-256 is one in which eight PFETs and eight NFETs are arranged in one line, and 1 is set in accordance with the value of 8-bit digital data, like the switch unit of the multiplexer shown in FIG.
Each F is set so that all FETs are turned on only in one switch section.
The gate of ET has a latch circuit and a level shift circuit 101.
To 108 outputs. With the switch unit having such a configuration, one FET row is provided for each switch unit.
Since it is arranged in rows, the length in the Y direction can be expected to be significantly shortened as compared with the multiplexer shown in FIG.

However, when a multiplexer is formed by using the switch section shown in FIG. 7, the length of the IC chip corresponding to the X direction is certainly longer than that in FIG. Further, the in-phase output bit signal DH0 output from the latch circuit and the level shift circuits 101 to 108
.About.DH7 and the inverted output bit signals * DH0 to * DH7 are also doubled in wiring, so that the area of the entire IC chip cannot be reduced.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a multiplexer capable of significantly reducing the chip size of a driver IC of a liquid crystal display device.

[0018]

According to the first aspect of the present invention,
Of the 2 ^m types of input signals with different voltage values,
In a multiplexer that selects and outputs one input signal according to m-bit digital data, a decoder circuit that decodes n (1 <n <m) -bit digital data of the m-bit digital data, and 2 ^m types Input signals of 2 ^{m− n} each are input to each of the 2 ⁿ selection circuits, and any one of the selection circuits selected according to the decoding result of the decoder circuit is selected from the m-bit digital data. ²ⁿ selection circuits for selecting one of the 2 ^mn types of input signals input based on ^mn bit data, the decoder circuit and the 2 ⁿ The multiplexer is characterized in that the individual selection circuits are formed on a semiconductor substrate having a plurality of wiring layers.

According to a second aspect of the present invention, in the multiplexer according to the first aspect, the wiring provided between the decoder circuit and the 2 ⁿ selection circuits and each of the 2 ⁿ selection circuits are input. Mn-bit data line
It is characterized in that each of the plurality of wiring layers is formed in a different wiring layer.

[0020] According to a third aspect of the invention, in the multiplexer according to claim 2, the wiring provided between said decoder circuit wherein the 2 ⁿ selection circuits, each of said 2 ⁿ pieces of selection circuit The input mn-bit data line has a section formed in parallel with and overlapping with each other, and in the section, the decoder circuit and the 2
The width of the wiring provided between the ⁿ selection circuits and the mn
It is formed by the value of n that minimizes the difference between the bit and the width of the data line.

The invention according to claim 4 is the invention according to claims 1 to 3.
In the multiplexer according to any one of the items,
Each of the 2 ⁿ selection circuits is configured by connecting a plurality of N-channel MOSFETs and a plurality of P-channel MOSFETs in series.

[0022] The invention according to claim 5 is the invention according to claims 1 to 3.
In the multiplexer according to any one of the items,
Each of the 2 ⁿ selection circuits is configured by only a P-channel MOSFET when the input voltage is equal to or higher than a predetermined voltage value, and is configured by only an N-channel MOSFET when the input voltage is equal to or lower than the predetermined voltage value. Is characterized by.

According to a sixth aspect of the present invention, in the multiplexer according to the fifth aspect, the predetermined voltage value is the ON resistance of the P-channel MOSFET and the N-channel MOSF.
It is characterized in that the ON resistance of ET has the same voltage value.

The invention according to claim 7 is the invention according to claims 1 to 3.
In the multiplexer according to any one of the items,
Each of the 2 ⁿ selection circuits uses only a P-channel MOSFET when the input voltage is equal to or higher than a first voltage value, and uses only an N-channel MOSFET when the input voltage is equal to or lower than a second voltage value. If the input voltage is less than the first voltage value and exceeds the second voltage value, the P-channel MO
It is characterized by being constituted by an SFET and an N-channel MOSFET.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are block diagrams showing the circuit configuration of the multiplexer in this embodiment. Similar to FIG. 5, this multiplexer selects one of the grayscale voltages obtained by dividing a predetermined voltage into 256 steps by a resistance array or the like based on 8-bit digital data input from the outside. , Is output to a liquid crystal cell (not shown).

In FIG. 1, reference numerals 101 to 108 denote conventionally known latch circuits and level shift circuits, which are 0 V when the clock signal CLK is "1".
Input bit signals DL0 to DL7 (DL0 is the least significant bit) represented by a voltage of "(0") and 3V ("1") are set to 0V.
Output bit signals DH0 to DH7 that are in phase with the input bit signal by level-shifting to a digital signal represented by (0) and 5V ("1"), and an inverted output bit signal * DH0 obtained by inverting them. ~ * DH7 is output. When the clock signal CLK is "0", the clock signal CLK is "0".
The state of each output signal immediately before is maintained.

Numerals 3-1 to 3-8 are PFET switch sections, and each PFET switch section has a gradation voltage V1 obtained by dividing a predetermined voltage into 256 stages by a resistor or the like, as in FIG. 32 types of gray scale voltages are input from V256 to V256. That is, as shown in the figure,
Grayscale voltages V1 to V32 are input to one end of each PFET row in the PFET switch unit 3-1.
The gradation voltages V32 (i-1) +1 to V32i are input to the switch unit 3-i (i is an integer from 2 to 8). In FIG. 1, the gradation voltages V1 to V256 are V1.
May be set as the minimum voltage, and the voltage may be increased in the order of V2, V3, ..., V256, or vice versa. Further, the gradation voltages V1 to V256 may be arbitrarily input regardless of the magnitude of the gradation voltage value.

Here, since all the PFET switch sections have the same configuration, the configuration of the PFET switch section will be described below by taking the PFET switch section 3-1 as an example. PFE
The T switch part is a PFE in which six PFETs are connected in series.
There are 32 T-rows, and the above-mentioned 3
Two kinds of gradation voltages are individually input. In addition, each P
Of the six PFETs in the FET row, the gates of the five PFETs have latch circuits and level shift circuits 101 to 1
5 low-order 5-bit digital data DL0 to
Depending on the value of DL4 (0000 to 11111), the in-phase output bit signals DH0 to DH4 or the inverted output bit signals * DH0 to * DH4 are appropriately set so that all five PFETs in any one FET row are turned ON. Has been entered.

On the other hand, the inversion selection signal * S1 (described later in detail) is input to the gate of the remaining one PFET in common to all PFET rows. As a result, when each inversion selection signal * S1 is "0", the PFETs to which the inversion selection signal is commonly input to the FET row are turned ON,
The PFET switch unit 3-1 is in the active state, that is, one of the 32 PFET strings in the PFET switch unit 3-1 is selected by the in-phase output bit signals DH0 to DH4 and the inverted output bit signals * DH0 to * DH4. PF
The grayscale voltage input to the ET column is ready to be output to the liquid crystal cell.

Further, other PFET switch units 3-2 to 3-3
As for −8, only the type of the inverted selection signal input to each is different, and the five PFETs in each PFET string are different.
Of the in-phase output bit signals DH0 to DH4 or the inverted output bit signals * DH0 to * DH4 input to the gate of the
This is the same as the T switch section 3-1.

Reference numerals 4-1 to 4-8 are NFET switch sections, and each NFET switch section is composed of 32 NFET rows with 6 NFETs connected in series as one NFET row. Also, PFET switch sections 3-1 to 3-
As in the case of 8, the gradation voltages V1 to V256 are input to the respective NFET rows, and the selection signals S1 to S8 are applied to the gates of one of the six NFETs constituting each NFET row.
Any one of the selection signals (described later in detail) is commonly input.

Then, the gates of the remaining five NFETs all have five FETs in one FET row depending on the values of the digital data DL0 to DL4 input to the latch circuits and level shift circuits 101 to 105. The in-phase output bit signals DH0 to DH4 or the inverted output bit signals * DH0 to * DH4 are appropriately input so that the PFET is turned on.

The above-mentioned PFET switch sections 3-1 to 3-
8 and NFET switch parts 4-1 to 4-8 are FETs to which the same voltage is input in the corresponding switch parts.
The columns are connected to each other, the FET columns are also connected to each other, and finally all the outputs of the respective switch parts are connected to one liquid crystal cell. The PFET switch unit and the NFET switch unit to which the same 32 kinds of gradation voltages are input are activated by the same selection signal, although there is a difference between positive logic and negative logic.

In the above structure, the selection circuit is a PFET.
Although both the switch and the NFET switch are provided, it is possible to configure only one of the FET switch rows depending on the value of the grayscale voltage of the grayscale voltages V1 to V256. That is, when the voltage value of the gradation voltage is equal to or higher than the predetermined voltage, the NFET switch is in a high impedance state, so that it is possible to operate only by the PFET switch, and conversely, when the voltage value of the gradation voltage is the predetermined voltage. At the following values, the PFET switch is in a high impedance state, and therefore it is possible to operate with only the NFET switch.

Further, if the above-mentioned predetermined voltage is technically limited, the voltage value of the grayscale voltage is equal to the ON resistance of the PFET and the NFE.
It is possible to limit the input voltage where the ON resistances of T match. That is, the ON resistance of the PFET increases as the voltage value of the gradation voltage decreases, and the ON resistance of the NFET increases as the voltage value of the gradation voltage increases.
If the ON resistance of the NFET and the ON resistance of the NFET are equal to or higher than the voltage, the PFET switch operates only to turn on the PFET.
NF is below the voltage at which the resistance and the ON resistance of NFET match
It is operated only by the ET switch.

As described above, if the selection circuit is composed of only one of the FET switch rows, the number of transistors can be reduced by half, and the chip size of the driver IC of the liquid crystal display device can be greatly reduced. It will be possible. As described above, if the selection circuit is configured by only one of the FET switch rows, the chip size can be significantly reduced, but the ON resistance of the PFET and the NFET are reduced.
In order to assure the switching operation of the FET switch in the vicinity of the voltage at which the ON resistances of 1 and 2 match, it is preferable that both the PFET and the NFET are provided near the voltage.

That is, according to the structure described in claim 7, when the input voltage is equal to or higher than the first voltage value, the selection circuit is constituted by only PFET, and when the input voltage is equal to or lower than the second voltage value, the selection circuit is selected. Is composed of NFETs only, and at a voltage value less than the first voltage value and exceeding the second voltage value, the selection circuit is composed of PFETs and NFETs.
The first voltage value may be an input voltage value when the ON resistance of the NFET becomes a resistance value that is considered to be substantially infinite. Specifically, for example, N at the lowest gradation voltage value may be used.
The input voltage value may be an ON resistance value that is 20 times the ON resistance value of the FET. Similarly, the second voltage value is, for example, PFE.
It may be an input voltage value when the ON resistance of T becomes a resistance value that is considered to be substantially infinite. Specifically, the ON resistance is 20 times the ON resistance value of the PFET at the lowest gradation voltage value. The value may be the input voltage value. By configuring the FET switch array in this way, it is possible to significantly reduce the chip size while ensuring a reliable switch operation.

Further, in FIG. 2, 1 is a decoder, which is a latch circuit and level shift circuits 106, 107,
High-order 3 bits in-phase output bit signals DH5, DH6, DH7 and inverted output bit signal * DH5,
* DH6, * DH7 are decoded and the result is selected signal S1
~ S8 is output to each of the NFET switch sections 4-1 to 4-8. Further, the logics of the selection signals S1 to S8 are inverted by the inverter group 2 and the inverted selection signals * S1 to * S8.
Is output to each of the PFET switch units 3-1 to 3-8. Here, the truth table of the decoder 1 is shown below.
That is, Table 1 is a truth table of a decoder that can be used as the decoder 1 of FIG.
H6 and DH5 signals and their inverted signals *
Selection signal S1 to DH7, * DH6, * DH5 signals
It shows how the value of S8 becomes.

[Table 1]

Next, the operation of the above multiplexer will be described. First, when digital data DL0 to DL8 are input to the latch circuits and level shift circuits 101 to 108, the latch circuits and level shift circuits 101 to 108 are input.
Outputs the in-phase output bit signals DH0 to DH7 and the inverted output bit signals * DH0 to * DH7 by boosting the input bit signals. Of these, the upper 3 bits of the in-phase output bit signals DH5 to DH7 and the inverted output bit signals * DH5 to * D
H7 is decoded by the decoder 1 and the result is output as selection signals S1 to S8.

The selection signals S1 ...
The S8 is input to the NFET switch sections 4-1 to 4-8, and also passes through the inverter group 2 to generate the inverted selection signals * S1 to * S8, which are respectively the PFET switch sections 3-1.
Input to 3-8. As a result, one set of PFET switch part and NFE to which the same 32 kinds of voltages are input are input.
The T switch section becomes active. Then, in the PFET switch unit and the NFET switch unit that are in the active state, any one of the FET rows is turned ON depending on the states of the in-phase output bit signals DH0 to DH4 and the inverted output bit signals * DH0 to * DH4, and the FET The voltage input to the column is output to the liquid crystal cell.

For example, when the clock signal CLK is "1", the digital data DH0 to DH7 input to the latch circuits and level shift circuits 101 to 108 are binary numbers "00".
000001 ", the latch circuit and level shift circuits 106 to 108 output in-phase output bit signals DH5 to
DH7 "000" and inverted output bit signal * DH5 to * DH7
"111" is output to the decoder 1 and as a result of decoding, the selection signals S1 to S8 are "1" only for S1 (the inverted selection signal is "0" only for * S1), whereby the PFET switch section 3-1 and the NFET. Only the switch unit 4-1 becomes active.

In the PFET switch section 3-1 and the NFET switch section 4-1, the in-phase output bit signals DH0 to DH4 and the inverted output bit signals * DH0 to * DH4 output from the latch circuits and level shift circuits 101 to 105 are output.
Are "00001" and "11110", respectively, so that only the FET row to which the gradation voltage V2 is input is all FE.
When T is turned on, the gradation voltage V2 is output to the liquid crystal cell.

As described above, in the multiplexer of the present embodiment, one set out of eight sets of switch units is selected based on the data from the most significant bit to the third most significant bit of the 8-bit digital data, The selected switch unit selects one of the input 32 kinds of gradation voltages based on the data from the least significant bit to the 5th bit, and outputs it to the liquid crystal cell.

Next, a layout in the case where the multiplexer shown in FIGS. 1 and 2 is formed into a CMOS integrated circuit will be described. FIG. 3 is a pattern of a portion (around NFET switch portions 4-1 to 4-8) in which it is significantly shown that the area of the IC chip can be significantly reduced by configuring the multiplexer as shown in FIGS. It is the schematic diagram which showed typically. Here, since the PFET and the NFET in FIG. 1 are formed as a PMOS transistor and an NMOS transistor, respectively, on the semiconductor substrate when forming a CMOS integrated circuit, the PFET switch section and the NFET switch section in FIG.
It will be referred to as a MOS switch section. Further, the horizontal direction in the figure corresponds to the X direction of the frame portion in FIG. 6, and the vertical direction corresponds to the Y direction.

In FIG. 3, 11, 11, ... Are N-type diffusion regions formed on the P-type semiconductor substrate, respectively.
Reference numeral 22 is a polysilicon wiring formed on each N-type diffusion region 11. In addition, the polysilicon wiring 12, 14, 1
6, 18 and 20 are in-phase output bit signals DH4,
DH3, DH2, DH1 and DH0 are also polysilicon wiring 1
Inverted output bit signals * DH4, * DH3, * DH2, * DH1, and * DH0 are output to 3, 15, 17, 19, and 21, respectively. Then, a selection signal corresponding to each NMOS switch section is input to the polysilicon wiring 22 in each NMOS switch section.

Reference numeral 23 denotes a gate electrode, which is provided at the intersection of each N-type diffusion region 11 and the polysilicon wirings 12 to 22 as required, thereby forming an NMOS transistor. Here, regarding the position where the gate electrode 23 is formed, the gate of each NFET in FIG. 1 and the in-phase output bit signals DH0 to DH4 and the inverted output bit signals * DH0 to *
Since it corresponds to the connection relationship with DH4, its explanation is omitted.

Reference numerals 24 to 31 denote aluminum wirings, respectively, each N-type diffusion region 11 and polysilicon wiring 12.
Is provided on an insulating film (not shown) formed on the upper surfaces of That is, in the layout of FIG. 3, there are two wiring layers, a polysilicon wiring layer and an aluminum wiring layer, which are separated by an insulating film, whereby the polysilicon wiring and the aluminum wiring can be provided in an overlapping manner.
Aluminum wiring 2 among the above-mentioned aluminum wiring
Reference numerals 4, 24, ... Are input signal lines for inputting the gradation voltages V1 to V256 to the respective NMOS transistors. The aluminum wiring 25 is an output signal line to which the output from each NMOS switch section is connected.
Further, the aluminum wirings 26 to 31 are selection signal lines for inputting the selection signals S2 to S8 output from the decoder 1 to each of the NMOS switch sections 4-2 to 4-8.

In the case of the above-mentioned multiplexer layout, the polysilicon wiring for supplying the selection signal output from the decoder 1 to each NMOS transistor is set to each NM in order to activate the NMOS switch section.
Only one OS switch unit is required, and aluminum wiring can be used for the selection signal line from the decoder 1 to each NMOS switch unit. Therefore, as described above, since the aluminum wiring layer and the polysilicon wiring layer are separated by the insulating film, as shown in FIG. 3, the aluminum wirings 26 to 31 through which the selection signals S2 to S8 pass are connected to the polysilicon wirings. 16 to 21 can be overlapped and formed.

Therefore, in FIG. 3, the number of wirings arranged in parallel in the X direction for each NMOS switch portion is twelve, that is, the output line 25 and the polysilicon wirings 12 to 22. Further, when viewed as the entire multiplexer, the wiring in the X direction is two output lines and 22 polysilicon wirings. When this is compared with the switch unit shown in FIG. 7, the switch unit in FIG. 7 requires two output lines and 32 polysilicon lines. That is, the multiplexer of the present embodiment can reduce the number of wirings arranged in parallel in the X direction by 10 compared to the layout of the conventional multiplexer.
Therefore, for each multiplexer, the length corresponding to the X direction in the IC chip can be shortened by the amount of 10 wires. If this is considered in the driver IC as a whole, as described above, the multiplexer is required as many as the respective source lines arranged in the liquid crystal display device (VG.
Therefore, it can be said that the length of the IC chip corresponding to the X direction is significantly reduced.

In the present embodiment, a multiplexer for controlling 256 gradations with 8-bit digital data is taken as an example, and the upper 3 bits of the digital data are decoded to select signals of each FET switch section. However, the number of bits used to generate this selection signal is determined in consideration of the performance required for the semiconductor chip, the width of the polysilicon wiring and the aluminum wiring, the spacing between the wirings, and the wiring layer. Considering the number of layers of
It may be determined so as to have the smallest wiring area.

[0051]

As described above, according to the multiplexer of the present invention, 2 ^m kinds of input signals are input to 2 ⁿ kinds of selection circuits by 2 ^mn kinds, and the decoder circuit outputs m bits of digital data. Of which, n (1 <n <m)
In the selection circuit specified by the result of decoding the bit digital data, one of the input 2 ^mn types of input signals is output based on the mn bit data, so that the present multiplexer is provided with a plurality of input signals. When formed on a semiconductor substrate having a wiring layer, a wiring provided between the decoder circuit and the 2 ⁿ selection circuits and an ^mn -bit data line input to each of the 2 ⁿ selection circuits are provided. , And can be formed on different wiring layers.
Further, by this, the width required for the wiring formed on the semiconductor substrate can be reduced, so that the chip size of the driver IC of the liquid crystal display device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multiplexer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration around a decoder of the multiplexer.

FIG. 3 is a schematic view showing a part of a layout when the multiplexer is formed on a semiconductor substrate.

FIG. 4 is an explanatory diagram for explaining the principle of the TFT driving method.

FIG. 5 is a block diagram showing an example of a configuration of a conventional multiplexer.

FIG. 6 is a frame portion of a liquid crystal display device and a driver IC.
FIG. 6 is an explanatory diagram for explaining the arrangement of FIG.

FIG. 7 is an explanatory diagram for explaining another configuration example of the switch unit in the conventional multiplexer.

[Explanation of symbols]

1 ... Decoder, 2 ... Inverter group, 3-1 to 3-8
... PFET switch, 4-1 to 4-8 ... NFET
Switch part, 11 ... N-type diffusion region, 12-22 ... Polysilicon wiring, 23 ... Gate electrode, 24-31 ...
Aluminum wiring 101-108 ... Latch circuit and level shift circuit

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Shigeru Yamada Inventor Shigeru Yamada 580, Horikawa-cho, Kawasaki-shi, Kanagawa 15-share company Toshiba Semiconductor Systems Technology Center (72) Inventor Hironori Minamizaki Horikawa-cho, Kawasaki-shi, Kanagawa 580 No. 15 in stock company Toshiba Semiconductor System Technology Center (72) Inventor Takashi Taguchi Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa No. 580 in stock company Toshiba Semiconductor System Technology Center

Claims (7)

[Claims] 1. A multiplexer for selecting and outputting one input signal by m-bit digital data among 2 ^m types of input signals having different voltage values, wherein n (1 <N <m)
A decoder circuit for decoding bit digital data, and 2 ⁿ selection circuits to which the 2 ^m kinds of input signals are input in 2 ^mn kinds each, which are selected according to the decoding result of the decoder circuit One selection circuit
²ⁿ selection circuits for selecting one of the input 2 ^mn types of input signals based on m-n bit data of the m-bit digital data, A multiplexer, wherein the decoder circuit and the 2 ⁿ selection circuits are formed on a semiconductor substrate having a plurality of wiring layers. 2. A plurality of wirings provided between the decoder circuit and the 2 ⁿ selection circuits, and an mn-bit data line input to each of the 2 ⁿ selection circuits, 2. The multiplexer according to claim 1, wherein each of the wiring layers is formed in a different wiring layer. 3. The wiring provided between the decoder circuit and the 2 ⁿ selection circuits and the mn-bit data line input to each of the 2 ⁿ selection circuits are parallel to each other. And the width of the wiring provided between the decoder circuit and the 2 ⁿ selection circuits and the width of the mn-bit data line in the section. 3. A multiplexer as claimed in claim 2, characterized in that it is formed by the value of n which minimizes the difference between and. 4. Each of the 2 ⁿ selection circuits includes a plurality of N-channel MOSFETs and a plurality of P-channel Ms.
4. The multiplexer according to claim 1, wherein the multiplexer is connected in series with an OSFET. 5. Each of the 2 ⁿ selection circuits includes a P channel MO when the input voltage is equal to or higher than a predetermined voltage value.
4. The multiplexer according to claim 1, wherein the multiplexer is composed of only SFET and is composed of only N-channel MOSFET when the input voltage is equal to or lower than a predetermined voltage value. 6. The predetermined voltage value is the P channel MO
ON resistance of SFET and O of N-channel MOSFET
The multiplexer according to claim 5, wherein the N resistance and the N resistance have the same voltage value. 7. Each of the 2 ⁿ selection circuits includes a P channel MO when the input voltage is equal to or higher than a first voltage value.
With SFET only, with the N-channel MOSFET only when the input voltage is less than or equal to the second voltage value, and when the input voltage is less than the first voltage value and greater than the second voltage value,
4. The multiplexer according to claim 1, wherein the multiplexer comprises a P-channel MOSFET and an N-channel MOSFET.