JPH09260375A - Semiconductor device - Google Patents

Abstract

(57) Abstract: To provide a wiring structure that is resistant to high frequencies. As a wiring structure, a structure in which a side surface and a bottom surface of a metal layer 16 as a signal wiring is surrounded by a metal layer 14 set to a ground potential via an insulating layer 15 is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device characterized by a wiring structure.

[0002]

2. Description of the Related Art Currently, logic LSI, SRAM, CM
The operating frequency of a semiconductor device (semiconductor element) such as an OS or a bipolar transistor has reached several hundred MHz to several GHz, and is expected to reach several tens GHz to several hundred GHz in the near future.

At this time, a problem is the influence of the high frequency signal. Specifically, when the operating frequency is 10 GHz, the wavelength of the high-frequency signal is about 3 cm. Therefore, for example, in a device using a high-frequency signal such as a communication device, wiring other than wiring in the device by the high-frequency signal is used. There is concern about the effect on other parts (other devices).

Further, when the operating frequency becomes 100 GHz, the wavelength of the high frequency signal becomes about 3 mm.
In addition to the influence of other devices in the equipment due to high frequency signals,
The wiring itself is also likely to be affected by high frequencies from its surroundings.

Under the influence of high frequency, the signal current may change and the device may malfunction. Currently, L
Since the wiring of SI tends to be multi-layered, it is considered that the influence of high frequency will become apparent in the future.

At present, a wiring structure having a single-layer cross section used in a semiconductor device is easily affected by a high-frequency signal. As a countermeasure against this, a method of adjusting a distance between wirings or a dielectric constant of an insulating film has hitherto been used. It has been taken.

However, when the size of the LSI is further reduced in the future, the countermeasure method for adjusting the distance between wirings cannot be a practical countermeasure because the degree of freedom in wiring design decreases. on the other hand,
As a countermeasure method for adjusting the dielectric constant, the thickness and material of the insulating film must be changed, which requires a large amount of R & D cost and labor, and similarly cannot be a realistic countermeasure.

[0008]

As described above, a method of adjusting the distance between wirings and the dielectric constant of the insulating film has been taken as a measure for reducing the influence of high frequency signals. But,
This type of method cannot be a practical countermeasure because the degree of freedom in wiring design is reduced and a large amount of R & D cost and labor are required when the size of the LSI is further reduced in the future.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor having a wiring structure capable of easily reducing the influence of a high frequency signal even if the size of the LSI is further reduced in the future. To provide a device.

[0010]

[Means for Solving the Problems]

[Outline] In order to achieve the above object, a semiconductor device (claim 1) according to the present invention comprises: a first conductive layer as a signal wiring; and an insulating layer around the first conductive layer. A second conductive layer formed so as to partially surround the periphery, and a wiring structure in which a potential of the first conductive layer and a potential of the second conductive layer are different from each other. It is characterized by

Another semiconductor device according to the present invention (claim 2) is characterized in that the wiring structure of the semiconductor device (claim 1) is formed by laminating two or more layers via an interlayer insulating film. To do.

Another semiconductor device according to the present invention (claim 3) is the same as the semiconductor device (claim 1) above the wiring structure (first wiring structure) of the semiconductor device (claim 1). The wiring structure (second wiring structure) according to item 1) is provided via an interlayer insulating film, and the first conductive layer as the signal wiring of the second wiring structure is the signal wiring of the first wiring structure. Is electrically connected to the first conductive layer of the first wiring structure through an opening formed in the interlayer insulating film on the first conductive layer.

According to another semiconductor device of the present invention (claim 4), there is provided a first conductive layer as a signal wiring and the first conductive layer.
A second conductive layer formed around the conductive layer so as to partially surround the conductive layer via an insulating layer, and the potential of the first conductive layer and the second conductive layer. A wiring structure having two or more potentials different from each other is formed by stacking two or more layers with an interlayer insulating film interposed therebetween. The wiring structure is insulated from the first conductive layer and is electrically connected to the second conductive layer in a predetermined manner. A third conductive layer set to a potential is provided.

Here, it is desirable that all the second conductive layers are provided on the surfaces where the surfaces of all the second conductive layers are exposed and the surface layers of all the first conductive layers are not exposed. It is preferable that a third conductive layer set to the ground potential be provided so as to be connected to.

Preferred modes of the present invention are as follows. (1) Make the potential of the second conductive layer the same as the substrate potential. (2) Make the potential of the second conductive layer the same as the ground potential. (3) Make the potential of the third conductive layer the same as the ground potential. (4) The second conductive layer is formed so as to surround the lower peripheral portion of the first conductive layer. (5) The upper surfaces of the first conductive layer, the insulating layer, the second conductive layer, and the interlayer insulating film formed around them are substantially in the same plane. (6) The material of the first conductive layer and the second conductive layer is T
i, V, Cr, Zr, Nb, Mo, Hf, Ta, W, C
A compound of one element or two or more elements selected from u, Ag, Au, Al and Si is used. (7) As the interlayer insulating film, a SiO ₂ film, a SiN film, a polyimide film, or a laminated film of these insulating films is used. (8) As the semiconductor substrate on which the wiring structure of the present invention is formed, a Si substrate, a Ge substrate, a GaAs substrate, a ZnSe substrate, a CdTe substrate, or an InGaP substrate is used.

[Operation] The wiring structure according to the present invention has substantially the same line structure as the coaxial cable. Therefore, the wiring structure according to the present invention is unlikely to be affected by high frequencies even if it is provided in a portion that operates at high speed. At the same time, even if a high-frequency signal is passed through the wiring structure according to the present invention, the other parts are not easily affected by the high frequency.

Further, since the wiring structure according to the present invention can be formed by a simple process, unlike the case of the conventional high frequency measure for adjusting the distance between wirings or the dielectric constant of the insulating film, the wiring design is free. There will be no problems such as diminished degree, cost and labor.

Therefore, according to the present invention, it is possible to provide a semiconductor device having a wiring structure capable of easily reducing the influence of a high frequency signal even if the size of the LSI is further reduced in the future.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIGS. 1 and 2 are process sectional views showing a method for forming a coaxial wiring according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a first insulating layer 11 and a second insulating layer 12 are sequentially formed on an insulating film or a semiconductor substrate 10. As the insulating layers 11 and 12,
For example, a SiO ₂ layer, a SiN layer, a polyimide layer, or a laminated film of these insulating layers is used.

Next, as shown in FIG. 1B, a wiring groove 13 is formed in the second insulating layer 12 by reactive ion etching (R).
It is formed by using anisotropic etching such as IE (Reactive Ion Etching).

At this time, the first insulating layer 11 is used as a stopper at the time of forming the groove 13, and if the same processing can be performed, it is not particularly necessary to provide it. Next, FIG.
As shown in, the sputtering method and the chemical vapor deposition method (C
VD: Chemical Vapor Deposit
The first metal layer 14 as a ground wire is formed on the entire surface by a film forming method such as ion.

The material of the metal layer 14 is Ti,
One or more elements selected from refractory metals such as V, Cr, Zr, Nb, Mo, Hf, Ta and W, precious metals such as Cu, Ag and Au, and conventional wiring materials Al and Si. Compounds of the elements can be used.

Next, as shown in FIG. 3D, LP-CVD is performed.
(Low Pressure-Chemical Va
The third insulating layer 15 is formed on the first metal layer 14 by a film forming method having a good coverage such as por deposition.

The insulating layer 15 is, for example, SiO.
_{A two-} layer, a SiN layer, a polyimide layer, or a laminated film of these insulating layers can be used. Next, as shown in FIG. 2A, a second metal layer 16 as a signal wiring is formed on the entire surface by a film forming method such as a sputtering method or a CVD method.

The material of the metal layer 16 is Ti,
A high melting point metal such as V, Cr, Zr, Nb, Mo, Hf, Ta or W, a noble metal such as Cu, Ag or Au, or a conventional wiring material such as Al or Si can be used. Usually, the same material as the first metal layer 16 is used.

Next, as shown in FIG. 2B, the metal layer 16 is sufficiently embedded in the groove 13 by heat treatment or reflow by laser annealing. Note that this reflow step can be omitted if the metal layer 16 is sufficiently embedded in the step of FIG.

Next, as shown in FIG. 2C, the metal layers 14 and 16 and the insulating layer 15 other than the groove 13 portion are chemically mechanically polished (CMP: Chemical Mechanical).
(1Polishing) or a flattening technique such as a resist etch back method to remove and complete the coaxial wiring.

Finally, as shown in FIG. 2D, by grounding the first metal layer 14, the first metal layer 1 is grounded.
4 acts as a ground wire. Therefore, the second metal layer 16 is used as a signal wire (core wire),
Even if a high frequency signal is applied to the metal layer 16, the first metal layer 1
4, the second metal layer 16
There is no electric field leakage to the left, right or bottom. On the contrary, the second metal layer 16 can block the influence of the electric field from the left, right, and bottom.

That is, since the coaxial type wiring of the present embodiment has substantially the same line structure as the coaxial cable, other portions are not affected even when a high frequency signal is passed, and
Even if a part that operates at high speed is provided, it is not easily affected by high frequencies.

Further, since the wiring structure of the present embodiment can be formed by a simple process, unlike the conventional case of high frequency measures for adjusting the distance between wirings or the dielectric constant of the insulating film, the wiring design is free. There will be no problems such as diminished degree, cost and labor.

The influence of the electric field leaking upward in the second metal layer 16 can be blocked if the upper wiring has the same structure as the wiring of this embodiment. (Second Embodiment) FIGS. 3 and 4 are process sectional views showing a method for forming a coaxial wiring according to a second embodiment of the present invention. This embodiment is an example in which the coaxial wiring is multilayered.

First, as shown in FIG. 3A, the coaxial wiring of the first layer is formed by the same method as in the first embodiment. Next, as shown in FIG.
0, the first insulating layer (etching stopper) 21, and the second insulating layer 22 are sequentially formed. Insulating layers 20, 21, 22
As the (interlayer insulating film), for example, SiO ₂ film, SiN
A film, a polyimide film, or a laminated film of these insulating layers is used.

Next, as shown in FIG. 3B, wiring grooves 23 are formed in the second insulating layer 22 in a desired pattern.
At this time, the first insulating layer 21 is used as an etching stopper when forming the groove 23, and if the same processing is possible, it is not particularly necessary to provide it.

Next, as shown in FIG. 3C, a metal layer 24 as an earth wire is formed by a film forming method such as a sputtering method or a CVD method. The material of the metal layer 24 is T
One or two elements selected from refractory metals such as i, V, Cr, Zr, Nb, Mo, Hf, Ta and W, precious metals such as Cu, Ag and Au, and conventional wiring materials Al and Si. Compounds of the above elements can be used.

Next, in order to contact the signal wiring,
As shown in FIG. 3D, the via hole 25 is formed by using the RIE method or the like. Here, the insulating layer 15 is used so that the etching rate of the insulating layer 15 used for separating the signal wiring and the ground wire in the first-layer coaxial wiring is slower than that of the inter-wiring insulating layer 20. When the material of the inter-wiring insulating layer 20 is selected, the insulating layer 15 functions as an etching stopper even if misalignment between the signal wiring and the via hole occurs. That is, the insulating layer 1
5, the buried shape of the metal layer 16 as the signal wiring is not deteriorated.

Next, as shown in FIG. 3E, in order to electrically insulate the metal layer 16 as a signal wire and the metal layer 24 as a ground wire, a method with a good coverage such as an LP-CVD method. As a result, the insulating layer 26 including a SiO ₂ layer, a SiN layer, a polyimide layer film, or a laminated film of these insulating layers is formed.
To form

Next, as shown in FIG. 4A, the insulating layer 26 at the bottom of the contact is removed by bias cleaning with Ar or RIE. Next, as shown in FIG. 4B, a metal layer 27 as a signal wiring is formed on the entire surface by a sputtering method, a CVD method or the like. The metal layer 27 is directly connected to the metal layer via the groove.

Materials for the metal layer 27 include Ti, V, and C.
High melting point metals such as r, Zr, Nb, Mo, Hf, Ta and W, noble metals such as Cu, Ag and Au, and one element or a compound of two or more elements selected from conventional wiring materials Al and Si. Can be used. Usually, the same material as the metal layer 24 is used.

Next, as shown in FIG. 4C, the metal layer 27 is sufficiently embedded in the groove by heat treatment or reflow by laser annealing. Note that this reflow step can be omitted if the metal layer 27 is sufficiently embedded in the step of FIG. 4B.

Finally, as shown in FIG. 4D, the metal layers 24 and 27 and the insulating layer 26 other than the groove portions are removed by a flattening technique such as a CMP method or a resist etch back method to remove the second layer. The coaxial wiring is completed.

In the case of forming a multi-layer wiring having three or more layers, it is possible to repeat the steps shown in FIGS. At this time, between the upper and lower coaxial wirings of the second layer and above, the insulating layer used for separating the signal wiring and the ground wire should have a slower etching rate than the interlayer insulating layer. desirable.

In this embodiment, the same effect as that of the second embodiment can be obtained. Further, it is possible to easily make contact between the upper and lower coaxial wirings. (Third Embodiment) FIGS. 5 and 6 are process sectional views showing a method of forming a coaxial wiring according to a third embodiment of the present invention. This embodiment is another example in which the coaxial wiring is multilayered.

First, as shown in FIG. 5A, the coaxial wiring of the first layer is formed by the same method as in the first embodiment. Next, as shown in FIG. 5B, the inter-wiring insulating layer 40 is formed by a film forming method such as a sputtering method or a CVD method. As the inter-wiring insulating layer 40, for example, SiO
_{A two-} layer, a SiN layer, a polyimide layer, or a laminated film of these insulating layers can be used.

Next, in order to make contact with the signal wiring, as shown in FIG. 5C, a via hole 41 is formed by using the RIE method or the like. Here, the insulating layer 15 and the wiring are arranged so that the etching rate of the insulating layer 15 used for separating the signal wiring and the ground wire in the wiring of the first layer is slower than that of the inter-wiring insulating layer 40. When the material of the inter-insulating layer 40 is selected, the insulating layer 15 functions as an etching stopper even if misalignment between the signal wiring and the via hole occurs. That is, the insulating layer 15 is not etched and the embedded shape of the metal layer 16 is not deteriorated.

Next, as shown in FIG. 5D, in order to extract a signal from the signal wiring of the coaxial wiring of the first layer, a film forming method such as a sputtering method or a CVD method is used to form a lead wiring. To form the metal layer 42.

The material of the metal layer 42 is Ti, V, C.
One element or a compound of two or more elements selected from refractory metals such as r, Zr, Nb, Mo, Hf, Ta and W, precious metals such as Cu, Ag and Au, and conventional wiring materials Al and Si. Can be used.

Next, as shown in FIG. 5E, the metal layer 42
Is processed into a desired pattern using an etching method such as the RIE method, and then an interlayer first insulating layer 43 and a second insulating layer (stopper layer) 44 are sequentially formed on the entire surface.

Next, as shown in FIG. 6A, after forming an insulating layer 48 on the entire surface, the second layer coaxial wiring (metal layer 45) is formed by using the same method as in the first embodiment. , Insulating layer 4
6, a metal layer 47) is formed. Next, as shown in FIG. 4A, the insulating layer 49 is formed on the entire surface.

As these insulating layers 43, 44 and 49,
For example, a SiO ₂ film, a SiN film, a polyimide film, or a laminated film of these insulating layers can be used. Also,
As the film forming method, for example, a sputtering method or a CVD method can be used.

At this time, the second insulating layer 44 is used as an etching stopper when forming the coaxial wiring of the second layer, and if the same processing is possible, it is not particularly necessary to provide it.

Next, as shown in FIG. 6B, the via holes 50 and 51 are formed with RI in order to make contact with the signal wiring.
It is formed by using the E method or the like. Here, the insulating layer 46 and the interlayer insulating film are formed so that the etching rate of the insulating layer 46 used for separating the signal line and the ground line in the second layer wiring is slower than that of the insulating layer 49. When the material of No. 49 is selected, the insulating layer 46 functions as an etching stopper even if misalignment between the signal wiring and the via hole occurs. That is, the insulating layer 46 is not etched and the embedded shape of the metal layer 47 is not deteriorated.

Next, as shown in FIG. 6C, in order to extract a signal from the signal wiring of the coaxial wiring of the second layer, a film forming method such as a sputtering method or a CVD method is used to form a connection wiring. To form the metal layer 52.

Materials for the metal layer 52 include Ti, V, and C.
A refractory metal such as r, Zr, Nb, Mo, Hf, Ta or W, a noble metal such as Cu, Ag or Au, or one element or a compound of two or more elements made of conventional wiring materials Al and Si is used. be able to.

At this time, if the metal layer 52 cannot be sufficiently embedded in the via holes 50 and 51, the via hole 5 is subjected to heat treatment or reflow by laser annealing.
The metal layer 52 is sufficiently embedded in 0, 51.

Finally, as shown in FIG. 6D, the metal layer 52 is processed into a desired pattern by etching such as RIE to complete the coaxial wiring of the second layer.
In addition, in the case of forming a multilayer wiring of three layers or more, FIG.
The process of FIG. 6 may be repeated. In this embodiment, the same effect as the third embodiment can be obtained. (Fourth Embodiment) FIGS. 7, 8 and 9 show a fourth embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method for forming the coaxial wiring according to the embodiment of FIG. This embodiment is another example in which the coaxial wiring is multilayered.

First, as shown in FIG. 7A, two insulating layers having a laminated structure consisting of a first insulating layer (etching stopper) 31 and a second insulating layer 32 are formed on an insulating film or a semiconductor substrate 30. Form.

As the insulating layers 31 and 32, for example, Si
An O ₂ layer, a SiN layer, a polyimide layer, or a laminated film of these insulating layers can be used. Next, as shown in FIG. 7B, a wiring groove 33 is formed in the second insulating layer 32 by RIE.
And the like.

Next, as shown in FIG. 7C, a contact pad groove 34 is formed in the second insulating layer 32. At this time, the first insulating layer 31 is used as an etching stopper at the time of forming the grooves 33 and 34, and it is not particularly necessary to provide it if similar processing can be performed.

Next, as shown in FIG. 7D, a metal layer 35 as a ground wire is formed by a sputtering method or a CVD method, and then a film forming method with a good coverage such as an LP-CVD method is used. The insulating layer 36 is formed.

As the insulating layer 36, for example, SiO ₂
A layer, a SiN layer, a polyimide layer, or a laminated film of these insulating layers can be used. Next, as shown in FIG. 3D, by a film forming method such as a sputtering method or a CVD method,
A metal layer 37 as a signal wiring is formed.

Materials for the metal layer 37 include Ti, V, and C.
One or more elements selected from refractory metals such as r, Zr, Nb, Mo, Hf, Ta and W, precious metals such as Cu, Ag and Au, and conventional wiring materials Al and Si. Can be used.

Next, as shown in FIG. 7E, the grooves 33, 34 are formed by reflowing by heat treatment or laser annealing.
The metal layer 37 is sufficiently embedded therein. Note that this reflow step can be omitted if the metal layer 37 is sufficiently embedded in the step of FIG. 7D.

Next, as shown in FIG. 8A, the grooves 33, 3 are formed.
The metal layers 35 and 37 and the insulating layer 36 other than the four portions are removed by a flattening technique such as a CMP method or a resist etch back method. At this stage, the coaxial wiring of the first layer is completed.

Next, in order to form the coaxial wiring of the second layer, first, as shown in FIG. 8B, the inter-wiring insulating film 38 is formed.
To form Next, as shown in FIG. 2B, two insulating layers having a laminated structure including the first insulating layer 31 and the second insulating layer 32 are formed on the inter-wiring insulating film 38.

Next, as shown in FIG. 8C, the insulating layer 3
1, 32 are processed by RIE or the like to form wiring grooves 33. At this time, the lower one of the two first insulating layers 31 is used as an etching stopper for the inter-wiring insulating film 38. However, if similar processing is possible, it is not particularly necessary to provide it.

Next, as shown in FIG. 8D, the insulating layer 32 is formed.
A groove 34 for a contact pad is formed in. At this time,
The upper one of the two first insulating layers 31 is the two second insulating layers 31.
Is used as an etching stopper for the upper one of the insulating layers 32. However, if similar processing is possible, it is not particularly necessary to provide it.

Next, as shown in FIG. 9A, in order to make contact with the ground line, the insulating layers 31 and 32 and the inter-wiring insulating film 38 are etched to form a contact hole 39.

Next, as shown in FIG. 9A, after the metal layer 35 as the ground wire is formed by the film forming method such as the sputtering method or the CVD method, the signal wiring and the ground wire are electrically insulated. Therefore, the insulating layer 36 is formed by a film forming method having a good coverage such as an LP-CVD method.

As the insulating layer 36, for example, SiO _{2 is used.}
A layer, a SiN layer, a polyimide layer, or a laminated film of these insulating layers is used. Next, as shown in FIG. 9B, a metal layer 37 as a signal wiring is formed by a film forming method such as a sputtering method or a CVD method.

Next, as shown in FIG. 9C, the metal layer 37 is sufficiently buried in the groove by heat treatment or reflow by laser annealing. Note that this reflow step can be omitted if the metal layer 37 is sufficiently embedded in the step of FIG. 9B.

Finally, as shown in FIG. 9D, the metal layers 35, 37 in the portion above the groove formed in the insulating layer 32,
The insulating layer 36 is removed by a planarization technique such as a CMP method or a resist etch back method to complete the coaxial wiring of the second layer.

In the case of forming a multi-layer wiring having three or more layers, the steps of FIGS. 7, 8 and 9 may be repeated. In the present embodiment, the same effect as in the first embodiment can be obtained. Further, since the upper and lower metal layers 35 serving as ground lines are connected to each other through the contact holes 39, if one metal layer 35 is set to the ground potential, the remaining metal layers 35 are simultaneously set to the ground potential. Will be. That is, it is sufficient to set one metal layer 35 to the ground potential.
The same applies to the case of three or more layers. (Fifth Embodiment) FIGS. 10 and 11 are process sectional views showing a method of forming a coaxial wiring according to a fifth embodiment of the present invention. This embodiment is another example in which the coaxial wiring is multilayered.

First, as shown in FIG. 10A, a first insulating layer (etching stopper) 61 and a second insulating layer 62 are sequentially formed on a wafer or an insulating film formed on the wafer.

As the insulating layers 61 and 62, for example, Si
An O ₂ layer, a SiN layer, a polyimide layer, or a laminated film of these insulating layers can be used. Next, as shown in FIG. 10B, a wiring groove 63 is formed in the second insulating layer 62 by RI.
It is formed using E or the like. At this time, the first insulating layer 61
Is used as a stopper at the time of forming the groove 63, and it is not particularly necessary to provide it if similar processing is possible.

Next, as shown in FIG. 9B, a first metal layer 64 as a ground wire is formed by a film forming method such as a sputtering method or a CVD method. As the material of the metal layer 64, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta,
It is possible to use a high melting point metal such as W, a noble metal such as Cu, Ag, and Au, or one element selected from Al and Si, which are conventional wiring materials, or a compound of two or more elements.

Next, as shown in FIG.
The insulating layer 65 is formed by a film forming method having a good coverage such as the D method. As the insulating layer 65, for example, a SiO ₂ layer, SiN
A layer, a polyimide layer, or a stacked film of these insulating layers can be used.

Next, as shown in FIG. 9B, a second metal layer 66 as a signal wiring is formed by a film forming method such as a sputtering method or a CVD method. The material of the second metal layer 66 may be the same as that of the first metal layer 64.

Next, as shown in FIG. 10C, the metal layer 66 is sufficiently embedded in the groove 63 by heat treatment or reflow by laser annealing. Note that this reflow step can be omitted if the metal layer 66 is sufficiently embedded in the step of FIG. 10B.

Next, as shown in FIG. 10D, the metal layer 66 other than the groove portion is removed by a flattening technique such as a CMP method or a resist etch back method to form a signal wiring. At this stage, the coaxial wiring of the first layer is completed.

Next, in order to form the coaxial wiring of the second layer in the same manner as the coaxial wiring of the first layer, first, as shown in FIG.
As shown in, the inter-wiring insulating film 67 and the insulating layers 68 and 69 are sequentially formed.

As the insulating layers 67, 68, 69 (interlayer insulating film), for example, a SiO ₂ layer, a SiN layer, a polyimide film layer or a laminated film of these insulating layers can be used. Next, as shown in FIG. 11A, a wiring groove 70 is formed in the insulating layer 69 by using RIE or the like.

At this time, the insulating layer 68 is used as a stopper at the time of forming the groove 70, and if the same processing is possible, it is not particularly necessary to provide it. Next, as shown in FIG. 6A, after forming the first metal layer 71 by a film forming method such as a sputtering method or a CVD method, a film forming method with a good coverage such as an LP-CVD method is performed. The insulating layer 72 is formed.

The material of the metal layer 71 is Ti, V, C.
A material selected from high melting point metals such as r, Zr, Nb, Mo, Hf, Ta and W, precious metals such as Cu, Ag and Au, and conventional wiring materials Al and Si can be used.

As the insulating layer 72, for example, Si
An O ₂ layer, a SiN layer, a polyimide layer, or a laminated film of these insulating layers can be used. Next, as shown in FIG. 11B, the second metal layer 73 is formed on the entire surface by a film forming method such as a sputtering method or a CVD method. At this time,
When the metal layer 73 cannot be sufficiently filled in the groove, it is filled by heat treatment or reflow by laser annealing. The material of the second metal layer 73 may be the same as that of the first metal layer 71.

Next, as shown in FIG. 11C, the metal layer 73 other than the groove portion is removed by the CMP method, the resist etch back method or the like to form the signal wiring, and the second layer of coaxial type wiring is formed. Complete.

Finally, as shown in FIG. 11D, in order to connect the metal layers 64 and 71 to form a ground wire, a cleavage surface formed when the wafer is cut into chips, that is, a ground wire. The third metal layer 74 is formed on the surface where the surfaces of the metal layers 64 and 71 are exposed and the surfaces of the metal layers 66 and 731 as the signal wiring are not exposed, and the conductive layer 74 is grounded. To do.

The metal layer 74 may be formed by a film forming method such as a CVD method, or may be formed by applying a conductive material such as a conductive paste. It should be noted that in the case of forming a multilayer wiring of three layers or more, the steps of FIGS. 10 and 11 may be repeated.

Also in this embodiment, the same effect as in the fourth embodiment can be obtained. Further, according to the present embodiment, since it is not necessary to form the lead wiring or the connection wiring, it becomes possible to ground all the ground wires by a simpler process than the fourth embodiment.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the potential of the metal layer as the ground wire is set to the ground potential has been described, but it is not always necessary to set it to the ground potential.

That is, if the potential of the metal layer as the ground wire is different from the potential of the metal layer as the signal wiring,
It need not be at ground potential. This is achieved, for example, by setting the potential of the metal layer as the ground wire to the substrate potential (usually the ground potential).

Further, in the above embodiment, the type of the substrate on which the coaxial wiring is formed is not particularly mentioned.
For example, Si substrate, Ge substrate, GaAs substrate, ZnSe
A semiconductor substrate such as a substrate, a CdTe substrate or an InGaAsP substrate can be used. In addition, various modifications can be made without departing from the scope of the present invention.

[0093]

As described in detail above, according to the present invention, by using a wiring structure substantially in the form of a coaxial cable,
Even if the size of the LSI is further reduced in the future, the influence of high frequency signals can be easily reduced.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for forming a first half of a single-layer coaxial wiring according to a first embodiment of the present invention.

2A to 2C are process cross-sectional views showing a method of forming the latter half of the multilayer coaxial wiring according to the first embodiment of the invention.

FIG. 3 is a process sectional view showing a method of forming a first half of a multilayer coaxial wiring according to a second embodiment of the present invention.

FIG. 4 is a process sectional view showing a method of forming the latter half of the multilayer coaxial wiring according to the second embodiment of the invention.

FIG. 5 is a process sectional view showing a method of forming the first half of a multilayer coaxial wiring according to a third embodiment of the invention.

FIG. 6 is a process sectional view showing a method of forming the latter half of a multilayer coaxial wiring according to a third embodiment of the invention.

FIG. 7 is a process cross-sectional view showing the method for forming the first half of the multilayer coaxial wiring according to the fourth embodiment of the present invention.

FIG. 8 is a process cross-sectional view showing the method for forming the middle half of the multilayer coaxial wiring according to the fourth embodiment of the present invention.

FIG. 9 is a process sectional view showing a method of forming the latter half of the multilayer coaxial wiring according to the fourth embodiment of the invention.

FIG. 10 is a process sectional view showing the method of forming the first half of the multilayer coaxial wiring according to the fifth embodiment of the invention.

FIG. 11 is a process cross-sectional view showing the method of forming the latter half of the multilayer coaxial wiring according to the fifth embodiment of the invention.

[Explanation of symbols]

 10 ... Substrate 11, 12 ... Insulating layer 13 ... Groove 14 ... Metal layer (second conductive layer) 15 ... Insulating layer 16 ... Metal layer (first conductive layer) 20 ... Inter-wiring insulating layer 21, 22 ... Insulating layer 23 ... Groove 24 ... Metal layer (second conductive layer) 25 ... Via hole 26 ... Insulating layer 27 ... Metal layer (first conductive layer) 30 ... Substrate 31, 32 ... Insulating layer 33, 34 ... Groove 35 ... Metal Layer (second conductive layer) 36 ... Insulating layer 37 ... Metal layer (first conductive layer) 38 ... Inter-wiring insulating film 40 ... Inter-wiring insulating film 41 ... Via hole 42 ... Metal layers 43, 44 ... Insulating layer 45 Metal layer (second conductive layer) 46 ... Insulating layer 47 ... Metal layer (first conductive layer) 48, 49 ... Insulating layer 50, 51 ... Via hole 52 ... Metal layer 61, 62 ... Insulating layer 63 ... Groove 64 ... Metal layer (second conductive layer) 65 ... Insulating layer 66 ... Metal layer (first conductive layer) 67 ... Inter-wiring insulating film 68, 69 ... Insulating layer 71 ... Metal layer (second conductive layer) 72 ... Insulating layer 73 ... Metal layer (first conductive layer) 73 ... Metal layer (third conductive layer)

Claims (5)

[Claims] 1. A first conductive layer as a signal wiring, and a second conductive layer formed around the first conductive layer so as to partially surround the first conductive layer via an insulating layer. A semiconductor device having a wiring structure having a potential of the first conductive layer and a potential of the second conductive layer different from each other. 2. A semiconductor device, wherein the wiring structure according to claim 1 is formed by laminating two or more layers with an interlayer insulating film interposed therebetween. 3. The wiring structure according to claim 2 is provided on the wiring structure according to claim 1 through an interlayer insulating film, and the wiring structure as a signal wiring of the second wiring structure is provided. A first conductive layer of the first wiring structure is formed through an opening formed in the interlayer insulating film on the first conductive layer as a signal wiring of the first wiring structure. A semiconductor device, which is electrically connected to a conductive layer. 4. A first conductive layer as a signal wiring, and a second conductive layer formed around the first conductive layer so as to partially surround the first conductive layer via an insulating layer. And a wiring structure in which the potential of the first conductive layer and the potential of the second conductive layer are different from each other is formed by laminating two or more layers via an interlayer insulating film, and is insulated from the first conductive layer The semiconductor device is provided with a third conductive layer set to a predetermined potential so as to be conducted in common with the second conductive layer. 5. The method according to claim 1, wherein the second conductive layer is formed so as to surround a lower peripheral portion of the first conductive layer. The semiconductor device according to 1.