JPH09275196A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a narrow element separation width and manufacturing method thereof, whereby such semiconductor device can be easily and reliably produced while ensuring an inversion withstanding voltage and punch-through withstanding voltage, without using a complicated process. SOLUTION: Source and drain regions of adjacent elements to be separated are formed below separating trenches 40 in the form of common broad impurity diffused layer lines. A first conductive film 31 covering a gate insulation film 24 and separating insulation film 23 is patterned to separate the elements. At the same time, utilizing an etch-resistive film, it is etched in the same pattern as deep as piercing the separating insulation film 23 down to a substrate 10 to form element separating trenches into the substrate and the impurity diffused layer lines 11 on the substrate are separated by these trenches to form source and drain lines 12, 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EEPROM (Electr
TECHNICAL FIELD The present invention relates to a semiconductor device such as an Erasable Programmable ROM) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Recently, a non-volatile memory such as an EEPROM that can be electrically written and erased has been actively developed. Also, attention is focused on a flash memory that can achieve high density at low cost. Among flash memories, flash E having a memory array configuration as shown in FIG.
EPROMs are known. This flash EEPRO
In M, memory transistors MTr are arranged in a matrix, and bit lines (drain lines) BL and source lines SL are wired in the vertical direction of the drawing, and the memory transistors MTr in the vertical direction of the drawing include these bit lines BL and source lines SL. To share. The word line (control gate) WL is wired orthogonally to the bit line BL, and each memory transistor MTr
Constitutes the control gate of. The memory transistors MTr in the word line WL direction are isolated from each other.

Writing and erasing of this memory is performed by FN using the entire surface of the channel with the control gate WL being a positive bias.
(Fowler Nordheim) tunneling causes electrons to be injected into the floating gate FG to write data, while the control gate WL is used as a negative bias to cause floating gate FG.
Erasing is performed by pulling out electrons from the inside. This method has various advantages over other methods.

For example, CHE (Channel Hot Electron)
Since power consumption during writing is lower than that of the injection method, writing by the internal booster circuit can be speeded up. Regarding the number of times of writing, it is known that the FN tunneling injection on the entire surface of the channel is more advantageous for both writing and erasing.

Even in the method of writing data by extracting electrons from the floating gate by FN tunneling, a band-to-band tunnel current flows at the time of writing data, so that there is a problem in the writing speed due to internal boosting. Further, it is advantageous in that random access is faster than the NAND type in which FN tunneling injection is applied to the entire surface of the same channel.

An example of a conventional method of manufacturing a memory cell having the above characteristics will be briefly described with reference to the drawings. 14 is a process sectional view, and FIG. 15 is a plan view. First, as shown in FIG. 14A, the semiconductor substrate 10
The element isolation region 200 is formed at 0 using the LOCOS method.

Next, as shown in FIGS. 14B and 15A, the pad oxide film 202 and the silicon nitride film 20 are formed.
3 is formed and patterned by photolithography and dry etching so as to cover a portion to be a channel region. At this time, polycrystalline silicon may be formed between the pad oxide film 202 and the silicon nitride film 203 in order to relax the stress of the silicon nitride film 203. continue,
Using the silicon nitride film 203 as a mask, phosphorus or arsenic is ion-implanted to form the impurity diffusion layer 101.

Next, thermal oxidation is performed to form the silicon nitride film 20.
Since 3 serves as an oxidation mask, FIGS.
As shown in (b), a relatively thick oxide film 204 is formed. At this time, the drain line (bit line) 102 and the source line 103 are formed under the oxide film 204.

Next, as shown in FIGS. 14D and 15C, the silicon nitride film and the pad oxide film are peeled off to expose the channel region. Subsequently, as shown in FIG. 14E, thermal oxidation is performed to form a tunnel oxide film 205.

Next, as shown in FIG. 14 (f), polycrystalline silicon 301 to be a floating gate is formed and patterned. At this time, as shown in FIG. 15D, the polycrystalline silicon is not cut in the extending direction of the bit line (the BB 'direction in the drawing). Then, ion implantation for forming a channel stop is performed. In order to secure the reverse breakdown voltage, it is necessary to make the injection amount as high as 10 ¹⁷ / cm ³ order. Further, the channel stop 104 needs to be spaced apart from the bit line 103 or the source line 102 in order to secure the junction breakdown voltage. This ion implantation is performed on the floating gate 301.
The ONO film can be shared with the mask at the time of formation, but in order to prevent diffusion due to heat at the time of forming the ONO film (three-layer film of silicon oxide, silicon nitride, and silicon oxide film) formed on the floating gate 301, After forming, the ion implantation may be performed again through the photolithography process.

Next, after forming the ONO film 206, polycrystalline silicon 302 serving as a control gate is deposited, a resist film is formed and patterned, and then the control gate 302,
The ONO film 206 and the floating gate 301 are etched at one time. Further, by using the resist for forming the control gate as a mask, boron ion implantation is carried out to the bit line direction (B−
The memory cells adjacent to B ') are separated. As a result, a memory cell having a structure as shown in FIGS. 14G and 15E can be obtained.

[0012]

However, in the above method, a high voltage of about 20 V is required at the time of writing, so that the inversion withstand voltage and the punch through withstand voltage in the element isolation between the memory cells adjacent to the bit line can be secured. There is a problem that it becomes difficult.

In the separation by the LOCOS method or the like, when the LOCOS film thickness is increased in order to secure the inversion breakdown voltage, the separation width increases by the width of the bird's beak due to the dimension conversion difference, and the integration degree decreases. It is conceivable to adopt trench isolation having a large punch-through breakdown voltage instead of LOCOS, but in order to simultaneously form a portion having a large isolation width and a portion having a small isolation width, for example, CMP (chemical mechanical polishing) or the like is used. There is a problem in that a complicated embedded flattening process using the special process technology is required, resulting in an increase in cost.

It is also possible to increase the concentration of the channel stop, but in order to secure the junction breakdown voltage, it is necessary to provide a space between the source / drain region and the channel stop ion-implanted region, and the separation width is also large. It becomes necessary to do so, and the degree of integration is reduced.

The present invention has been made in view of the above circumstances, and a semiconductor device having a small element isolation width while ensuring the inversion breakdown voltage and the punch-through breakdown voltage, and a semiconductor device such as this can be easily and easily formed without using a complicated process. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be reliably manufactured.

[0016]

In order to achieve the above object, the present invention has a semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, and isolation insulating films formed on both sides of the gate insulating film. An impurity diffusion layer formed on the substrate below the isolation insulating film, a first conductive film formed on the gate insulating film and the isolation insulating film, the first conductive film, the isolation insulating film, and impurities. Provided is a semiconductor device having element isolation trenches that are formed by penetrating and separating the diffusion layers, respectively, and are formed in the direction perpendicular to the substrate surface and are filled with an insulating material.

In order to achieve the above object, the present invention further comprises a step of forming a plurality of impurity diffusion layer lines extending along the semiconductor substrate, and an isolation insulating film on the region of the impurity diffusion layer lines. A step of forming a gate insulating film in a region between the impurity diffusion line layers, a step of forming a first conductive film that covers the gate insulating film and the isolation insulating film, and a step of forming a first conductive film on the first conductive film. A step of forming an etching resistant layer on the substrate, a step of patterning the etching resistant layer, and the first conductive film using the patterned etching resistant layer as a mask,
A step of etching the isolation insulating film and the substrate to form an element isolation groove for dividing the impurity diffusion layer line into the substrate to form a source line and a drain line, and a step of filling the element isolation groove with an insulating material. A method for manufacturing a semiconductor device is provided.

The semiconductor device of the present invention has a structure in which the substrate and the first conductive film are opposed to each other with the gate insulating film interposed therebetween, and the diffusion layer is formed under the isolation insulating layer on both sides of the gate insulating film. The element isolation is performed between the elements by an element isolation groove (trench) dug in the substrate through the first conductive film, the isolation insulating film, and the diffusion layer.

Therefore, since the elements that need to be separated are separated by the trench isolation having a high reverse breakdown voltage and a punch through breakdown voltage and a small isolation width, the integration degree is improved while ensuring the reverse breakdown voltage and the punch through breakdown voltage. be able to. In addition, since it is possible to use a method in which trench isolation is adopted only in a memory region having a small isolation width and LOCOS is used in a peripheral circuit or the like that requires a wide isolation width, it is difficult to fill a wide groove. Different processes can be avoided and cost rise can be prevented.

Further, a method of manufacturing a semiconductor device according to the present invention
First, the source and drain regions of adjacent elements that require element isolation are formed as common wide impurity diffusion layer lines under the isolation trenches. Then, the first conductive film that covers the gate insulating film and the isolation insulating film is patterned to perform isolation. At the same time, the etching-resistant film used here is used to penetrate the isolation insulating film in the same pattern and perform etching to the substrate to form an element isolation trench (trench) in the substrate.
Is formed, and the impurity diffusion layer line formed on the substrate is divided by the element isolation groove to form a source line and a drain line.

Therefore, the trench isolation having a high inversion breakdown voltage and punch-through breakdown voltage and a small isolation width can be formed in a self-aligned manner simultaneously with the patterning of the first conductive film, so that the memory cell area can be increased by an extremely easy process. It is possible to surely perform element isolation without performing the above. In addition, a trench isolation is adopted only for a memory region having a small isolation width, and a LOCO is used for a peripheral circuit requiring a wide isolation width.
Since S can be adopted, it is possible to avoid a difficult process of filling a groove having a wide separation width, and suppress an increase in cost.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiments of the present invention will be specifically described below, but the present invention is not limited to the following embodiments. FIG. 1 shows one embodiment of a semiconductor device of the present invention, which is an example applied to a separated source type.
(A) is sectional drawing, (b) is a top view, (a) is sectional drawing which followed the AA line of (b). The circuit is shown in FIG.

Explaining the cross-sectional structure of this semiconductor device,
A gate insulating film 21 having a thickness of about 10 nm is formed on the surface of the substrate 10.
And the isolation insulating film 23 having a film thickness of about 30 to 100 nm is formed on both sides of the isolation insulating film 23. Substrate 1 under isolation insulating film 23
Impurity diffusion layers (source and drain) 12 and 13 are formed at 0. Further, the first conductive film 31 is laminated on the gate insulating film 21 and the isolation insulating film 23 to form a floating gate. An element isolation groove 40 is formed in the substrate in the region where the first conductive film 31, the isolation insulating film 23, and the impurity diffusion layers 12 and 13 are isolated. The element isolation trench 40 has an oxide film 25 formed on its inner wall and is filled with an insulating material 26. The upper surface of the insulating material 26 has substantially the same height as the element isolation trench 40. Further, the channel stop 14 is formed on the substrate below the element isolation groove 40 to complete isolation. ON for covering the first conductive film 31
The O film 27 is formed, which allows the first conductive film 3 to be formed.
1 is insulated from the surroundings. A second conductive film 32 is formed on the ONO film 27, and the second conductive film 32 constitutes a control gate.

Next, the plane structure will be described. The second conductive film 32 extends in the horizontal direction of the drawing to form the word line WL. Further, the bit line BL (drain 12) and the source line SL (source 13) are arranged in parallel and extend orthogonally to the word line WL. Word line WL and gate insulating film 21
Memory transistors MTr1 to MTr at the intersection of
4 is formed, and the floating gate 31 is provided below the word line WL of the memory transistor. The trench isolation TI (element isolation trench 40) separates the source line SL and the bit line BL from each other and separates the memory transistors adjacent to each other in the word line WL direction. On the other hand, the memory transistors arranged vertically in the drawing share the bit line BL and the source line SL.

Explaining the circuit of FIG. 2, a pair of source lines SL and a bit line (drain) BL are arranged in parallel, and a memory transistor sharing the pair of source lines SL and bit lines BL (MTr2 in the drawing). A plurality of MTr4 and MTr1 and MTr3) are provided along the source line SL and the bit line BL. The word line WL is provided orthogonally to the bit line BL, and each constitutes a control gate of each memory transistor. Further, memory transistors in the word line WL direction (columns orthogonal to the bit lines) that do not share the source line SL and the bit line BL are separated by an element isolation trench (trench) TI that divides the bit line BL and the source line SL. Has been done.

For writing and erasing data in this memory, for example, data is written by injecting electrons into the floating gates 31 and FG by F-N tunneling using the control gates 32 and WL as a positive bias of about 20 V and using the entire surface of the channel. On the other hand, erasing is performed by pulling out electrons from the floating gate 31 and FG with the control gates 32 and WL as a negative bias.

In the above semiconductor device, the memory devices MTr1 and MTr2 adjacent to each other in the word line WL direction and the MTr are arranged.
Since 3 and MTr4 are trench-separated by the deep element isolation trench 40 and TI, much higher inversion breakdown voltage and punch-through breakdown voltage than in the LOCOS method can be obtained.
Therefore, at the time of writing, even if a high bias voltage is applied to the control gate and WL32, no problem occurs. Also, LOC
Unlike the OS, since there is no bird's beak that expands the isolation region, the element isolation region can be made smaller and the integration degree can be improved.

An example of a method of manufacturing the above-mentioned semiconductor device will be described with reference to FIGS. In each figure, (a) is a sectional view and (b) is a plan view. First, as shown in FIG.
A pad oxide film 21 and then a silicon nitride film 22 are deposited on the silicon substrate 10 and patterned by using a photolithography technique and a dry etching method. At this time, polycrystalline silicon may be formed between the pad oxide film 21 and the silicon nitride film 22 in order to relax the stress of the silicon nitride film 22. Before this step, LOCOS is formed in the circuit portion other than the memory cell such as the peripheral circuit. Then, phosphorus or arsenic is ion-implanted using the silicon nitride film 22 as a mask to form the impurity diffusion layer line 11. The impurity diffusion layer line 11 is later divided by an element isolation groove to form a source and a drain.

Next, as shown in FIG. 4, the silicon nitride film 22 is used as a mask for thermal oxidation to form an oxide film (isolation insulating film).
23 are formed. The thickness of the oxide film 23 may be such that electrons do not tunnel. Specifically, it is preferably thinner than the usual LOCOS thickness and about 30 to 100 nm. The impurity diffusion layer line 11 is buried under the oxide film 23 to form a buried diffusion layer.

Then, as shown in FIG. 5, after the silicon nitride film 22 and the pad oxide film 21 are peeled off, they are thermally oxidized to form a tunnel oxide film 24 with a film thickness of, for example, about 10 nm. After that, as shown in FIG. 6, a first conductive layer 31 to be a floating gate is deposited by a polycrystalline silicon CVD method or the like. Next, the resist R1 is applied by spin coating or the like, the resist R1 is patterned by using photolithography, and then the first conductive layer 31 is patterned using the resist R1 as an etching resistant layer. At this time, FIG.
As shown in (b), the width direction central portion of the oxide film 23 is etched in the extending direction of the impurity diffusion layer line 11 without cutting in the extending direction of the impurity diffusion layer line 11 (BB direction in the drawing). .

Then, in the present invention, as shown in FIG. 7, the oxide film 23 and the substrate 10 are continuously etched using the resist R1 as a mask to form an element isolation groove (trench) 40 in the substrate. To do. As a result, the impurity diffusion layer line 11 is divided by the separation groove 40, and the source line 12 and the bit line 13 are formed in a self-aligned manner.

After forming the element isolation trench 40, if necessary, ion implantation is performed to form the channel stop 14. In this case, in the present embodiment, since the source and the drain are continuous, it is not necessary to ion-implant the side wall of the separation groove from the viewpoint of side wall inversion, and it is preferable to form the channel stop 14 only on the bottom surface.

Next, as shown in FIG. 8, thermal oxidation is performed,
After forming the thermal oxide film 25 on the inner wall of the separation groove 40, CVD
An insulating film 26 such as silicon oxide is deposited by a method such as
Fill 0 with insulating material. Then, as shown in FIG. 9, the floating gate 2 is formed by etching back the insulating film 26.
3 is exposed and the insulating film 26 is left in the isolation trench 40. At this time, the floating gate 2 is increased by increasing the etching amount.
It is preferable to expose the side surface of the floating gate 3 and the surface area of the floating gate 23 can be increased, so that the coupling ratio becomes advantageous. In addition, to ensure insulation,
The surface of the insulating film 26 that fills the isolation trench after the etch back needs to be higher than the surface of the silicon substrate 10, but since there is a margin for the thickness of the oxide film 23, control is easy. The thickness of the oxide film 23 should be selected also from this viewpoint.

Next, returning to FIG. 1, for example, the thickness is 20 nm.
After forming the ONO film 27 to a certain extent, the polycrystalline silicon 32 to be the control gate is deposited. After forming a resist film, the resist film is patterned and the polycrystalline silicon film 32 for control gates, the ONO film 27, and the polycrystalline silicon 31 for floating gates are etched at one time using the resist film as a mask. Further, boron ions are implanted using the same resist film as a mask to separate the memory cells adjacent in the bit line 13 direction. As a result, a memory cell region having a structure as shown in FIG. 1 can be obtained.

In FIG. 1B, one memory cell is shown by a broken line. Assuming that the minimum dimension is F, when the memory cells are arranged at the minimum pitch, a very small value of 6F ² is obtained. According to this manufacturing process, the isolation trench is formed in a self-aligned manner with the same mask used for forming the floating gate, so that element isolation can be performed without increasing the memory cell area. Further, in the above method, the LOCOS isolation method and the trench isolation method can be used together, and the LOCOS method is used for a portion having a large isolation width such as a peripheral circuit, and the trench isolation is used only for a narrow portion in the memory cell. It is not necessary to use a difficult and complicated process of filling a wide area, such as bias ECR CVD, CMP (chemical mechanical polishing), selective epitaxial growth, etc., and element isolation can be performed by an extremely easy process.

Although the element isolation trench 40 has a cross-sectional shape which is vertically etched to form a substantially rectangular shape in the above example, as shown in FIG. 10, it has a reverse taper shape in which the width gradually increases toward the bottom surface. But it's okay. In FIG. 10, the same members as those described above are designated by the same reference numerals. In the case of a normal trench, in order to avoid electric field concentration, it is preferable to form a taper shape in which the width becomes gradually narrower toward the bottom surface. However, the isolation trench in the present invention avoids ion implantation for channel stop on the sidewall of the isolation trench. From the viewpoint, it is preferable that the separation groove has a rectangular cross section or a taper shape in which the bottom surface is wider. The separation groove having such a shape can be formed, for example, by controlling the gas ratio of etching gases (for example, Cl ₂ and N ₂ ).

Further, in the above description, an example of application to the separated source type is shown, but the semiconductor device of the present invention is not limited to this, and can be applied to a semiconductor device having a structure as shown in FIG. 11, for example. Is. In the semiconductor device shown in FIG. 11, a gate insulating film 21 is formed on the surface of the semiconductor substrate 10, and isolation insulating films 23 are formed on both sides of the gate insulating film 21. Impurity diffusion layers 12 and 13 are formed on the lower surface of the isolation insulating film 23, and a first conductive film 31 is formed on the gate insulating film 21 and the isolation insulating film 23. Further, penetrating the first conductive film 31 and the isolation insulating film 23,
An element isolation groove 40 is formed in a direction perpendicular to the substrate surface, and the element isolation groove 40 is filled with an insulating material 26.

Next, the present invention is applied to MNOS (Metal Nitride).
An example of application to an Oxide Semiconductor type EEPROM will be described. For example, as shown in FIG. 12, the MNOS structure has a structure in which, for example, a silicon nitride film (trap insulating layer) 28 and a silicon oxide film 29 are laminated on a gate oxide film 21, and polysilicon and aluminum are formed thereon. The gate electrodes 33 are laminated. In writing and erasing, a high voltage is applied to the gate insulating film 21 to cause a tunnel current to flow and the silicon nitride film to capture electrons.

This structure can be realized by the above process. For example, the processes up to the process shown in FIG. 9 can be the same. However, the first conductive film 31 is used to protect the oxide film 23,
Since it will be removed by etching later, other than polysilicon may be used. In this case, if an ONO film is formed instead of the first conductive film 31, the ONO film is also etched at the same time when the element isolation trench 40 is filled with the insulating material 26 and is etched back. Further, if the element isolation trenches 40 are formed by only the pattern of the resist film without forming the first conductive film 31, the oxide film 2 is also removed when the element isolation trenches 40 are etched back by the insulating material 26.
3 is etched. Therefore, the first conductive film 3
Some protective film such as 1 is required. The film thickness of the gate oxide film (tunnel oxide film) may be thinner than 10 nm.

The state shown in FIG. 9, that is, the first conductive film 31.
Is patterned to form the element isolation trench 40, and then the polysilicon film 31 is removed from the state where the element isolation trench 40 is filled with the insulating material 26. Then, as shown in FIG.
After the film is formed to a thickness of about nm, the silicon nitride film 28 is thermally oxidized to form a silicon oxide film 29 to a thickness of about 4 nm. The step of forming the silicon oxide film 29 may be omitted. After that, a gate electrode film 33 made of polysilicon or aluminum is formed. Then, the gate electrode film 33, the silicon oxide film 29, and the silicon nitride film 28 are patterned by etching to obtain MNOS as shown in FIG.

[0041]

The semiconductor device of the present invention has a high reverse breakdown voltage and a punch through breakdown voltage, and also has an element isolation region having a small occupied area. Further, according to the method of manufacturing a semiconductor device of the present invention, such a semiconductor device can be manufactured easily and reliably.

[Brief description of drawings]

FIG. 1 shows an example in which a semiconductor device of the present invention is applied to a flash memory, (a) is a sectional view and (b) is a plan view.

FIG. 2 is a circuit diagram of the semiconductor device shown in FIG.

3A and 3B show an example of a manufacturing process of a semiconductor device of the present invention, in which FIG. 3A is a sectional view and FIG. 3B is a plan view.

4A and 4B show a step that follows FIG. 3, in which FIG. 4A is a cross-sectional view and FIG. 4B is a plan view.

5A and 5B show a step that follows FIG. 4, in which FIG. 5A is a cross-sectional view and FIG. 5B is a plan view.

6A and 6B show a step that follows FIG. 5, in which FIG. 6A is a cross-sectional view and FIG. 6B is a plan view.

FIG. 7 shows a step that follows FIG. 6, in which (a) is a cross-sectional view and (b) is a plan view.

FIG. 8 shows a step that follows FIG. 7, in which (a) is a cross-sectional view and (b) is a plan view.

9A and 9B show a step that follows the step of FIG. 8, in which FIG. 9A is a cross-sectional view and FIG. 9B is a plan view.

FIG. 10 is a cross-sectional view showing a modified example of the semiconductor device of the present invention.

FIG. 11 is a cross-sectional view showing a general structure of a semiconductor device of the present invention.

FIG. 12 is a cross-sectional view showing the structure of an MNOS type nonvolatile memory.

FIG. 13 is a cross-sectional view showing an example in which the present invention is applied to MNOS.

14A to 14G are flowcharts for explaining a conventional process for manufacturing a flash memory with sectional views.

15A to 15E are flowcharts for explaining the process of FIG. 12 in a plan view.

16 is a circuit diagram of the flash memory shown in FIGS. 12 and 13. FIG.

[Explanation of symbols]

10 ... Substrate, 11 ... Impurity diffusion layer line, 12 ... Source line,
13 ... Bit line (drain line), 14 ... Channel stop, 23 ... Isolation insulating film, 24 ... Gate insulating film (tunnel oxide film), 27 ... ONO film, 28 ... Silicon nitride film (trap insulating layer), 29 ... Silicon oxide film, 31
... first conductive film (floating gate), 32 ... second conductive film (control gate), 40 ... isolation trench, WL ... word line, BL ... bit line, SL ... source line, MTr1-MTr4 ... memory transistor, TI ... Separation groove.

Claims (7)

[Claims] 1. A semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, isolation insulating films formed on both sides of the gate insulating film, and impurity diffusion formed on the substrate below the isolation insulating film. The layer, the first conductive film formed on the gate insulating film and the isolation insulating film, and the first conductive film, the isolation insulating film, and the impurity diffusion layer, each of which is divided and penetrates, and is perpendicular to the substrate surface. A semiconductor device having an element isolation groove formed in the substrate and filled with an insulating material. 2. The impurity diffusion layer divided by the element isolation groove constitutes a source line and a drain line of a non-volatile memory element, and a non-volatile memory element which shares these is arranged along the source line and the drain line. The semiconductor device according to claim 1, which is provided. 3. The semiconductor device according to claim 1, wherein the element isolation groove has a substantially rectangular shape or a cross-sectional shape in which the width gradually increases toward the bottom. 4. A semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, isolation insulating films formed on both sides of the gate insulating film, and impurity diffusion formed on the substrate below the isolation insulating film. Layer, the isolation insulating film, and the impurity diffusion layer, which are separated from each other and penetrate through the isolation insulating film and the impurity diffusion layer, are formed in the direction perpendicular to the substrate surface, and are filled with an insulating material, and the trap insulation formed on the gate insulating film. A semiconductor device having a layer and a conductive film formed over the trap insulating layer. 5. A step of forming a plurality of impurity diffusion layer lines extending along each other on a semiconductor substrate, a step of forming an isolation insulating film on a region of the impurity diffusion layer lines, A step of forming a gate insulating film in the region, a step of forming a first conductive film that covers the gate insulating film and the isolation insulating film, a step of forming an etching resistant layer on the first conductive film, A step of patterning the etching resistant layer, and by etching the first conductive film, the isolation insulating film and the substrate by using the patterned etching resistant layer as a mask, the impurity diffusion layer line is divided into the substrate to form the source line and the drain. A method of manufacturing a semiconductor device, comprising: a step of forming an element isolation groove for forming a line; and a step of filling the element isolation groove with an insulating material. 6. A step of forming an insulating film and a second conductive film on the patterned first conductive film, and then patterning the first conductive film, the insulating film, and the second conductive film at a time. 5. The method for manufacturing a semiconductor device according to 5. 7. The method of manufacturing a semiconductor device according to claim 5, wherein impurities are introduced into the substrate at the bottom of the element isolation groove after forming the element isolation groove.