JPH09321590A - Variable delay line circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable delay line circuit in which an optional delay with high accuracy is realized by suppressing the effect of dispersion in the manufacturing process and the effect attended with fluctuation in the ambient temperature and a power supply voltage. SOLUTION: A delay circuit group 104 includes a plurality of stages of delay circuits having two output systems in cascade connection. A delay characteristic detection circuit 101 detects reference data R designating the number of stages of the delay circuits delaying an input signal IN by a prescribed time. A control circuit 102 updates control data D designating number of stages of the delay circuits delaying the input signal IN by the time corresponding to delay amount designation data U by reference data R. A selection circuit 105 receives an output of each delay circuit to select an output based on the reference data R and provides an output to the delay characteristic detection circuit 101. A selection circuit 106 receives the output of each delay circuit to select an output based on the control data D and provides an output of an object delay signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay line circuit that delays an input signal according to external control data and outputs the delayed signal, and more particularly to an ASIC such as a gate array.
The present invention relates to a variable delay line circuit realized by (application-specific IC).

[0002]

2. Description of the Related Art VGA (Video Graphics Array) output from a personal computer or the like to a monitor device
When a video signal based on a signal output standard such as SVGA, which is a signal output standard that is upwardly compatible with VGA, etc., is taken into an external liquid crystal monitor device, a pixel frequency corresponding to each signal output standard is used. The video signal may need to be sampled.

In this case, if the phases of the sampling clock and the video signal are not optimally adjusted, the video signal cannot be accurately sampled, and as a result of sampling, the jitter or fluctuation in the signal amplitude level of the video signal is detected. Such symptoms may appear.

Therefore, in order to adjust the phase between the sampling clock and the video signal, a variable delay line circuit that can change the delay amount of an input signal in accordance with an external control signal is required.

FIG. 5 is a schematic block diagram showing the overall configuration of a conventional variable delay line circuit 500. Variable delay line circuit 5
A delay circuit group 00 receives an input signal IN to be delayed and outputs a plurality of delay signals having different delay times, and a plurality of delay signals from the delay circuit group 501 and an externally applied delay. And a decoding circuit 502 which selects and outputs a target delay signal based on the quantity designation data UX.

Delay circuit group 501 includes a plurality of cascaded delay circuits, for example, inverter circuits A _{1 to} A _N.
including. The inverter circuit A ₁ receives the input signal IN as an input, and each of the inverter circuits A _{2 to} A _N in the subsequent stage receives the output of the inverter circuit A _{1 to} A _{N−1 in} the previous stage as an input. The outputs of the inverter circuits A _{1 to} A _N are input to the decoding circuit 502 in parallel.

Each of the inverter circuits A _{1 to} A _N delays and outputs the input signal for a fixed period. This period is the same for each of the inverter circuits A _{1 to} A _N.

Next, the operation of the variable delay line circuit 500 will be described.
Briefly explained. First stage inverter circuit A₁Input to
When the signal IN is input, the input signal IN stays
It is delayed and output as a delayed signal. This delayed signal is
Sequential inverter circuit A_Two~ A _NTransmission while receiving a delay at
Will be done.

The decode circuit 502 decodes the delay amount designation data UX input from the outside, selects a target delay signal from the delay signals output from the inverter circuits A _{1 to} A _N , and outputs the selected delay signal. To do.

Therefore, by changing the value of the delay amount designation data UX, it is possible to delay the input signal IN by an arbitrary amount and take it out as the delay signal OUT.

However, this variable delay line circuit 500
In the configuration, the delay amount of the finally output delay signal OUT is greatly affected by variations in performance of the delay circuits A _{1 to} A _N and drift of delay characteristics.

For example, taking the case where the variable delay line circuit 500 is composed of a gate array as an example, the delay amount is generally expressed by the following equation.

[0013] (delay) = (standard delay) × Kt × Kv × Kp ... (1) where, Kt, Kv and Kp, the temperature coefficient respectively for the delay times of the delay circuits A ₁ to A _N, the voltage A coefficient and a process coefficient.

Representative values of these coefficient values are shown in FIG. FIG. 6A shows a change of the temperature coefficient Kt with respect to the external environment temperature, FIG. 6B shows a change of the voltage coefficient Kv with respect to the power supply voltage, and FIG. 6C shows a process variation of the process coefficient Kp (for example, daily variation, etc.). ) Shows the maximum and minimum values, respectively.

Based on the variation of each coefficient shown in FIG. 6, the variation of the delay amount of the variable delay line circuits formed on the cells of the same gate array is the same even if there is no process variation. When the temperature changes from 25 ° C. to 75 ° C., it increases about 13%, and when the power supply voltage changes from 5.0V to 4.5V, it increases about 9%.

Further, if a factor of the process coefficient Kp is added to this variation, the variation in the delay amount between the cells of each gate array may be doubled or more at the maximum.

[0017]

[SUMMARY OF THE INVENTION That is, the configuration of a conventional variable delay line circuit 500 shown in FIG. 5, even when implemented on ASIC, the characteristic variation or delay of the respective delay line circuits A ₁ to A _N It is difficult to accurately obtain a target delay amount due to the influence of characteristic drift and the like, and it is difficult to adopt the variable delay line circuit 500 for applications in which particularly high accuracy is required.

To solve this problem, a variable delay line circuit 600 shown in FIG. 7 has been proposed (Japanese Patent Application No. 8-10).
2633) is not yet known.

FIG. 7 is a schematic block diagram showing the entire structure of the variable delay line circuit 600. 7, the variable delay line circuit 600 includes a signal delay circuit 601, a signal generation circuit 602, a delay amount detection circuit 603, and a switching circuit 60.
4, a control circuit 605, a waveform complementing circuit 606, and a switching circuit 607.

The signal delay circuit 601 delays the input signal IN by a predetermined time and outputs it, under the control of the outside.

The signal delay circuit 601 includes a delay circuit group 6
08 and a selection circuit 609, and has the same configuration as the variable delay line circuit 500 shown in FIG.

The signal generation circuit 602 is a signal delay circuit 60.
A reference signal M for monitoring the delay amount of 1 and various control pulses are generated.

The signal generating circuit 602 includes a crystal oscillator circuit 610 for generating an internal clock signal and a reference signal generating circuit 61 for generating a reference signal M based on the internal clock signal.
Including 1 and.

The delay amount detection circuit 603 includes a signal delay circuit 6
The reference data R for controlling the signal delay circuit 601 necessary for delaying the reference signal M by a predetermined time is output via 01.

The switching circuit 604 receives the input signal IN and the reference signal M and selectively selects one of them.
Enter 1 That is, the variable delay line circuit 600 receives the signal delay circuit 60 with respect to the input signal IN to be delayed.
The reference signal M for monitoring the delay amount of 1 is time-divisionally interrupted and input.

The waveform complementing circuit 606 receives the input signal IN and outputs a complementary signal of a predetermined level.

Switching circuit 607 receives the outputs of signal delay circuit 601 and waveform complementing circuit 606 and selectively outputs one of the signals.

The control circuit 605 receives the delay amount designation data UY and the reference data R input from the outside and outputs the control data D, and the signal delay by switching the reference data R and the control data D. And a switching circuit 613 for outputting to the circuit 601.

In the arithmetic unit 612, the input signal I
In order to delay N by the time corresponding to the delay amount designation data UY input from the outside, the reference signal M is actually delayed for a predetermined time, and the delay amount is calculated based on the reference data R which is the required delay amount. The designated data UY is corrected and output as control data D.

That is, in the variable delay line circuit 600, the influence of the characteristic variation and drift of the delay circuit group 608 is detected by using the reference signal M, and the reference data R as the result is detected by the delay amount with respect to the input signal IN. The above problem is solved by reflecting it in the control of.

However, the variable delay line circuit 600 is configured to input the reference signal M by utilizing the inactive state of the input signal IN in order to detect the variation and drift of the characteristics of the delay circuit group 608. There is.

Therefore, when the duty ratio of the input signal IN is near 50%, it is difficult to multiplex the input signal IN and the reference signal M and selectively control the reference signal M and the input signal IN. is there.

That is, in the variable delay line circuit 600, there arises a problem that the input signal IN can be applied only to a horizontal synchronizing signal having a relatively biased duty ratio.

Therefore, the variable delay line circuit 70 shown in FIG.
0 has been proposed (Japanese Patent Application No. 8-102633), and here, a configuration is applicable in which the input signal IN is applicable even when the duty ratio is near 50%.

FIG. 8 shows such a variable delay line circuit 700.
3 is a schematic block diagram showing the overall configuration of FIG.

In FIG. 8, the same parts as those of the variable delay line circuit 600 shown in FIG. 7 are designated by the same reference numerals and the description thereof will be omitted.

The variable delay line circuit 700 is different from the configuration of the variable delay line circuit 600 shown in FIG.
Instead of 01, a signal delay circuit 701 is included.

The signal delay circuit 701 includes delay circuit groups 702 and 7 for inputting an input signal IN and a reference signal M, respectively.
03 and selection circuits 704 and 705 that receive the outputs of the delay circuit groups 702 and 703, respectively.

Therefore, since the configurations for delaying the input signal IN and the reference signal M exist independently of each other, even if the input signal IN is in the vicinity of the duty ratio of 50%, the variable shown in FIG. The problem in delay line circuit 600 does not occur.

However, since the variable delay line circuit 700 has the delay circuit groups 702 and 703 of two systems, variations in the performance of the delay line circuit groups 702 and 703 and relative differences in the delay characteristic drifts pose new problems. Become.

Further, the variable delay line circuit 700 is connected to one A
When trying to realize on SIC, delay circuit group 7 of 2 systems
Since 02 and 703 are included, there is a problem that the circuit scale increases and the cost also increases.

Therefore, the present invention has been made in order to solve the above-mentioned problems, and its purpose is to provide an input signal having a biased duty ratio as well as a duty ratio of 5%.
Provided is a variable delay line circuit capable of highly accurate variable delay operation by suppressing the influence of variations in performance of delay circuits included in the delay circuit group and delay characteristic drift even with respect to an input signal near 0%. It is to be.

Another object of the present invention is to provide a variable delay line circuit capable of realizing a highly accurate delay even on an inexpensive ASIC.

[0044]

According to another aspect of the present invention, there is provided a variable delay line circuit which delays an input signal for a target time according to external delay amount designation data and outputs the delayed signal as a delay signal. A delay characteristic detecting means for detecting a delay amount for delaying the input signal for a predetermined time according to a predetermined first timing signal based on the input signal;
Control means for receiving the delay amount designation data and computing and updating control data for delaying the input signal by a target time according to the output result of the delay characteristic detecting means; and the delay characteristic detecting means Signal delay means for feeding back a signal obtained by delaying the input signal according to the output result of the delay characteristic detecting means and delaying the input signal according to the control data to output a target delay signal.

According to another aspect of the variable delay line circuit of the present invention, the delay characteristic detecting means generates the first timing signal, and the second timing is determined by the first data that determines the update time of the control data received from the outside. Timing signal generating means for generating a signal and delay amount detecting means for detecting reference data for controlling the signal delay means necessary for delaying the input signal by a predetermined time each time the first timing signal is received. In addition, the control means selectively outputs the reference data in response to the second timing signal, and the delay amount designating data and the delay amount designating data which are different from each other.
Data from the outside, and a calculation means for calculating control data on the basis of the output of the latch means. And a first selection circuit that receives the outputs of a plurality of stages of delay circuits in parallel, selects the output of any one of the delay circuits according to the reference data, and feeds it back to the delay amount detecting means. A second selection circuit that receives outputs of the delay circuits of a plurality of stages in parallel, selects the output of any one of the delay circuits according to the control data, and outputs a target delay signal.

In the variable delay line circuit according to claim 3, the delay amount detecting means compares the logic level of the reference delay signal output from the first selection circuit with the logic level of the input signal based on the reference data. In response to the output of the comparing means and the comparing means, the reference data is increased or decreased by one unit so that the reference delay signal delays the input signal by a predetermined time, and the first selection circuit and the latch circuit are provided. And detecting means for outputting the reference data, and means for setting the reference data to the initial value each time the first timing signal is received.

According to another aspect of the variable delay line circuit of the present invention, the latch means receives the second timing signal that repeatedly takes two states of the first logic level and the second logic level, and receives the second timing. Means for updating the value of the reference data as the value of its output while the signal is at the first logic level.

In the variable delay line circuit according to the present invention, the arithmetic means receives the output of the latch means, the delay amount designating data and the second data, and multiplies the delay amount designating data by the proportional coefficient to obtain the control data. The proportional coefficient is obtained by dividing the second data by the maximum delay time per stage of the delay circuits of a plurality of stages, and has a means for calculating by dividing the output of the latch means.

In a variable delay line circuit according to a sixth aspect of the present invention, the second data has two levels of a third logic level and a fourth logic level.
For an input signal that repeats one state, it shows the pulse width of the third logic level of the input signal.

A variable delay line circuit according to a seventh aspect is characterized in that the input signal has a constant frequency with a duty ratio of around 50%.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a schematic block diagram showing an entire structure of a variable delay line circuit 100 according to a first embodiment of the present invention.

The variable delay line circuit 100 shown in FIG. 1 receives the input signal IN, detects the delay amount for delaying the input signal IN for a predetermined time in accordance with a predetermined first timing signal P, and outputs a reference value. The delay characteristic detection circuit 101 which outputs as the data R and the delay amount designation data U from the outside are received, and the control data D for delaying the input signal IN by the intended time is calculated based on the reference data R, Upon receiving the control circuit 102 to be updated and the reference data R, the input signal IN
And a signal delay circuit 103 that receives the control data D, delays the input signal IN for a corresponding time, and outputs a target delay signal OUT. Equipped with.

The signal delay circuit 103 includes a delay circuit group 104 for delaying the input signal IN and a first selection circuit 105.
And a second selection circuit 106.

FIG. 2 is a schematic block diagram showing the overall configuration of the signal delay circuit 103 according to the first embodiment.
Components common to those of the conventional variable delay line circuit 500 shown in FIG.

The delay circuit group 104 is different from the conventional delay circuit group 501 shown in FIG. 5 in that there are two systems of outputs from the delay circuit group 104, and correspondingly, the selection circuits 105 and 106 are provided. It is to have two systems.

Here, the first selection circuit 105 selects a delay signal corresponding to the reference data R output from the delay characteristic detection circuit 101 from a plurality of delay signals received from the delay circuit group 104 and having different delay times. Is fed back to the delay characteristic detection circuit 101 as the reference delay signal RS.

The second selection circuit 106 selects the delay signal corresponding to the control data D output from the control circuit 102 from the plurality of delay signals similarly received from the delay circuit group 104 and outputs it as the delay signal OUT. To do.

Delay characteristic detecting circuit 101 includes a timing signal generating circuit 107 and a delay amount detecting circuit 108.

The timing signal generation circuit 107 generates a first timing signal P for controlling the delay characteristic detection circuit 101, and externally receives data QL for determining the update time of the control data D in the latch circuit 109 described later. To generate a second timing signal Q synchronized with the first timing signal P.

Here, the first timing signal P is a repetitive signal having a constant cycle and duty ratio.

On the other hand, the second timing signal Q is a repetitive signal having the same cycle as the first timing signal P and a duty ratio different from that of the first timing signal P.

The delay amount detection circuit 108 receives the control of the first timing signal P, detects the number of stages of the delay circuit group 104 for delaying the input signal IN for a predetermined time, and outputs it as the reference data R. .

Each time the delay amount detecting circuit 108 receives the first timing signal P, it sets the reference data R to an initial value (hereinafter referred to as R ₀ for simplicity). In the following, it is assumed that the reference data R is R ₀ when the first timing signal P is at H level (note that this is not particularly described,
The relationship of the logic levels of the first timing signal P shown below may be reversed).

The delay amount detecting circuit 108 outputs the reference data R to the signal delay circuit 103 and receives the reference delay signal RS obtained by delaying the input signal IN corresponding to the reference data R by a time delay.

Upon receipt of the reference delay signal RS, the delay amount detection circuit 108 compares the input delay signal IN with the reference delay signal RS for a predetermined time, and based on the result,
The reference data R is corrected by increasing or decreasing the reference data R by one.

That is, the delay amount detecting circuit 108 receives the first timing signal P at the H level and sets the reference data R to R ₀ , and thereafter, while the first timing signal P is at the L level, the reference data R is set. Of the reference delay signal RS with the input signal IN and the reference data R accompanying the comparison result
Repeat the correction of.

The control circuit 102 includes a latch circuit 109,
And a calculator 110. Latch circuit 109 selectively outputs reference data R output from delay amount detection circuit 108 according to second timing signal Q received from delay characteristic detection circuit 101.

Specifically, the second timing signal Q is H
The value of the delay reference data RR is sequentially updated with the value of the reference data R every time the level is changed to the L level, and the arithmetic unit 11
It is output to 0 (hereinafter, although not particularly described, this logic level relationship may be reversed). This operation is repeated while the second timing signal Q is at L level. On the other hand, the second
Of the delay reference data R while the timing signal Q of
R is not changed and is output to the arithmetic unit 110.

The arithmetic unit 110 receives the delay amount designation data U and the input signal reference data T from the outside and receives the input signal IN.
Calculates the number of stages of the delay circuit group 104 required for delaying the time corresponding to the delay amount designation data U based on the delay reference data RR, updates as control data D, and outputs it.

Specifically, the arithmetic unit 110 calculates the control data D based on the following formula using the delay amount designation data U, the input signal reference data T and the delay reference data RR received from the outside. .

Z = RR / (T / TMA) (2) D = Z × U (3) If the input signal IN is a repetitive signal with a constant cycle and duty ratio, then the input signal IN Reference data T
Is data indicating the pulse width of the input signal IN, and TM
A is the maximum delay time per stage of each of the delay circuits A _{1 to} A _{N in} the delay circuit group 104.

That is, the calculator 110 compares the delay reference data RR and the input signal reference data T with the maximum delay time TMA.
The delay amount designation data U is corrected and the control data D is calculated according to the ratio Z to that obtained by dividing by. The reason why the input signal IN is delayed with high precision by the time corresponding to the delay amount designating data U and the target delay signal OUT is obtained by setting the control data D in the equation (3) will be described later. .

Based on the above preparations, the operation of the variable delay line circuit 100 shown in FIG. 1 will be described. In the first embodiment, the input signal IN is a rectangular wave with a duty ratio of 50%.

FIG. 3 is a timing chart showing an example of a temporal change of main signal levels used for explaining the operation of variable delay line circuit 100 in the first embodiment.

First, at time t1, the first timing signal P changes from L level to H level.

The delay amount detecting circuit 108 starts from time t1 to t.
During the period 2, the first timing signal P of H level is received,
The reference data R is set to the initial value R ₀ .

From time t2 to t4, the first timing signal P becomes L level. During this period, the delay amount detection circuit 1
08 corrects the reference data R according to the following procedure.

Here, FIG. 4 shows the input signal IN and the reference delay signal R in the delay amount detecting circuit 108 in the first embodiment.
It is a timing chart figure which shows the relationship with S.

In FIG. 4A, the reference delay signal RS
Input signal IN at the time when L level changes to H level
Signal level is H level.

That is, the delayed reference signal RS corresponding to the result of delaying the input signal IN based on the reference data R
Has a delay time shorter than 1/2 cycle of the input signal IN.
In this case, the delay amount detection circuit 108 increments the reference data R by 1.

On the other hand, in FIG. 4B, the signal level of the input signal IN at the time when the reference delay signal RS changes from L level to H level is L level.

That is, the delay time of the reference delay signal RS is longer than the 1/2 cycle of the input signal IN. in this case,
The delay amount detection circuit 108 decrements the reference data R by 1.

That is, when the delay time of the reference delay signal RS is less than 1/2 cycle of the input signal IN, the delay amount detecting circuit 108 increases the delay time by 1 of the input signal IN. If it exceeds / 2 cycle, the reference data R is changed so as to reduce the delay time. Finally, the reference data R is stable at a value in which the reference delay signal RS is delayed by 1/2 cycle with respect to the input signal IN. Here, for simplicity, this stable value is referred to as R (i). The i means that the i-th first timing signal P is received.

At time t4, the first timing signal P shifts from the L level to the H level, and the delay amount detecting circuit 108
Sets the reference data R to R ₀ again and detects a stable value after time t5.

Here, the reference delay signal RS is the input signal I
3/2 cycle, 5/2 cycle, or (1/2
+ N) cycles (where n is a positive number), the first timing signal P is a repetitive signal.
At the next first timing signal P, the reference data R is refreshed. That is, the first timing signal P is
The reference data R is prevented from being continuously set to an incorrect fixed value.

On the other hand, the second timing signal Q is the time t
It becomes H level from 1 to t3 and from time t4 to t6, and becomes L level from time t3 to t4.

At time t3, the second signal is changed from the H level to the L level.
When the timing signal Q of the state transitions, the latch circuit 1
09 outputs the value of the reference data R as delayed reference data RR. In this case, the value of the reference data R becomes the stable value R (i) by sufficiently setting the time t1 to t3.

From time t4 to t6, the latch circuit 109
Does not change the value of the delay reference data RR.

When the second timing signal Q transits from H level to L level again at time t6, the latch circuit 109 changes the value of the delay reference data RR to the reference data R
Update to the value of. In this case, the value of the reference data R is the stable value R (i + 1).

That is, the latch circuit 109 detects the L level of the second timing signal Q and sets the value of the reference data R as the delay reference data RR, so that the value of the delay reference data RR is always the reference data. The value is updated to the latest stable value of R and output.

Here, the pulse width of the second timing signal Q is determined by the data QL received from the outside, and is set to a time width such that the reference data R can reach a stable value sufficiently.

As described above, the arithmetic unit 110 calculates and outputs the control data D using the delay reference data RR based on the following formula.

Z (i) = RR (i) / (T / TMA) (4) D (i) = Z (i) × U (5) Here, RR (i) means R (i). ), Z (i) is the i-th proportional coefficient using RR (i), D (i) is the i-th control data D using Z (i). Refers to.

In the equation (4), (T / TMA)
Is the delay circuit A₁~ A_NDelay time per stage is delayed
Maximum value TMA (that is, the delay per delay circuit stage)
In the case of no change in time), the time T
In the form 1, it corresponds to 1/2 cycle of the input signal IN)
Delay circuit A required to delay the input signal IN
₁~ A_NRR (i) is actually time T
Indicates the number of stages required to delay the input signal IN.
You.

That is, the arithmetic unit 110 corrects the delay amount designating data U, which is the number of stages, which is input as the delay time per stage of the delay circuit does not change, by the equation (5), so that the delay The number of stages D (i) required in the circuits A _{1 to} A _N is calculated.

Here, when the delay time per stage of the delay circuits A _{1 to} A _N is TMA, the delay reference data RR
Becomes RRM, and as a result, DM is obtained as the value of the control data D, the delay time difference Δdm of the delay signal OUT with respect to the input signal IN is expressed as follows.

Δdm = TMA × DM (6) That is, using equations (2) and (3), Δdm = TMA × [RRM / (T / TMA) × U] (7) where the delay circuit Consider a case where the delay time per stage of A _{1 to} A _N changes to 1 / k of TMA due to various factors described later. In this case, the value of the obtained delay reference data is R
If it is RK, the delay time difference Δdk of the delay signal OUT with respect to the input signal IN is expressed as follows.

Δdk = TMA × (1 / k) × [RRK / (T / TMA) × U] (8) Here, 1 / k takes an arbitrary value from 0.25 to 1.

By the way, the relationship between RRK and RRM is expressed as follows. RRK = RRM × k (9) Therefore, according to equations (7), (8), and (9), Δdk
And Δdm have the following relationship.

Δdk = Δdm (10) That is, as shown in Expression (1), the conventional variable delay line circuit 500 receives a change in environmental temperature or power supply voltage, and
Although there was a problem that the delay time of the target delay signal fluctuates, the variable delay line circuit 10 according to the first embodiment
As shown in the equation (10), 0 indicates that the delay time of the delay signal with respect to the arbitrary delay amount designation data U is the delay circuits A _{1 to} A
_It does not change even when the delay time per _N stage changes.

Therefore, the variable delay line circuit 100 can realize an arbitrary delay without considering changes in the environmental temperature and the power supply voltage.

Further, the variable delay line circuit 100 according to the first embodiment delays the input signal IN by the delay circuit group 104 for a predetermined time, and as a result, the performance existing in the delay circuit group 104 depends on the required number of stages. The effects of variations and drifts are corrected by detecting the effects of variations and drifts of delay characteristics and reflecting the results in the control for delaying the input signal IN to obtain the target delay signal. are doing.

That is, the variable delay line circuit 100 uses the input signal IN as a reference signal in order to detect variations in performance and delay characteristic drift of the delay circuits A _{1 to} A _N. Therefore, in the conventional variable delay line circuit 600, the crystal oscillation circuit 610 required for generating the reference signal different from the input signal IN becomes unnecessary in the variable delay line circuit 100.

In the first embodiment, a signal having a duty ratio of 50% has been described as an example of the input signal IN, but the present invention can be applied even if the input signal IN is a signal having a biased duty ratio.

[0105]

As described above, according to the present invention, a variable delay line circuit that delays an input signal for a desired time and outputs it as a delayed signal in accordance with external delay amount designation data is used. It is possible to output a highly accurate delay signal even when there is a variation in performance due to a variation in the manufacturing process of the delay circuit that constitutes the line circuit or a drift in the delay characteristic due to an external power supply voltage, environmental temperature, etc. .

Further, by forming the circuit elements forming the variable delay line circuit on the ASIC, it is possible to greatly reduce the number of parts and provide a highly accurate and inexpensive variable delay line circuit.

[Brief description of drawings]

FIG. 1 is a schematic block diagram illustrating an overall configuration of a variable delay line circuit according to a first embodiment.

FIG. 2 is a schematic block diagram showing an overall configuration of a signal delay circuit according to the first embodiment.

FIG. 3 is a timing chart of main signal levels of the variable delay line circuit according to the first embodiment.

FIG. 4 is a timing chart showing a relationship between an input signal and a reference delay signal in the delay amount detection circuit according to the first embodiment.

FIG. 5 is a schematic block diagram showing the entire configuration of a conventional variable delay line circuit.

FIG. 6 is a coefficient correspondence diagram for explaining variation in delay amount of a conventional variable delay line circuit, in which (a) is a temperature coefficient,
(B) shows the power supply voltage coefficient, and (c) shows the process coefficient.

FIG. 7 is a schematic block diagram showing an entire configuration of a conventional variable delay line circuit.

FIG. 8 is a schematic block diagram showing the entire configuration of a conventional variable delay line circuit.

[Explanation of symbols]

100 variable delay line circuit 101 delay characteristic detection circuit 102 control circuit 103 signal delay circuit 104 delay circuit group 105, 106 selection circuit 107 timing signal generation circuit 108 delay amount detection circuit 109 latch circuit 110 arithmetic unit A _{1 to} A _N delay circuit

Claims (7)

[Claims] 1. According to the delay amount designation data from the outside,
A variable delay line circuit that delays an input signal for a desired time and outputs the delayed signal as a delayed signal, for delaying the input signal for a predetermined time according to a predetermined first timing signal based on the input signal. A delay characteristic detecting means for detecting a delay amount, and receiving the delay amount specifying data, and calculating control data for delaying the input signal by a target time according to an output result of the delay characteristic detecting means. To the delay characteristic detecting means, and feeds back a signal obtained by delaying the input signal according to the output result of the delay characteristic detecting means, and inputs the input signal according to the control data. A variable delay line circuit, comprising: a signal delay unit that delays a signal and outputs a target delayed signal. 2. The timing signal generating means, wherein the delay characteristic detecting means generates the first timing signal and also generates a second timing signal based on first data that determines an update time of the control data received from the outside. Means and delay amount detecting means for detecting reference data for controlling the signal delay means necessary for delaying the input signal by the predetermined time each time the first timing signal is received, The control means receives, from the outside, latch means for selectively outputting the reference data according to the second timing signal, and the delay amount designating data and second data different from the delay amount designating data. And a calculation unit that calculates the control data based on the output of the latch unit, wherein the signal delay unit sequentially receives the input signal. A delay circuit group including a plurality of stages of delay circuits connected in cascade and an output of the delay circuits of the plurality of stages are received in parallel, and an output of any one of the delay circuits is selected according to the reference data. A first selection circuit that feeds back to the delay amount detecting means and outputs of the delay circuits of the plurality of stages are received in parallel, and an output of any one of the delay circuits is selected according to the control data. 2. The variable delay line circuit according to claim 1, further comprising a second selection circuit that outputs the delay signal. 3. The delay amount detecting means, comparing means for comparing the logic level of the reference delay signal output from the first selection circuit with the logic level of the input signal based on the reference data, In response to the output result of the comparison means, the reference delay signal is increased or decreased by one unit so that the reference delay signal delays the input signal by the predetermined time, and the first selection circuit and the latch. 3. The variable delay line circuit according to claim 2, further comprising: a detection unit that outputs the reference data to a circuit; and a unit that sets the reference data to an initial value each time the first timing signal is received. 4. The latch means receives the second timing signal that repeatedly takes two states of a first logic level and a second logic level, and the second timing signal is the first logic level. 3. The variable delay line circuit according to claim 2, wherein the value of the reference data is updated as the value of its output during the level. 5. The arithmetic means receives the output of the latch means, the delay amount designating data and the second data, multiplies the delay amount designating data by a proportional coefficient, and outputs it as the control data. However, the proportional coefficient is obtained by converting the second data into one of the delay circuits of the plurality of stages.
The variable delay line circuit according to claim 2, wherein the variable delay line circuit is calculated by dividing the output of the latch means by dividing the maximum delay time per stage. 6. In the input signal, wherein the second data repeatedly takes two states of a third logic level and a fourth logic level, the third data of the input signal is used.
3. The variable delay line circuit according to claim 2, wherein the pulse width of the logic level of is the value. 7. The variable delay line circuit according to claim 2, wherein the input signal has a constant frequency with a duty ratio of around 50%.