JPH09331217A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which the input balance characteristics of a plurality of differential amplifier circuit sections can be improved when the sections are formed on a semiconductor substrate. SOLUTION: The transistors Ta1 to Tb8 of differential input sections 21a to 22b corresponding to each other between operational amplifiers 12a and 12b are arranged in two rows and four columns on a silicon substrate. At the same time, the corresponding transistor Ta1 to Ta4, Ta2 to Ta3, Ta6 to Ta7, Ta5 to Ta8,... are arranged so that each are adjacent to each other in the row direction and transistors Ta1 and Tb1, Ta2 and Tb2,... which become corresponding components between the amplifiers 12a and 12b can become adjacent to each other in the column direction, and then, each closely arranged two transistors Ta1 and Ta2, Ta3 and Ta4,... in each element for input can be arranged in different rows.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a plurality of differential amplifier circuit parts formed on a semiconductor substrate.

[0002]

In an IC (integrated circuit) in which a large number of circuit elements are integrally formed on a semiconductor substrate, stable operation characteristics can be obtained because the characteristics of each circuit element can be easily aligned. it can. For example, in the case of configuring a differential amplifier circuit, variations in the electrical characteristics of the transistors in the input stage greatly affect the output characteristics as an offset voltage, but in the case of an IC, there is an advantage that the characteristics can be easily made uniform. is there.

However, even when the operational amplifier is configured as an IC as described above, when high-precision characteristics are required, characteristic variations caused by various factors in the chips forming the IC are The offset voltage may be adversely affected.

This is because, for example, a mask shift caused by photolithography during the IC manufacturing process,
A deviation of the implantation amount that occurs when introducing impurities into the interior by ion implantation or thermal diffusion, or an uneven distribution of internal stress that occurs when a protective film such as an oxide film is formed,
It is considered that various factors such as variations in the temperature distribution in the plane of the chip are complicatedly entangled with each other, and in reality, some factors of characteristic variations cannot be avoided.

Therefore, conventionally, even when such a variation in the manufacturing process exists as a factor, as an operational amplifier, it is possible to obtain a highly accurate characteristic by preventing the characteristic variation due to the generation of the offset voltage as much as possible. For example, the ones shown in FIGS. 8 and 9 are considered. That is,
In the operational amplifier 1a, a PNP transistor t
The emitters a1, ta2, ta3, and ta4 are connected to the power supply terminal 3a via the constant current source 2a. The bases of the transistors ta1 and ta2 are connected to the inverting input terminal of the operational amplifier 1a, and the transistors ta3 and ta3 are connected to each other.
Each base of a4 is connected to the non-inverting input terminal of the operational amplifier 1a.

The collectors of the transistors ta1 and ta2 are
It is connected to the collectors and bases of NPN type transistors ta5 and ta6, and at the same time is connected to NPN type transistor t.
It is also connected to the bases of a7 and ta8. The collectors of the transistors ta3 and ta4 are the transistors ta7 and t.
It is connected to the collector of a8 and also to the input terminal of the amplification section 4a (see FIG. 9). The emitters of the transistors ta5, ta6, ta7 and ta8 are connected to ground.

In the above configuration, two sets of transistors ta1−ta2 and ta3− each including two transistors as one set.
ta4, ta5-ta6 and ta7-ta8 are operational amplifiers 1 respectively
The differential input sections 5a and 6a as the differential amplifier circuit of a are configured. The operational amplifier 1b has a configuration of the operational amplifier 1a.
Is similar to the above, but is shown with reference numeral “b” added instead of reference numeral “a”. The amplifiers 4a and 4b amplify the input voltages respectively obtained by the operational amplifiers 1a and 1b described above and output the amplified input voltages to the operational amplifier in the next stage.

Conventionally, such an operational amplifier 1a or 1b
In the case of forming a differential amplifier circuit consisting of a semiconductor substrate on a silicon substrate, as shown in FIG.
The positions of the transistors ta1 to ta2 and ta3 to ta4 forming a, and the transistor ta5 forming the differential input section 6a.
The positions of -ta6 and ta7-ta8 on the silicon substrate were arranged to cross each other. Each differential input section 5
By arranging a and 6a in this way, the transistors ta1 to ta8 of the differential input sections 5a and 6a are equally affected by the temperature distribution unevenly distributed on the silicon substrate and the film stress distribution. Therefore, the input balance characteristics of the operational amplifier 1a as a differential amplifier can be improved.

By the way, generally, in the case of constructing a differential amplifier circuit, as shown in FIG. 10, by changing the impedance of the input signal source by setting operational amplifiers 1a and 1b in the input stage respectively and setting the input impedance high. In addition, it is often practiced to amplify these outputs by an operational amplifier 7 provided separately to obtain the outputs.

In such a case, the operational amplifiers 1a and 1b formed by the arrangement on the silicon substrate shown in FIG.
When a differential amplifier circuit is configured by the operational amplifier 1 depending on the position of the heat source or the stress source on the silicon substrate.
There is a problem in that the input balance between the operational amplifiers 1a and 1b may not be achieved due to the fact that either one of a and 1b is close and the other is far.

The present invention has been made to solve the above problems, and
An object of the present invention is to provide a semiconductor integrated circuit device capable of improving the input balance characteristics of a plurality of differential amplifier circuit parts formed on a semiconductor substrate.

[0012]

According to the invention described in claim 1, even when a stress is locally generated on the semiconductor substrate, each input element can be subjected to such stress equally. As a result, it is possible to equalize the characteristic variations that each input element receives according to its stress. Therefore, by offsetting the variation among the input elements in the differential amplifier circuit section as equal, the adverse effect Can be reduced as much as possible, and the adverse effects can be reduced as much as possible by receiving the same stress between the differential amplifier circuit units, and a highly accurate differential amplifier circuit can be provided by using a plurality of differential amplifier circuit units. Even in the case of the configuration, it is possible to suppress the variation of the characteristic and perform the highly accurate amplification operation.

Further, according to claim 2,
The characteristic deviation in the differential amplifier circuit section can be further reduced to enable highly accurate operation, and the characteristic deviation can be further reduced between the plurality of differential amplifier circuit sections by the third aspect. High-precision operation becomes possible.

In addition, according to the present invention, it is possible to optimize the balance between the deviation of the characteristics in each differential amplifier circuit section and the deviation of the characteristics between the differential amplifier circuit sections. As a result, the operation of the integrated circuit as a whole can be made highly precise with less fluctuation.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment in which the present invention is applied to a high precision operational amplifier will be described below with reference to FIGS. FIG. 4 shows an electrical configuration when this high-precision operational amplifier is used in a detection circuit of a pressure sensor. The pressure sensor 10 includes four resistors 11a to 11 on a diaphragm portion formed on a semiconductor chip (not shown).
d is formed, and these are configured in a bridge connection state.

When the diaphragm is distorted by the pressure sensor 10, the resistance values of the resistors 11a to 11d change due to the piezo effect, so that a voltage signal corresponding to the pressure can be taken out as a bridge output. It is a thing. Then, in the pressure sensor 10, each terminal in a bridge connection state has two input terminals 10c and 10d for applying a power source and an output terminal 1 for obtaining a sensor output.
It is provided as 0a and 10b.

Output terminals 10a and 10 of the pressure sensor 10
b is connected to the non-inverting input terminal of the operational amplifier (differential amplifier circuit section) 12a and the non-inverting input terminal of the operational amplifier (differential amplifier circuit section) 12b, respectively. The inverting input terminal of the operational amplifier 12b is connected to the power supply terminal E for generating the reference voltage Vref via the resistor 13 having the resistance value R4, and the output terminal of the operational amplifier 12b is connected to the operational amplifier 12b via the resistor 14 having the resistance value R3. It is connected to the inverting input terminal of.

On the other hand, the inverting input terminal of the operational amplifier 12a is connected to the output terminal of the operational amplifier 12b via the resistor 15 having the resistance value R2, and the output terminal of the operational amplifier 12a is connected to the operational amplifier via the resistor 16 having the resistance value R1. 12a
And the inverting input terminal of the operational amplifier 18 via the resistor 17 having the resistance value R5. The inverting input terminal of the operational amplifier 18 is connected to the output terminal of the operational amplifier 18 via the resistor 19 having the resistance value R6, and the non-inverting input terminal of the operational amplifier 18 is connected to the reference voltage source Vref. The differential amplifier circuit 23 is configured as described above.

The detection output Vo of the pressure sensor 10 obtained by the differential amplifier circuit 23 having the above structure is expressed as follows. First, assuming that the output voltages of the output terminals 10a and 10b of the pressure sensor 10 are Va and Vb, respectively, the output terminal voltages V1 and V2 of the operational amplifiers 12a and 12b, respectively.
Is represented by the following equation.

[Equation 1]

[Equation 2]

The detection output Vo obtained by the differential amplifier circuit 23 is

(Equation 3) Therefore, by substituting the expression (2) into the expression (1) and further substituting it into the expression (3),

(Equation 4) However, Vop1: offset voltage of operational amplifier 12a Vop2: offset voltage of operational amplifier 12b Vop3: offset voltage of operational amplifier 18

Output voltages Va and Vb from the pressure sensor 10
When they are equal, the detection output Vo of the differential amplifier circuit 23 is ideally Vo = Vref. However, in reality, since the offset voltages Vop1 to Vop3 exist, if this case is calculated as Va = Vb in the equation (4), R2 = R3 and R1 = R between the resistance values R1 to R4.
When the condition of 4 is assumed, the following formula is obtained.

(Equation 5)

Here, in general, R1 / R2 is several 10 to one.
Since it is set to about 00, the value indicated by the second term in the equation (5) has a great influence on the input balance characteristic of the differential amplifier circuit 23. Thus, the second of the equation (5)
It can be seen that it is necessary to balance the input characteristics of the operational amplifiers 12a and 12b in order to minimize the influence of the values shown in the section. That is, as described above, since the occurrence of the offset voltages Vop1 and Vop2 cannot be avoided to some extent, it is sufficient to make the values of the two substantially equal.

FIG. 2 is an electrical configuration diagram showing the input stages inside a plurality of operational amplifiers 12a and 12b, for example, a pair of two operational amplifiers. The electrical configuration of these operational amplifiers 12a and 12b is the same as the operational amplifier 1a of the conventional configuration shown in FIG.
1b, the eight transistors which are the input transistors are denoted by "T" instead of "t". In FIG. 2, the collectors of the transistors Ta3 and Ta4 are amplifiers 20a which constitute an amplification output stage.
(See FIG. 1), and the collectors of the transistors Tb3 and Tb4 are connected to the input terminal of the amplifying section 20b (see FIG. 1).

In the operational amplifier 12a, a plurality of, for example, 2
Transistors Ta1-Ta2 and Ta3-Ta4, Ta5-Ta6 which are a pair of input elements in which individual transistors are connected in parallel.
And Ta7-Ta8 form differential input sections 21a and 22a, respectively. Further, in the operational amplifier 12b, the transistors Tb1-Tb2 and Tb3-Tb which are a pair of input elements are used.
4, Tb5-TTb6 and Tb7-Tb8 are respectively connected to the differential input section 2
1b and 22b are configured.

Further, FIG. 1 shows operational amplifiers 12a and 12
b, transistors Ta1 to Ta8 and Tb1 to T
It shows a state in which b8 is arranged as an integrated circuit on a silicon substrate as a semiconductor substrate. Operational amplifier 12a
And 12b, corresponding eight differential input sections 21a and 21b are formed, and the differential input sections 21b and 2 are provided.
The eight transistors forming 2b are arranged in two rows and four columns and concentrated in a predetermined arrangement area, and the transistors are arranged in the upper and lower rows to form the four rows and four columns arrangement.

This arrangement rule is as follows. Transistors Ta1-Ta4 and Ta2-Ta3, Ta6-Ta7 and Ta5-Ta8, Tb1-Tb4 corresponding to the input elements of the respective differential input sections 21a, 22a, 21b and 22b.
And Tb2-Tb3, Tb6-Tb7 and Tb5-Tb8 are arranged so as to be adjacent to each other in the vertical direction (row direction).

Transistors Ta1-Tb1, Ta2-Tb2, which are the corresponding components between the operational amplifiers 12a-12b,
Ta3-Tb3, Ta4-Tb4, Ta5-Tb5, Ta6-Tb6, T
The a7-Tb7 and Ta8-Tb8 are arranged so as to be adjacent to each other in the lateral direction (column direction).

Two adjacent transistors Ta1-Ta2, Ta3-Ta4, Ta5-Ta6, Ta7-T in each input element.
a8 and transistors Tb1-Tb2, Tb3-Tb4, Tb5-T
b6 and Tb7-Tb8 are arranged in different rows.

In addition, the adjacent two in each of the above-mentioned input devices
Arrange so that the distances between the individual transistors are all equal.

According to the arrangement rules as described above, the transistors Ta1 to Ta8 forming the operational amplifiers 12a and 12b,
Tb1 to Tb8 are arranged in a mixed state between both operational amplifiers 12a and 12b.

The temperature characteristic of the offset voltage of each differential amplifier circuit section is generally affected by the temperature itself generated in the chip (silicon substrate), and in addition to the protection characteristic accumulated in the manufacturing process and the like. It fluctuates under the influence of stress such as oxide film. Actually, such a stress may be locally generated, but in the configuration of the present embodiment, such an influence is exerted on each differential amplifier circuit section equally, It is possible to reduce the error in the output voltage Vo due to the generation of the offset voltage shown in the equation (5).

FIG. 3 shows the results of a simulation conducted by the inventors regarding the influence of the above-mentioned stress, which will be described in detail below. In the conventional arrangement shown in FIG. 9 and the arrangement of this embodiment shown in FIG. 1, assuming that the film stress generation source is near the upper left side where the transistors ta1 and Ta1 are arranged, the horizontal axis indicates each transistor. The horizontal distribution position from the reference origin is taken and the vertical axis shows the stress distribution intensity on the silicon substrate. In FIG. 3, a solid line and a broken line are curves showing stress distribution characteristics on the A and B cross sections in FIG. 9 and FIG. 1, respectively.

The stress value σ at the position of each transistor is shown with the reference numeral of each transistor as a subscript, and each differential input section 5 in each of the conventional operational amplifiers 1a and 1b is shown.
The difference in stress values between a and 6a and between 5b and 6b is σop
Let a and σopb be expressed as σopa = σta1 + σta2 − σta3 − σta4 σopb = σtb1 + σtb2 − σtb3 − σtb4 (6) Then, the difference σ of the stress values between the operational amplifiers 1a and 1b is
It is expressed as the difference between σopa and σopb as follows. σ = σopa−σopb = (σta1−σtb1) + (σta2−σtb2) − (σta3−σtb3) − (σta4−σtb4) (7) Also, the difference σ of the stress values between the operational amplifiers 12a and 12b in the present embodiment. Similarly, ′ is expressed by the following equation. σ ′ = (σTa1 −σTb1) + (σTa2 −σTb2) − (σTa3 −σTb3) − (σTa4 −σTb4) ... (8)

Then, the difference between the stress values of the conventional example and the stress value of the present embodiment, σ−σ ′, is calculated. Σ−σ ′ = (σtb3−σtb2) + (σtb4−σtb1) + ( σTa3 −σTb3) − (σTa2 −σTb2) (9) (σta1 = σTa1, σTb1 = σta3, σTb4 = σta2,
σta4 = σTa4) (9) is evaluated. From FIG. 3, the difference between the first and second terms is substantially zero, and the difference Δσ4 of the fourth term is smaller than the difference Δσ3 of the third term. Since σ−σ ′ = Δσ3−Δσ4> 0, it can be seen that the balance characteristic against the stress between the operational amplifiers 12a and 12b is improved as compared with the conventional case.

As described above, according to this embodiment, the operational amplifiers 12a, 12 arranged in the input stage of the differential amplifier circuit 23 are arranged.
The transistors Ta1 to Tb8 of the differential input sections 21a to 22b corresponding to the respective b are collectively arranged on a silicon substrate (chip) in 2 rows and 4 columns, and in the input elements of the differential input sections 21a to 22b, Corresponding transistors Ta1-Ta4 and Ta2-Ta3, Ta6-Ta7 and Ta5-T, respectively.
are arranged so as to be adjacent to each other in the row direction, and transistors Ta1 to Tb1, Ta2 to Tb2, which are corresponding components between the operational amplifiers 12a and 12b are arranged to be adjacent to each other in the column direction, and Two adjacent transistors Ta1-Ta2, Ta3-Ta4, ... In each input element are arranged in different columns.

Therefore, with respect to the temperature distribution and the film stress distribution unevenly distributed on the silicon substrate, the balance characteristics in the differential input sections 21a to 22b are kept well, and the balance characteristics between the operational amplifiers 12a and 12b. Therefore, the input balance characteristics can be improved by arranging the two operational amplifiers 12a and 12b in the input stage to equalize the fluctuations in the offset voltage of the differential amplifier circuit 23 formed as a semiconductor integrated circuit. Can be improved.

Further, according to this embodiment, the two adjacent transistors Ta1 to Ta2 and Ta3 to Ta in each input element are adjacent to each other.
Since the distances between 4, ... Are arranged so as to be the same in all things, the input balance characteristics of the differential amplifier circuit 23 can be further improved by making the overall arrangement balance more uniform.

FIG. 5 shows a second embodiment of the present invention. In the second embodiment, operational amplifiers 12a, 12
As a variation in the case of arranging the transistors Ta1 to Tb8 forming b on the silicon substrate, they are arranged by applying the arrangement rules up to. That is, when the arrangement shown in FIG. 5 is compared with the arrangement shown in FIG. 1 in the first embodiment, the third row and the fourth row are interchanged.
Also according to the second embodiment configured as described above, it is possible to obtain substantially the same effect as that of the first embodiment.

FIG. 6 shows a third embodiment of the present invention. In the third embodiment, as in the second embodiment, the arrangement rules up to are applied as variations of the arrangement of the transistors Ta1 to Tb8. The arrangement shown in FIG. 6 is the arrangement shown in FIG. 1 in the first embodiment. First compared to
The row and the second row are interchanged. Also according to the third embodiment configured as described above, it is possible to obtain substantially the same effect as the first embodiment.

FIG. 7 shows a fourth embodiment of the present invention. When the arrangement shown in FIG. 7 is compared with the arrangement shown in FIG. 6 in the third embodiment, the third row and the fourth row are replaced with each other, and further the arrangement shown in FIG. 1 in the first embodiment is compared. That is, the first and second columns are interchanged, and the third and fourth columns are interchanged. That is, the relative positional relationship of each transistor in the fourth embodiment is
Same as the embodiment, except that the transistors Ta1-Ta2,
For Ta3-Ta4, ..., Arrangement rules are established. According to the fourth embodiment configured as described above, the first
The same effect as that of the embodiment can be obtained.

The present invention is not limited to the embodiments described above and shown in the drawings, but the following modifications and expansions are possible. In the first to fourth embodiments, the first
Also, the arrangement of the second and third columns and the arrangement of the third and fourth columns may be interchanged. Further, the arrangement of the first and second rows and the arrangement of the third and fourth rows may be exchanged. Shape of each transistor (NP
N, PNP) may be appropriately replaced according to the configuration of the operational amplifier. The operational amplifier 18 may be provided as needed.

The number of differential amplifier circuit sections may be three or more. The number of input transistors forming the input element may be three or more. Further, the arrangement of the input transistors is not limited to that shown in FIGS. 1 and 5 to 7, but the arrangement of the differential input sections of the plurality of differential amplifier circuit sections is arranged in a mixed state. Also, it may be arranged so as to be adjacent to the input transistor of the differential input section forming a pair in the differential amplifier circuit section to which it belongs, or may be arranged centrally in a predetermined arrangement area.
It is also applicable to other than the pressure detection circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing an arrangement of transistors constituting a semiconductor integrated circuit device according to a first embodiment of the present invention on a silicon substrate.

FIG. 2 is an electrical configuration diagram showing an input stage of an operational amplifier.

FIG. 3 is a diagram showing a state of stress distribution with respect to arrangement of each transistor on a silicon substrate.

FIG. 4 is an electrical configuration diagram of a differential amplifier circuit that receives an output of a pressure sensor.

FIG. 5 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 6 is a view corresponding to FIG. 1, showing a third embodiment of the present invention.

FIG. 7 is a diagram corresponding to FIG. 1 showing a fourth embodiment of the present invention.

FIG. 8 is a diagram corresponding to FIG. 2 showing a conventional technique.

FIG. 9 is a diagram corresponding to FIG. 1;

FIG. 10 is an electrical configuration diagram of a differential amplifier circuit.

[Explanation of symbols]

Reference numerals 12a and 12b denote operational amplifiers (differential amplification circuit section), T
a1, Ta2, Ta3, Ta4, Ta5, Ta6, Ta7, Ta8 and T
b1, Tb2, Tb3, Tb4, Tb5, Tb6, Tb7, Tb8 are transistors (input elements, input transistors), 21
Reference numerals a, 22a, 21b and 22b denote differential input sections, and 23 denotes a differential amplifier circuit.

Claims (5)

[Claims] 1. A semiconductor integrated circuit device in which an integrated circuit is configured to include a plurality of differential amplifier circuit sections on a semiconductor substrate, wherein each input for configuring a differential input section of the differential amplifier circuit section. A semiconductor integrated circuit device, wherein elements are concentratedly arranged in a predetermined arrangement region on the semiconductor substrate. 2. Each input element constituting the differential input section of the differential amplifier circuit section is configured by connecting a plurality of input transistors in parallel, and each of these input transistors is self-translated. 7. The semiconductor device is arranged on the semiconductor substrate so as to be adjacent to an input transistor provided corresponding to an input element of a differential input section forming a pair in the differential amplifier circuit section to which the above-mentioned belongs. 1. The semiconductor integrated circuit device according to 1. 3. The respective input elements constituting the differential input section of the differential amplifier circuit section are arranged on the semiconductor substrate in a mixed state between the differential amplifier circuit sections. The semiconductor integrated circuit device according to claim 1, which is characterized in that. 4. Each of the input elements constituting the differential input section of the differential amplifier circuit section has two adjacent input transistors of the same input element in the arrangement state on the semiconductor substrate. It is arranged so as not to be adjacent to each other, and is arranged to be adjacent to a corresponding input transistor of a different differential amplifier circuit section.
Or the semiconductor integrated circuit device according to item 3. 5. The distance between input transistors forming the same input element of each of the differential amplifier circuit sections is arranged and set on the semiconductor substrate so as to be equal to each other. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device.